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/linux/drivers/net/dsa/mv88e6xxx/
H A Dsmi.h15 /* Offset 0x00: SMI Command Register */
16 #define MV88E6XXX_SMI_CMD 0x00
17 #define MV88E6XXX_SMI_CMD_BUSY 0x8000
18 #define MV88E6XXX_SMI_CMD_MODE_MASK 0x1000
19 #define MV88E6XXX_SMI_CMD_MODE_45 0x0000
20 #define MV88E6XXX_SMI_CMD_MODE_22 0x1000
21 #define MV88E6XXX_SMI_CMD_OP_MASK 0x0c00
22 #define MV88E6XXX_SMI_CMD_OP_22_WRITE 0x0400
23 #define MV88E6XXX_SMI_CMD_OP_22_READ 0x0800
24 #define MV88E6XXX_SMI_CMD_OP_45_WRITE_ADDR 0x0000
[all …]
H A Dglobal2.h16 /* Offset 0x00: Interrupt Source Register */
17 #define MV88E6XXX_G2_INT_SRC 0x00
18 #define MV88E6XXX_G2_INT_SRC_WDOG 0x8000
19 #define MV88E6XXX_G2_INT_SRC_JAM_LIMIT 0x4000
20 #define MV88E6XXX_G2_INT_SRC_DUPLEX_MISMATCH 0x2000
21 #define MV88E6XXX_G2_INT_SRC_WAKE_EVENT 0x1000
22 #define MV88E6352_G2_INT_SRC_SERDES 0x0800
23 #define MV88E6352_G2_INT_SRC_PHY 0x001f
24 #define MV88E6390_G2_INT_SRC_PHY 0x07fe
28 /* Offset 0x01: Interrupt Mask Register */
[all …]
/linux/drivers/clk/samsung/
H A Dclk-exynos5260.h15 #define MUX_SEL_AUD 0x0200
16 #define MUX_ENABLE_AUD 0x0300
17 #define MUX_STAT_AUD 0x0400
18 #define MUX_IGNORE_AUD 0x0500
19 #define DIV_AUD0 0x0600
20 #define DIV_AUD1 0x0604
21 #define DIV_STAT_AUD0 0x0700
22 #define DIV_STAT_AUD1 0x0704
23 #define EN_ACLK_AUD 0x0800
24 #define EN_PCLK_AUD 0x0900
[all …]
/linux/arch/x86/math-emu/
H A Dcontrol_w.h20 #define CW_RC _Const_(0x0C00) /* rounding control */
21 #define CW_PC _Const_(0x0300) /* precision control */
23 #define CW_Precision Const_(0x0020) /* loss of precision mask */
24 #define CW_Underflow Const_(0x0010) /* underflow mask */
25 #define CW_Overflow Const_(0x0008) /* overflow mask */
26 #define CW_ZeroDiv Const_(0x0004) /* divide by zero mask */
27 #define CW_Denormal Const_(0x0002) /* denormalized operand mask */
28 #define CW_Invalid Const_(0x0001) /* invalid operation mask */
30 #define CW_Exceptions _Const_(0x003f) /* all masks */
32 #define RC_RND _Const_(0x0000)
[all …]
/linux/drivers/net/wireless/broadcom/brcm80211/include/
H A Dbrcmu_d11.h20 /* bit 0~7 channel number
21 * for 80+80 channels: bit 0~3 low channel id, bit 4~7 high channel id
23 #define BRCMU_CHSPEC_CH_MASK 0x00ff
24 #define BRCMU_CHSPEC_CH_SHIFT 0
25 #define BRCMU_CHSPEC_CHL_MASK 0x000f
26 #define BRCMU_CHSPEC_CHL_SHIFT 0
27 #define BRCMU_CHSPEC_CHH_MASK 0x00f0
36 #define BRCMU_CHSPEC_D11N_SB_MASK 0x0300
38 #define BRCMU_CHSPEC_D11N_SB_L 0x0100 /* control lower */
39 #define BRCMU_CHSPEC_D11N_SB_U 0x0200 /* control upper */
[all …]
H A Dbrcmu_wifi.h18 #define CH_UPPER_SB 0x01
19 #define CH_LOWER_SB 0x02
20 #define CH_EWA_VALID 0x04
32 #define BAND_2G_INDEX 0 /* wlc->bandstate[x] index */
42 #define WL_CHANSPEC_CHAN_MASK 0x00ff
43 #define WL_CHANSPEC_CHAN_SHIFT 0
45 #define WL_CHANSPEC_CTL_SB_MASK 0x0300
47 #define WL_CHANSPEC_CTL_SB_LOWER 0x0100
48 #define WL_CHANSPEC_CTL_SB_UPPER 0x0200
49 #define WL_CHANSPEC_CTL_SB_NONE 0x0300
[all …]
/linux/arch/powerpc/boot/
H A Dgamecube-head.S28 rlwinm 9, 9, 0, ~((1<<4)|(1<<5)) /* MSR_DR|MSR_IR */
42 li 8, 0
43 mtspr 0x210, 8 /* IBAT0U */
44 mtspr 0x212, 8 /* IBAT1U */
45 mtspr 0x214, 8 /* IBAT2U */
46 mtspr 0x216, 8 /* IBAT3U */
47 mtspr 0x218, 8 /* DBAT0U */
48 mtspr 0x21a, 8 /* DBAT1U */
49 mtspr 0x21c, 8 /* DBAT2U */
50 mtspr 0x21e, 8 /* DBAT3U */
[all …]
H A Dwii-head.S29 rlwinm 9, 9, 0, ~((1<<4)|(1<<5)) /* MSR_DR|MSR_IR */
43 li 8, 0
44 mtspr 0x210, 8 /* IBAT0U */
45 mtspr 0x212, 8 /* IBAT1U */
46 mtspr 0x214, 8 /* IBAT2U */
47 mtspr 0x216, 8 /* IBAT3U */
48 mtspr 0x218, 8 /* DBAT0U */
49 mtspr 0x21a, 8 /* DBAT1U */
50 mtspr 0x21c, 8 /* DBAT2U */
51 mtspr 0x21e, 8 /* DBAT3U */
[all …]
/linux/sound/soc/codecs/
H A Dtfa9879.h12 #define TFA9879_DEVICE_CONTROL 0x00
13 #define TFA9879_SERIAL_INTERFACE_1 0x01
14 #define TFA9879_PCM_IOM2_FORMAT_1 0x02
15 #define TFA9879_SERIAL_INTERFACE_2 0x03
16 #define TFA9879_PCM_IOM2_FORMAT_2 0x04
17 #define TFA9879_EQUALIZER_A1 0x05
18 #define TFA9879_EQUALIZER_A2 0x06
19 #define TFA9879_EQUALIZER_B1 0x07
20 #define TFA9879_EQUALIZER_B2 0x08
21 #define TFA9879_EQUALIZER_C1 0x09
[all …]
/linux/net/nfc/
H A Ddigital_technology.c11 #define DIGITAL_CMD_SENS_REQ 0x26
12 #define DIGITAL_CMD_ALL_REQ 0x52
13 #define DIGITAL_CMD_SEL_REQ_CL1 0x93
14 #define DIGITAL_CMD_SEL_REQ_CL2 0x95
15 #define DIGITAL_CMD_SEL_REQ_CL3 0x97
17 #define DIGITAL_SDD_REQ_SEL_PAR 0x20
19 #define DIGITAL_SDD_RES_CT 0x88
23 #define DIGITAL_SEL_RES_NFCID1_COMPLETE(sel_res) (!((sel_res) & 0x04))
24 #define DIGITAL_SEL_RES_IS_T2T(sel_res) (!((sel_res) & 0x60))
25 #define DIGITAL_SEL_RES_IS_T4T(sel_res) ((sel_res) & 0x20)
[all …]
/linux/arch/arm/mach-omap2/
H A Dprcm43xx.h15 #define AM43XX_PRM_OCP_SOCKET_INST 0x0000
16 #define AM43XX_PRM_MPU_INST 0x0300
17 #define AM43XX_PRM_GFX_INST 0x0400
18 #define AM43XX_PRM_RTC_INST 0x0500
19 #define AM43XX_PRM_TAMPER_INST 0x0600
20 #define AM43XX_PRM_CEFUSE_INST 0x0700
21 #define AM43XX_PRM_PER_INST 0x0800
22 #define AM43XX_PRM_WKUP_INST 0x2000
23 #define AM43XX_PRM_DEVICE_INST 0x4000
26 #define AM43XX_PRM_IRQSTATUS_MPU_OFFSET 0x0004
[all …]
H A Dprm33xx.h14 #define AM33XX_PRM_BASE 0x44E00000
21 #define AM33XX_PRM_OCP_SOCKET_MOD 0x0B00
22 #define AM33XX_PRM_PER_MOD 0x0C00
23 #define AM33XX_PRM_WKUP_MOD 0x0D00
24 #define AM33XX_PRM_MPU_MOD 0x0E00
25 #define AM33XX_PRM_DEVICE_MOD 0x0F00
26 #define AM33XX_PRM_RTC_MOD 0x1000
27 #define AM33XX_PRM_GFX_MOD 0x1100
28 #define AM33XX_PRM_CEFUSE_MOD 0x1200
31 #define AM33XX_PM_PER_PWRSTST_OFFSET 0x0008
[all …]
/linux/include/linux/mfd/madera/
H A Dregisters.h14 #define MADERA_SOFTWARE_RESET 0x00
15 #define MADERA_HARDWARE_REVISION 0x01
16 #define MADERA_CTRL_IF_CFG_1 0x08
17 #define MADERA_CTRL_IF_CFG_2 0x09
18 #define MADERA_CTRL_IF_CFG_3 0x0A
19 #define MADERA_WRITE_SEQUENCER_CTRL_0 0x16
20 #define MADERA_WRITE_SEQUENCER_CTRL_1 0x17
21 #define MADERA_WRITE_SEQUENCER_CTRL_2 0x18
22 #define MADERA_TONE_GENERATOR_1 0x20
23 #define MADERA_TONE_GENERATOR_2 0x21
[all …]
/linux/drivers/phy/marvell/
H A Dphy-berlin-sata.c17 #define HOST_VSA_ADDR 0x0
18 #define HOST_VSA_DATA 0x4
19 #define PORT_SCR_CTL 0x2c
20 #define PORT_VSR_ADDR 0x78
21 #define PORT_VSR_DATA 0x7c
23 #define CONTROL_REGISTER 0x0
24 #define MBUS_SIZE_CONTROL 0x4
31 #define BG2_PHY_BASE 0x080
32 #define BG2Q_PHY_BASE 0x200
34 /* register 0x01 */
[all …]
/linux/drivers/net/ethernet/qualcomm/
H A Dqca_7k.h21 #define QCA7K_SPI_WRITE (0 << 15)
23 #define QCA7K_SPI_EXTERNAL (0 << 14)
27 #define QCASPI_HW_BUF_LEN 0xC5B
30 #define SPI_REG_BFR_SIZE 0x0100
31 #define SPI_REG_WRBUF_SPC_AVA 0x0200
32 #define SPI_REG_RDBUF_BYTE_AVA 0x0300
33 #define SPI_REG_SPI_CONFIG 0x0400
34 #define SPI_REG_SPI_STATUS 0x0500
35 #define SPI_REG_INTR_CAUSE 0x0C00
36 #define SPI_REG_INTR_ENABLE 0x0D00
[all …]
/linux/drivers/net/ethernet/intel/ice/
H A Dice_sbq_cmd.h14 ice_sbq_opc_neigh_dev_req = 0x0C00,
15 ice_sbq_opc_neigh_dev_ev = 0x0C01
50 eth56g_phy_0 = 0x02,
51 rmn_0 = 0x02,
52 rmn_1 = 0x03,
53 rmn_2 = 0x04,
54 cgu = 0x06,
55 eth56g_phy_1 = 0x0D,
59 ice_sbq_msg_rd = 0x00,
60 ice_sbq_msg_wr = 0x01
[all …]
/linux/drivers/media/dvb-frontends/
H A Datbm8830_priv.h19 #define REG_CHIP_ID 0x0000
20 #define REG_TUNER_BASEBAND 0x0001
21 #define REG_DEMOD_RUN 0x0004
22 #define REG_DSP_RESET 0x0005
23 #define REG_RAM_RESET 0x0006
24 #define REG_ADC_RESET 0x0007
25 #define REG_TSPORT_RESET 0x0008
26 #define REG_BLKERR_POL 0x000C
27 #define REG_I2C_GATE 0x0103
28 #define REG_TS_SAMPLE_EDGE 0x0301
[all …]
/linux/arch/csky/kernel/probes/
H A Dsimulate-insn.h20 } while (0)
22 __CSKY_INSN_FUNCS(br16, 0xfc00, 0x0400)
23 __CSKY_INSN_FUNCS(bt16, 0xfc00, 0x0800)
24 __CSKY_INSN_FUNCS(bf16, 0xfc00, 0x0c00)
25 __CSKY_INSN_FUNCS(jmp16, 0xffc3, 0x7800)
26 __CSKY_INSN_FUNCS(jsr16, 0xffc3, 0x7801)
27 __CSKY_INSN_FUNCS(lrw16, 0xfc00, 0x1000)
28 __CSKY_INSN_FUNCS(pop16, 0xffe0, 0x1480)
30 __CSKY_INSN_FUNCS(br32, 0x0000ffff, 0x0000e800)
31 __CSKY_INSN_FUNCS(bt32, 0x0000ffff, 0x0000e860)
[all …]
/linux/arch/arm/mach-imx/
H A Diim.h11 #define MXC_IIMSTAT 0x0000
12 #define MXC_IIMSTATM 0x0004
13 #define MXC_IIMERR 0x0008
14 #define MXC_IIMEMASK 0x000C
15 #define MXC_IIMFCTL 0x0010
16 #define MXC_IIMUA 0x0014
17 #define MXC_IIMLA 0x0018
18 #define MXC_IIMSDAT 0x001C
19 #define MXC_IIMPREV 0x0020
20 #define MXC_IIMSREV 0x0024
[all …]
/linux/Documentation/devicetree/bindings/mmc/
H A Dcavium-mmc.txt34 reg = <0x0c00 0 0 0 0>; /* DEVFN = 0x0c (1:4) */
36 #size-cells = <0>;
39 mmc-slot@0 {
41 reg = <0>;
/linux/drivers/net/ethernet/marvell/octeontx2/af/
H A Drvu_reg.c30 {NIX_TXSCH_LVL_SMQ, 2, 0xFFFF, {{0x0700, 0x0708}, {0x1400, 0x14C8} } },
31 {NIX_TXSCH_LVL_TL4, 3, 0xFFFF, {{0x0B00, 0x0B08}, {0x0B10, 0x0B18},
32 {0x1200, 0x12E0} } },
33 {NIX_TXSCH_LVL_TL3, 4, 0xFFFF, {{0x1000, 0x10E0}, {0x1600, 0x1608},
34 {0x1610, 0x1618}, {0x1700, 0x17C8} } },
35 {NIX_TXSCH_LVL_TL2, 2, 0xFFFF, {{0x0E00, 0x0EE0}, {0x1700, 0x17C8} } },
36 {NIX_TXSCH_LVL_TL1, 1, 0xFFFF, {{0x0C00, 0x0D98} } },
45 if (reg & 0x07) in rvu_check_valid_reg()
62 for (idx = 0; idx < map->num_ranges; idx++) { in rvu_check_valid_reg()
/linux/arch/powerpc/include/asm/
H A Dcell-regs.h28 #define HID0_CBE_THERM_WAKEUP 0x0000020000000000ul
29 #define HID0_CBE_SYSERR_WAKEUP 0x0000008000000000ul
30 #define HID0_CBE_THERM_INT_EN 0x0000000400000000ul
31 #define HID0_CBE_SYSERR_INT_EN 0x0000000200000000ul
57 u64 pad_0x0000; /* 0x0000 */
59 u64 group_control; /* 0x0008 */
61 u8 pad_0x0010_0x00a8 [0x00a8 - 0x0010]; /* 0x0010 */
63 u64 debug_bus_control; /* 0x00a8 */
65 u8 pad_0x00b0_0x0100 [0x0100 - 0x00b0]; /* 0x00b0 */
67 u64 trace_aux_data; /* 0x0100 */
[all …]
/linux/include/soc/fsl/qe/
H A Dqe_tdm.h25 #define SIR_LAST 0x0001
26 #define SIR_BYTE 0x0002
29 #define SIR_SGS 0x0200
30 #define SIR_SWTR 0x4000
31 #define SIR_MCC 0x8000
32 #define SIR_IDLE 0
36 #define SIMR_SDM_NORMAL 0x0000
37 #define SIMR_SDM_INTERNAL_LOOPBACK 0x0800
38 #define SIMR_SDM_MASK 0x0c00
39 #define SIMR_CRT 0x0040
[all …]
/linux/drivers/media/i2c/
H A Dtc358743_regs.h19 #define CHIPID 0x0000
20 #define MASK_CHIPID 0xff00
21 #define MASK_REVID 0x00ff
23 #define SYSCTL 0x0002
24 #define MASK_IRRST 0x0800
25 #define MASK_CECRST 0x0400
26 #define MASK_CTXRST 0x0200
27 #define MASK_HDMIRST 0x0100
28 #define MASK_SLEEP 0x0001
30 #define CONFCTL 0x0004
[all …]
/linux/drivers/net/dsa/microchip/
H A Dksz_ptp_reg.h9 #define REG_SW_GLOBAL_LED_OVR__4 0x0120
11 #define LED_OVR_1 BIT(0)
13 #define REG_SW_GLOBAL_LED_SRC__4 0x0128
18 #define REG_PTP_CLK_CTRL 0x0500
26 #define PTP_CLK_RESET BIT(0)
28 #define REG_PTP_RTC_SUB_NANOSEC__2 0x0502
30 #define PTP_RTC_SUB_NANOSEC_M 0x0007
31 #define PTP_RTC_0NS 0x00
33 #define REG_PTP_RTC_NANOSEC 0x0504
35 #define REG_PTP_RTC_SEC 0x0508
[all …]

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