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Searched +full:0 +full:x0af00000 (Results 1 – 6 of 6) sorted by relevance

/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,sa8775p-dispcc.yaml61 reg = <0x0af00000 0x20000>;
66 <&dp_phy0 0>,
70 <&dsi_phy0 0>,
H A Dqcom,dispcc-sc8280xp.yaml30 - description: DisplayPort 0 link clock
31 - description: DisplayPort 0 VCO div clock
38 - description: DSI 0 PLL byte clock
39 - description: DSI 0 PLL DSI clock
64 reg = <0x0af00000 0x20000>;
68 <&mdss0_dp_phy0 0>,
70 <&mdss0_dp_phy1 0>,
72 <&mdss0_dp_phy2 0>,
74 <&mdss0_dp_phy3 0>,
76 <&mdss0_dsi0_phy 0>,
[all …]
H A Dqcom,glymur-dispcc.yaml28 - description: DisplayPort 0 link clock
29 - description: DisplayPort 0 VCO div clock
36 - description: DSI 0 PLL byte clock
37 - description: DSI 0 PLL DSI clock
40 - description: Standalone PHY 0 PLL link clock
41 - description: Standalone PHY 0 VCO div clock
73 reg = <0x0af00000 0x20000>;
76 <&mdss_dp_phy0 0>,
78 <&mdss_dp_phy1 0>,
80 <&mdss_dp_phy2 0>,
[all …]
H A Dqcom,dispcc-sm8x50.yaml102 reg = <0x0af00000 0x10000>;
104 <&dsi0_phy 0>,
106 <&dsi1_phy 0>,
108 <&dp_phy 0>,
/linux/arch/arm64/boot/dts/qcom/
H A Dsm4450.dtsi29 #clock-cells = <0>;
35 #clock-cells = <0>;
39 #clock-cells = <0>;
49 #size-cells = <0>;
51 cpu0: cpu@0 {
54 reg = <0x0 0x0>;
55 clocks = <&cpufreq_hw 0>;
60 qcom,freq-domain = <&cpufreq_hw 0>;
80 reg = <0x0 0x100>;
81 clocks = <&cpufreq_hw 0>;
[all …]
H A Dsdm670.dtsi37 #clock-cells = <0>;
43 #clock-cells = <0>;
50 #size-cells = <0>;
52 cpu0: cpu@0 {
55 reg = <0x0 0x0>;
59 qcom,freq-domain = <&cpufreq_hw 0>;
82 reg = <0x0 0x100>;
86 qcom,freq-domain = <&cpufreq_hw 0>;
104 reg = <0x0 0x200>;
108 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]