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/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dqcom,qcs615-dispcc.yaml43 reg = <0x0af00000 0x20000>;
46 <&mdss_dsi0_phy 0>,
48 <&mdss_dsi1_phy 0>,
49 <&mdss_dp_phy 0>,
50 <&mdss_dp_vco 0>;
H A Dqcom,milos-dispcc.yaml49 reg = <0x0af00000 0x20000>;
54 <&mdss_dsi0_phy 0>,
H A Dqcom,sm4450-dispcc.yaml48 reg = <0x0af00000 0x20000>;
H A Dqcom,sc7180-dispcc.yaml57 reg = <0x0af00000 0x200000>;
60 <&dsi_phy 0>,
62 <&dp_phy 0>,
H A Dqcom,dispcc-sm6350.yaml57 reg = <0x0af00000 0x20000>;
60 <&dsi_phy 0>,
62 <&dp_phy 0>,
H A Dqcom,sc7280-dispcc.yaml61 reg = <0x0af00000 0x200000>;
64 <&dsi_phy 0>,
66 <&dp_phy 0>,
68 <&edp_phy 0>,
H A Dqcom,sm7150-dispcc.yaml59 reg = <0x0af00000 0x200000>;
64 <&mdss_dsi0_phy 0>,
66 <&mdss_dsi1_phy 0>,
68 <&dp_phy 0>,
H A Dqcom,sdm845-dispcc.yaml66 reg = <0x0af00000 0x10000>;
70 <&dsi0_phy 0>,
72 <&dsi1_phy 0>,
74 <&dp_phy 0>,
H A Dqcom,sa8775p-dispcc.yaml61 reg = <0x0af00000 0x20000>;
66 <&dp_phy0 0>,
70 <&dsi_phy0 0>,
H A Dqcom,dispcc-sc8280xp.yaml30 - description: DisplayPort 0 link clock
31 - description: DisplayPort 0 VCO div clock
38 - description: DSI 0 PLL byte clock
39 - description: DSI 0 PLL DSI clock
64 reg = <0x0af00000 0x20000>;
68 <&mdss0_dp_phy0 0>,
70 <&mdss0_dp_phy1 0>,
72 <&mdss0_dp_phy2 0>,
74 <&mdss0_dp_phy3 0>,
76 <&mdss0_dsi0_phy 0>,
[all …]
H A Dqcom,sm8450-dispcc.yaml71 reg = <0x0af00000 0x10000>;
76 <&dsi0_phy 0>,
78 <&dsi1_phy 0>,
H A Dqcom,sm8550-dispcc.yaml78 reg = <0x0af00000 0x10000>;
83 <&dsi0_phy 0>,
85 <&dsi1_phy 0>,
87 <&dp0_phy 0>,
89 <&dp1_phy 0>,
91 <&dp2_phy 0>,
93 <&dp3_phy 0>,
H A Dqcom,dispcc-sm8x50.yaml102 reg = <0x0af00000 0x10000>;
104 <&dsi0_phy 0>,
106 <&dsi1_phy 0>,
108 <&dp_phy 0>,
/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dsm4450.dtsi29 #clock-cells = <0>;
35 #clock-cells = <0>;
39 #clock-cells = <0>;
49 #size-cells = <0>;
51 cpu0: cpu@0 {
54 reg = <0x0 0x0>;
55 clocks = <&cpufreq_hw 0>;
60 qcom,freq-domain = <&cpufreq_hw 0>;
80 reg = <0x0 0x100>;
81 clocks = <&cpufreq_hw 0>;
[all …]
H A Dsdm670.dtsi37 #clock-cells = <0>;
43 #clock-cells = <0>;
50 #size-cells = <0>;
52 cpu0: cpu@0 {
55 reg = <0x0 0x0>;
59 qcom,freq-domain = <&cpufreq_hw 0>;
82 reg = <0x0 0x100>;
86 qcom,freq-domain = <&cpufreq_hw 0>;
104 reg = <0x0 0x200>;
108 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dsm6350.dtsi35 #clock-cells = <0>;
43 #clock-cells = <0>;
49 #size-cells = <0>;
51 cpu0: cpu@0 {
54 reg = <0x0 0x0>;
55 clocks = <&cpufreq_hw 0>;
60 qcom,freq-domain = <&cpufreq_hw 0>;
84 reg = <0x0 0x100>;
85 clocks = <&cpufreq_hw 0>;
90 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dsar2130p.dtsi34 #clock-cells = <0>;
40 #clock-cells = <0>;
47 #size-cells = <0>;
49 cpu0: cpu@0 {
52 reg = <0x0 0x0>;
53 clocks = <&cpufreq_hw 0>;
56 qcom,freq-domain = <&cpufreq_hw 0>;
78 reg = <0x0 0x100>;
79 clocks = <&cpufreq_hw 0>;
82 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dsc8180x.dtsi31 #clock-cells = <0>;
37 #clock-cells = <0>;
45 #size-cells = <0>;
47 cpu0: cpu@0 {
50 reg = <0x0 0x0>;
54 qcom,freq-domain = <&cpufreq_hw 0>;
61 clocks = <&cpufreq_hw 0>;
79 reg = <0x0 0x100>;
83 qcom,freq-domain = <&cpufreq_hw 0>;
90 clocks = <&cpufreq_hw 0>;
[all …]
H A Dsm8350.dtsi40 #clock-cells = <0>;
48 #clock-cells = <0>;
54 #size-cells = <0>;
56 cpu0: cpu@0 {
59 reg = <0x0 0x0>;
60 clocks = <&cpufreq_hw 0>;
63 qcom,freq-domain = <&cpufreq_hw 0>;
83 reg = <0x0 0x100>;
84 clocks = <&cpufreq_hw 0>;
87 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dsc7180.dtsi67 #clock-cells = <0>;
73 #clock-cells = <0>;
79 #size-cells = <0>;
81 cpu0: cpu@0 {
84 reg = <0x0 0x0>;
85 clocks = <&cpufreq_hw 0>;
96 qcom,freq-domain = <&cpufreq_hw 0>;
113 reg = <0x0 0x100>;
114 clocks = <&cpufreq_hw 0>;
125 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dsm8150.dtsi35 #clock-cells = <0>;
42 #clock-cells = <0>;
50 #size-cells = <0>;
52 cpu0: cpu@0 {
55 reg = <0x0 0x0>;
56 clocks = <&cpufreq_hw 0>;
61 qcom,freq-domain = <&cpufreq_hw 0>;
63 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
84 reg = <0x0 0x100>;
85 clocks = <&cpufreq_hw 0>;
[all …]
H A Dqcs8300.dtsi30 #clock-cells = <0>;
36 #clock-cells = <0>;
43 #size-cells = <0>;
45 cpu0: cpu@0 {
48 reg = <0x0 0x0>;
55 qcom,freq-domain = <&cpufreq_hw 0>;
68 reg = <0x0 0x100>;
75 qcom,freq-domain = <&cpufreq_hw 0>;
88 reg = <0x0 0x200>;
108 reg = <0x0 0x300>;
[all …]
H A Dsm8450.dtsi40 #clock-cells = <0>;
46 #clock-cells = <0>;
53 #size-cells = <0>;
55 cpu0: cpu@0 {
58 reg = <0x0 0x0>;
63 qcom,freq-domain = <&cpufreq_hw 0>;
65 clocks = <&cpufreq_hw 0>;
82 reg = <0x0 0x100>;
87 qcom,freq-domain = <&cpufreq_hw 0>;
89 clocks = <&cpufreq_hw 0>;
[all …]
H A Dsdm845.dtsi79 #clock-cells = <0>;
86 #clock-cells = <0>;
93 #size-cells = <0>;
95 cpu0: cpu@0 {
98 reg = <0x0 0x0>;
99 clocks = <&cpufreq_hw 0>;
103 qcom,freq-domain = <&cpufreq_hw 0>;
127 reg = <0x0 0x100>;
128 clocks = <&cpufreq_hw 0>;
132 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dsc8280xp.dtsi33 #clock-cells = <0>;
38 #clock-cells = <0>;
45 #size-cells = <0>;
47 cpu0: cpu@0 {
50 reg = <0x0 0x0>;
51 clocks = <&cpufreq_hw 0>;
58 qcom,freq-domain = <&cpufreq_hw 0>;
78 reg = <0x0 0x100>;
79 clocks = <&cpufreq_hw 0>;
86 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]

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