| /freebsd/sys/contrib/device-tree/Bindings/display/msm/ |
| H A D | qcom,sm6350-mdss.yaml | 48 "^display-controller@[0-9a-f]+$":
56 "^displayport-controller@[0-9a-f]+$":
65 "^dsi@[0-9a-f]+$":
75 "^phy@[0-9a-f]+$":
95 reg = <0x0ae00000 0x1000>;
109 iommus = <&apps_smmu 0x800 0x2>;
116 reg = <0x0ae01000 0x8f000>,
117 <0x0aeb0000 0x2008>;
139 interrupts = <0>;
145 #size-cells = <0>;
[all …]
|
| H A D | qcom,sm6150-mdss.yaml | 47 "^display-controller@[0-9a-f]+$":
54 "^dsi@[0-9a-f]+$":
63 "^phy@[0-9a-f]+$":
84 reg = <0x0ae00000 0x1000>;
103 iommus = <&apps_smmu 0x800 0x0>;
109 reg = <0x0ae01000 0x8f000>,
110 <0x0aeb0000 0x2008>;
126 interrupts = <0>;
130 #size-cells = <0>;
132 port@0 {
[all …]
|
| H A D | qcom,sm8350-mdss.yaml | 53 "^display-controller@[0-9a-f]+$":
61 "^displayport-controller@[0-9a-f]+$":
69 "^dsi@[0-9a-f]+$":
79 "^phy@[0-9a-f]+$":
101 reg = <0x0ae00000 0x1000>;
104 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
105 <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>,
119 iommus = <&apps_smmu 0x820 0x402>;
131 reg = <0x0ae01000 0x8f000>,
132 <0x0aeb0000 0x2008>;
[all …]
|
| H A D | qcom,sdm845-mdss.yaml | 43 "^display-controller@[0-9a-f]+$":
51 "^displayport-controller@[0-9a-f]+$":
59 "^dsi@[0-9a-f]+$":
69 "^phy@[0-9a-f]+$":
94 reg = <0x0ae00000 0x1000>;
106 iommus = <&apps_smmu 0x880 0x8>,
107 <&apps_smmu 0xc80 0x
[all...] |
| H A D | qcom,sc7180-mdss.yaml | 49 "^display-controller@[0-9a-f]+$":
57 "^displayport-controller@[0-9a-f]+$":
65 "^dsi@[0-9a-f]+$":
75 "^phy@[0-9a-f]+$":
101 reg = <0xae00000 0x1000>;
118 iommus = <&apps_smmu 0x800 0x2>;
123 reg = <0x0ae01000 0x8f00
[all...] |
| H A D | qcom,sm8650-mdss.yaml | 42 "^display-controller@[0-9a-f]+$":
49 "^displayport-controller@[0-9a-f]+$":
56 "^dsi@[0-9a-f]+$":
65 "^phy@[0-9a-f]+$":
86 reg = <0x0ae00000 0x1000>;
89 interconnects = <&mmss_noc MASTER_MDP 0 &mc_virt SLAVE_EBI1 0>,
90 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_DISPLAY_CFG 0>;
106 iommus = <&apps_smmu 0x1c00 0x2>;
114 reg = <0x0ae01000 0x8f000>,
115 <0x0aeb0000 0x2008>;
[all …]
|
| H A D | qcom,sm8450-mdss.yaml | 39 "^display-controller@[0-9a-f]+$":
47 "^displayport-controller@[0-9a-f]+$":
57 "^dsi@[0-9a-f]+$":
67 "^phy@[0-9a-f]+$":
91 reg = <0x0ae00000 0x1000>;
115 iommus = <&apps_smmu 0x2800 0x402>;
123 reg = <0x0ae01000 0x8f00
[all...] |
| H A D | qcom,sm8150-mdss.yaml | 48 "^display-controller@[0-9a-f]+$":
56 "^displayport-controller@[0-9a-f]+$":
65 "^dsi@[0-9a-f]+$":
75 "^phy@[0-9a-f]+$":
96 reg = <0x0ae00000 0x1000>;
115 iommus = <&apps_smmu 0x800 0x420>;
123 reg = <0x0ae01000 0x8f000>,
124 <0x0aeb0000 0x2008>;
140 interrupts = <0>;
144 #size-cells = <0>;
[all …]
|
| H A D | qcom,sm8250-mdss.yaml | 47 "^display-controller@[0-9a-f]+$":
55 "^displayport-controller@[0-9a-f]+$":
65 "^dsi@[0-9a-f]+$":
75 "^phy@[0-9a-f]+$":
99 reg = <0x0ae00000 0x1000>;
118 iommus = <&apps_smmu 0x820 0x402>;
126 reg = <0x0ae01000 0x8f00
[all...] |
| H A D | qcom,sm8550-mdss.yaml | 43 "^display-controller@[0-9a-f]+$":
51 "^displayport-controller@[0-9a-f]+$":
61 "^dsi@[0-9a-f]+$":
71 "^phy@[0-9a-f]+$":
95 reg = <0x0ae00000 0x1000>;
98 interconnects = <&mmss_noc MASTER_MDP 0 &mc_virt SLAVE_EBI1 0>,
99 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_DISPLAY_CFG 0>;
116 iommus = <&apps_smmu 0x1c00 0x2>;
124 reg = <0x0ae01000 0x8f000>,
125 <0x0aeb0000 0x2008>;
[all …]
|
| H A D | qcom,sa8775p-mdss.yaml | 38 "^display-controller@[0-9a-f]+$":
46 "^displayport-controller@[0-9a-f]+$":
55 "^dsi@[0-9a-f]+$":
63 "^phy@[0-9a-f]+$":
90 reg = <0x0ae00000 0x1000>;
111 iommus = <&apps_smmu 0x1000 0x402>;
119 reg = <0x0ae01000 0x8f000>,
120 <0x0aeb0000 0x2008>;
141 interrupts = <0>;
145 #size-cells = <0>;
[all …]
|
| H A D | qcom,sc7280-mdss.yaml | 49 "^display-controller@[0-9a-f]+$":
57 "^displayport-controller@[0-9a-f]+$":
65 "^dsi@[0-9a-f]+$":
75 "^edp@[0-9a-f]+$":
83 "^phy@[0-9a-f]+$":
111 reg = <0xae00000 0x1000>;
130 iommus = <&apps_smmu 0x900 0x402>;
135 reg = <0x0ae0100
[all...] |
| H A D | qcom,sm7150-mdss.yaml | 52 "^display-controller@[0-9a-f]+$":
59 "^displayport-controller@[0-9a-f]+$":
66 "^dsi@[0-9a-f]+$":
75 "^phy@[0-9a-f]+$":
97 reg = <0x0ae00000 0x1000>;
125 iommus = <&apps_smmu 0x800 0x440>;
133 reg = <0x0ae01000 0x8f000>,
134 <0x0aeb0000 0x2008>;
157 interrupts = <0>;
161 #size-cells = <0>;
[all …]
|
| H A D | qcom,sm8750-mdss.yaml | 42 "^display-controller@[0-9a-f]+$":
49 "^displayport-controller@[0-9a-f]+$":
57 "^dsi@[0-9a-f]+$":
65 "^phy@[0-9a-f]+$":
88 reg = <0x0ae00000 0x1000>;
108 iommus = <&apps_smmu 0x800 0x2>;
119 reg = <0x0ae01000 0x93000>,
120 <0x0aeb0000 0x2008>;
124 interrupts-extended = <&mdss 0>;
146 #size-cells = <0>;
[all …]
|
| H A D | qcom,sar2130p-mdss.yaml | 43 "^display-controller@[0-9a-f]+$":
50 "^displayport-controller@[0-9a-f]+$":
58 "^dsi@[0-9a-f]+$":
66 "^phy@[0-9a-f]+$":
86 reg = <0x0ae00000 0x1000>;
107 iommus = <&apps_smmu 0x1c00 0x2>;
115 reg = <0x0ae01000 0x8f000>,
116 <0x0aeb0000 0x2008>;
139 interrupts = <0>;
143 #size-cells = <0>;
[all …]
|
| H A D | dsi-controller-main.yaml | 139 port@0:
153 enum: [ 0, 1, 2, 3 ]
169 enum: [ 0, 1, 2, 3 ]
188 - port@0
428 reg = <0x0ae94000 0x400>;
432 #size-cells = <0>;
454 assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>;
461 #size-cells = <0>;
463 port@0 {
464 reg = <0>;
[all …]
|
| /freebsd/sys/contrib/device-tree/src/arm64/qcom/ |
| H A D | sdm670.dtsi | 37 #clock-cells = <0>;
43 #clock-cells = <0>;
50 #size-cells = <0>;
52 cpu0: cpu@0 {
55 reg = <0x0 0x0>;
59 qcom,freq-domain = <&cpufreq_hw 0>;
82 reg = <0x0 0x100>;
86 qcom,freq-domain = <&cpufreq_hw 0>;
104 reg = <0x0 0x200>;
108 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
|
| H A D | sm6350.dtsi | 35 #clock-cells = <0>;
43 #clock-cells = <0>;
49 #size-cells = <0>;
51 cpu0: cpu@0 {
54 reg = <0x0 0x0>;
55 clocks = <&cpufreq_hw 0>;
60 qcom,freq-domain = <&cpufreq_hw 0>;
84 reg = <0x0 0x100>;
85 clocks = <&cpufreq_hw 0>;
90 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
|
| H A D | sar2130p.dtsi | 34 #clock-cells = <0>;
40 #clock-cells = <0>;
47 #size-cells = <0>;
49 cpu0: cpu@0 {
52 reg = <0x0 0x0>;
53 clocks = <&cpufreq_hw 0>;
56 qcom,freq-domain = <&cpufreq_hw 0>;
78 reg = <0x0 0x100>;
79 clocks = <&cpufreq_hw 0>;
82 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
|
| H A D | sc8180x.dtsi | 31 #clock-cells = <0>;
37 #clock-cells = <0>;
45 #size-cells = <0>;
47 cpu0: cpu@0 {
50 reg = <0x0 0x0>;
54 qcom,freq-domain = <&cpufreq_hw 0>;
61 clocks = <&cpufreq_hw 0>;
79 reg = <0x0 0x100>;
83 qcom,freq-domain = <&cpufreq_hw 0>;
90 clocks = <&cpufreq_hw 0>;
[all …]
|
| H A D | sm8350.dtsi | 40 #clock-cells = <0>;
48 #clock-cells = <0>;
54 #size-cells = <0>;
56 cpu0: cpu@0 {
59 reg = <0x0 0x0>;
60 clocks = <&cpufreq_hw 0>;
63 qcom,freq-domain = <&cpufreq_hw 0>;
83 reg = <0x0 0x100>;
84 clocks = <&cpufreq_hw 0>;
87 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
|
| H A D | sc7180.dtsi | 67 #clock-cells = <0>;
73 #clock-cells = <0>;
79 #size-cells = <0>;
81 cpu0: cpu@0 {
84 reg = <0x0 0x0>;
85 clocks = <&cpufreq_hw 0>;
96 qcom,freq-domain = <&cpufreq_hw 0>;
113 reg = <0x0 0x100>;
114 clocks = <&cpufreq_hw 0>;
125 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
|
| H A D | sm8150.dtsi | 35 #clock-cells = <0>;
42 #clock-cells = <0>;
50 #size-cells = <0>;
52 cpu0: cpu@0 {
55 reg = <0x0 0x0>;
56 clocks = <&cpufreq_hw 0>;
61 qcom,freq-domain = <&cpufreq_hw 0>;
63 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
84 reg = <0x0 0x100>;
85 clocks = <&cpufreq_hw 0>;
[all …]
|
| H A D | sm8450.dtsi | 40 #clock-cells = <0>;
46 #clock-cells = <0>;
53 #size-cells = <0>;
55 cpu0: cpu@0 {
58 reg = <0x0 0x0>;
63 qcom,freq-domain = <&cpufreq_hw 0>;
65 clocks = <&cpufreq_hw 0>;
82 reg = <0x0 0x100>;
87 qcom,freq-domain = <&cpufreq_hw 0>;
89 clocks = <&cpufreq_hw 0>;
[all …]
|
| H A D | sdm845.dtsi | 79 #clock-cells = <0>;
86 #clock-cells = <0>;
93 #size-cells = <0>;
95 cpu0: cpu@0 {
98 reg = <0x0 0x0>;
99 clocks = <&cpufreq_hw 0>;
103 qcom,freq-domain = <&cpufreq_hw 0>;
127 reg = <0x0 0x100>;
128 clocks = <&cpufreq_hw 0>;
132 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
|