Lines Matching +full:0 +full:x0ae94000
134 port@0:148 enum: [ 0, 1, 2, 3 ]164 enum: [ 0, 1, 2, 3 ]183 - port@0426 reg = <0x0ae94000 0x400>;430 #size-cells = <0>;452 assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>;459 #size-cells = <0>;461 port@0 {462 reg = <0>;472 data-lanes = <0 1 2 3>;