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/linux/Documentation/devicetree/bindings/net/
H A Dmdio-mux-gpio.yaml44 gpios = <&gpio1 3 0>, <&gpio1 4 0>;
47 #size-cells = <0>;
52 #size-cells = <0>;
56 marvell,reg-init = <3 0x10 0 0x5777>,
57 <3 0x11 0 0x00aa>,
58 <3 0x12 0 0x4105>,
59 <3 0x13 0 0x0a60>;
65 marvell,reg-init = <3 0x10 0 0x5777>,
66 <3 0x11 0 0x00aa>,
67 <3 0x12 0 0x4105>,
[all …]
/linux/arch/mips/boot/dts/cavium-octeon/
H A Docteon_3xxx.dts13 soc@0 {
15 phy0: ethernet-phy@0 {
19 <2 0x15 0xffcf 0>, /* Reg 2,21 Clear bits 4, 5 */
21 <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */
23 <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */
24 reg = <0>;
31 <2 0x15 0xffcf 0>, /* Reg 2,21 Clear bits 4, 5 */
33 <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */
35 <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */
42 marvell,reg-init = <3 0x10 0 0x5777>,
[all …]
H A Docteon_68xx.dts16 soc@0 {
26 * 1) Controller register (0 or 7)
27 * 2) Bit within the register (0..63)
29 #address-cells = <0>;
31 reg = <0x10701 0x00000000 0x0 0x4000000>;
37 reg = <0x10700 0x00000800 0x0 0x100>;
40 * 1) GPIO pin number (0..15)
49 interrupts = <7 0>, <7 1>, <7 2>, <7 3>,
58 #size-cells = <0>;
59 reg = <0x11800 0x00003800 0x0 0x40>;
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/vce/
H A Dvce_4_0_offset.h27 // base address: 0x22000
28 …VCE_STATUS 0x0a01
29 …ne mmVCE_STATUS_BASE_IDX 0
30 …VCE_VCPU_CNTL 0x0a05
31 …ne mmVCE_VCPU_CNTL_BASE_IDX 0
32 …VCE_VCPU_CACHE_OFFSET0 0x0a09
33 …ne mmVCE_VCPU_CACHE_OFFSET0_BASE_IDX 0
34 …VCE_VCPU_CACHE_SIZE0 0x0a0a
35 …ne mmVCE_VCPU_CACHE_SIZE0_BASE_IDX 0
36 …VCE_VCPU_CACHE_OFFSET1 0x0a0b
[all …]
/linux/drivers/media/platform/st/sti/bdisp/
H A Dbdisp-reg.h8 /* 0 - General */
87 #define BLT_CTL 0x0A00
88 #define BLT_ITS 0x0A04
89 #define BLT_STA1 0x0A08
90 #define BLT_AQ1_CTL 0x0A60
91 #define BLT_AQ1_IP 0x0A64
92 #define BLT_AQ1_LNA 0x0A68
93 #define BLT_AQ1_STA 0x0A6C
94 #define BLT_ITM0 0x0AD0
96 #define BLT_PLUGS1_OP2 0x0B04
[all …]
/linux/drivers/net/wireless/realtek/rtw88/
H A Drtw8723x.h28 IQK_ROUND_INVALID = 0xff,
45 u8 mac_addr[ETH_ALEN]; /* 0xd0 */
53 u8 res4[48]; /* 0xd0 */
54 u8 vendor_id[2]; /* 0x100 */
55 u8 product_id[2]; /* 0x102 */
56 u8 usb_option; /* 0x104 */
57 u8 res5[2]; /* 0x105 */
58 u8 mac_addr[ETH_ALEN]; /* 0x107 */
62 u8 res4[0x4a]; /* 0xd0 */
63 u8 mac_addr[ETH_ALEN]; /* 0x11a */
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_scl_filters.c31 // <sharpness> = 0
37 0x1000, 0x0000,
38 0x0FF0, 0x0010,
39 0x0FB0, 0x0050,
40 0x0F34, 0x00CC,
41 0x0E68, 0x0198,
42 0x0D44, 0x02BC,
43 0x0BC4, 0x043C,
44 0x09FC, 0x0604,
45 0x0800, 0x0800
[all …]
/linux/drivers/gpu/drm/amd/display/dc/spl/
H A Ddc_spl_scl_filters.c11 // <sharpness> = 0
17 0x1000, 0x0000,
18 0x0FF0, 0x0010,
19 0x0FB0, 0x0050,
20 0x0F34, 0x00CC,
21 0x0E68, 0x0198,
22 0x0D44, 0x02BC,
23 0x0BC4, 0x043C,
24 0x09FC, 0x0604,
25 0x0800, 0x0800
[all …]
/linux/drivers/media/i2c/ccs/
H A Dsmiapp-reg-defs.h19 #define SMIAPP_REG_U16_MODEL_ID CCI_REG16(0x0000)
20 #define SMIAPP_REG_U8_REVISION_NUMBER_MAJOR CCI_REG8(0x0002)
21 #define SMIAPP_REG_U8_MANUFACTURER_ID CCI_REG8(0x0003)
22 #define SMIAPP_REG_U8_SMIA_VERSION CCI_REG8(0x0004)
23 #define SMIAPP_REG_U8_FRAME_COUNT CCI_REG8(0x0005)
24 #define SMIAPP_REG_U8_PIXEL_ORDER CCI_REG8(0x0006)
25 #define SMIAPP_REG_U16_DATA_PEDESTAL CCI_REG16(0x0008)
26 #define SMIAPP_REG_U8_PIXEL_DEPTH CCI_REG8(0x000c)
27 #define SMIAPP_REG_U8_REVISION_NUMBER_MINOR CCI_REG8(0x0010)
28 #define SMIAPP_REG_U8_SMIAPP_VERSION CCI_REG8(0x0011)
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8ulp-pinfunc.h13 #define MX8ULP_PAD_PTD0__PTD0 0x0000 0x0000 0x1 0x0
14 #define MX8ULP_PAD_PTD0__I2S6_RX_BCLK 0x0000 0x0B44 0x7 0x1
15 #define MX8ULP_PAD_PTD0__SDHC0_RESET_B 0x0000 0x0000 0x8 0x0
16 #define MX8ULP_PAD_PTD0__FLEXSPI2_B_DQS 0x0000 0x0974 0x9 0x1
17 #define MX8ULP_PAD_PTD0__CLKOUT2 0x0000 0x0000 0xa 0x0
18 #define MX8ULP_PAD_PTD0__EPDC0_SDCLK_B 0x0000 0x0000 0xb 0x0
19 #define MX8ULP_PAD_PTD0__LP_APD_DBG_MUX_0 0x0000 0x0000 0xc 0x0
20 #define MX8ULP_PAD_PTD0__CLKOUT1 0x0000 0x0000 0xd 0x0
21 #define MX8ULP_PAD_PTD0__DEBUG_MUX0_0 0x0000 0x0000 0xe 0x0
22 #define MX8ULP_PAD_PTD0__DEBUG_MUX1_0 0x0000 0x0000 0xf 0x0
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/gmc/
H A Dgmc_6_0_d.h26 #define ixMC_IO_DEBUG_ACMD_CLKSEL_D0 0x00CE
27 #define ixMC_IO_DEBUG_ACMD_CLKSEL_D1 0x00DE
28 #define ixMC_IO_DEBUG_ACMD_MISC_D0 0x00AE
29 #define ixMC_IO_DEBUG_ACMD_MISC_D1 0x00BE
30 #define ixMC_IO_DEBUG_ACMD_OFSCAL_D0 0x00EE
31 #define ixMC_IO_DEBUG_ACMD_OFSCAL_D1 0x00FE
32 #define ixMC_IO_DEBUG_ACMD_RXPHASE_D0 0x010E
33 #define ixMC_IO_DEBUG_ACMD_RXPHASE_D1 0x011E
34 #define ixMC_IO_DEBUG_ACMD_TXBST_PD_D0 0x018E
35 #define ixMC_IO_DEBUG_ACMD_TXBST_PD_D1 0x019E
[all …]
/linux/sound/soc/mediatek/mt8365/
H A Dmt8365-reg.h15 #define AUDIO_TOP_CON0 (0x0000)
16 #define AUDIO_TOP_CON1 (0x0004)
17 #define AUDIO_TOP_CON2 (0x0008)
18 #define AUDIO_TOP_CON3 (0x000c)
20 #define AFE_DAC_CON0 (0x0010)
21 #define AFE_DAC_CON1 (0x0014)
22 #define AFE_I2S_CON (0x0018)
23 #define AFE_CONN0 (0x0020)
24 #define AFE_CONN1 (0x0024)
25 #define AFE_CONN2 (0x0028)
[all …]
/linux/arch/mips/include/asm/sibyte/
H A Dsb1250_regs.h46 * XXX: can't remove MC base 0 if 112x, since it's used by other macros,
51 #define A_MC_BASE_0 0x0010051000
52 #define A_MC_BASE_1 0x0010052000
53 #define MC_REGISTER_SPACING 0x1000
58 #define R_MC_CONFIG 0x0000000100
59 #define R_MC_DRAMCMD 0x0000000120
60 #define R_MC_DRAMMODE 0x0000000140
61 #define R_MC_TIMING1 0x0000000160
62 #define R_MC_TIMING2 0x0000000180
63 #define R_MC_CS_START 0x00000001A0
[all …]
/linux/drivers/net/ethernet/microchip/
H A Dlan743x_main.h16 #define ID_REV (0x00)
17 #define ID_REV_ID_MASK_ (0xFFFF0000)
18 #define ID_REV_ID_LAN7430_ (0x74300000)
19 #define ID_REV_ID_LAN7431_ (0x74310000)
20 #define ID_REV_ID_LAN743X_ (0x74300000)
21 #define ID_REV_ID_A011_ (0xA0110000) // PCI11010
22 #define ID_REV_ID_A041_ (0xA0410000) // PCI11414
23 #define ID_REV_ID_A0X1_ (0xA0010000)
25 ((((id_rev) & 0xFFF00000) == ID_REV_ID_LAN743X_) || \
26 (((id_rev) & 0xFF0F0000) == ID_REV_ID_A0X1_))
[all …]
/linux/drivers/usb/serial/
H A Dipaq.c37 { USB_DEVICE(0x0104, 0x00BE) }, /* Socket USB Sync */
38 { USB_DEVICE(0x03F0, 0x1016) }, /* HP USB Sync */
39 { USB_DEVICE(0x03F0, 0x1116) }, /* HP USB Sync 1611 */
40 { USB_DEVICE(0x03F0, 0x1216) }, /* HP USB Sync 1612 */
41 { USB_DEVICE(0x03F0, 0x2016) }, /* HP USB Sync 1620 */
42 { USB_DEVICE(0x03F0, 0x2116) }, /* HP USB Sync 1621 */
43 { USB_DEVICE(0x03F0, 0x2216) }, /* HP USB Sync 1622 */
44 { USB_DEVICE(0x03F0, 0x3016) }, /* HP USB Sync 1630 */
45 { USB_DEVICE(0x03F0, 0x3116) }, /* HP USB Sync 1631 */
46 { USB_DEVICE(0x03F0, 0x3216) }, /* HP USB Sync 1632 */
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/mmhub/
H A Dmmhub_2_3_0_offset.h27 // base address: 0x68000
28 …DAGB0_RDCLI0 0x0000
30 …DAGB0_RDCLI1 0x0001
32 …DAGB0_RDCLI2 0x0002
34 …DAGB0_RDCLI3 0x0003
36 …DAGB0_RDCLI4 0x0004
38 …DAGB0_RDCLI5 0x0005
40 …DAGB0_RDCLI6 0x0006
42 …DAGB0_RDCLI7 0x0007
44 …DAGB0_RDCLI8 0x0008
[all …]
H A Dmmhub_9_4_1_offset.h27 // base address: 0x68000
28 …DAGB0_RDCLI0 0x0000
30 …DAGB0_RDCLI1 0x0001
32 …DAGB0_RDCLI2 0x0002
34 …DAGB0_RDCLI3 0x0003
36 …DAGB0_RDCLI4 0x0004
38 …DAGB0_RDCLI5 0x0005
40 …DAGB0_RDCLI6 0x0006
42 …DAGB0_RDCLI7 0x0007
44 …DAGB0_RDCLI8 0x0008
[all …]
/linux/drivers/media/i2c/
H A Dvgxy61.c30 #define VGXY61_REG_MODEL_ID CCI_REG16_LE(0x0000)
31 #define VG5661_MODEL_ID 0x5661
32 #define VG5761_MODEL_ID 0x5761
33 #define VGXY61_REG_REVISION CCI_REG16_LE(0x0002)
34 #define VGXY61_REG_FWPATCH_REVISION CCI_REG16_LE(0x0014)
35 #define VGXY61_REG_FWPATCH_START_ADDR CCI_REG8(0x2000)
36 #define VGXY61_REG_SYSTEM_FSM CCI_REG8(0x0020)
37 #define VGXY61_SYSTEM_FSM_SW_STBY 0x03
38 #define VGXY61_SYSTEM_FSM_STREAMING 0x04
39 #define VGXY61_REG_NVM CCI_REG8(0x0023)
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/engine/device/
H A Dpci.c43 { 0x10de, 0x0010, NULL, { .tv_gpio = 4 } },
50 { 0x1462, 0x5710, NULL, { .tv_pin_mask = 0xc } },
57 { 0x19da, 0x1035, NULL, { .tv_pin_mask = 0xc } },
58 { 0x19da, 0x2035, NULL, { .tv_pin_mask = 0xc } },
64 { 0x10de, 0x0595, "Tesla T10 Processor" },
65 { 0x10de, 0x068f, "Tesla T10 Processor" },
66 { 0x10de, 0x0697, "Tesla M1060" },
67 { 0x10de, 0x0714, "Tesla M1060" },
68 { 0x10de, 0x0743, "Tesla M1060" },
74 { 0x106b, 0x00a7, "GeForce 8800 GS" },
[all …]
/linux/sound/soc/mediatek/mt8195/
H A Dmt8195-reg.h13 #define AFE_SRAM_BASE (0x10880000)
14 #define AFE_SRAM_SIZE (0x10000)
16 #define AUDIO_TOP_CON0 (0x0000)
17 #define AUDIO_TOP_CON1 (0x0004)
18 #define AUDIO_TOP_CON2 (0x0008)
19 #define AUDIO_TOP_CON3 (0x000c)
20 #define AUDIO_TOP_CON4 (0x0010)
21 #define AUDIO_TOP_CON5 (0x0014)
22 #define AUDIO_TOP_CON6 (0x0018)
23 #define AFE_MAS_HADDR_MSB (0x0020)
[all …]
/linux/sound/soc/mediatek/mt8188/
H A Dmt8188-reg.h14 #define AUDIO_TOP_CON0 (0x0000)
15 #define AUDIO_TOP_CON1 (0x0004)
16 #define AUDIO_TOP_CON2 (0x0008)
17 #define AUDIO_TOP_CON3 (0x000c)
18 #define AUDIO_TOP_CON4 (0x0010)
19 #define AUDIO_TOP_CON5 (0x0014)
20 #define AUDIO_TOP_CON6 (0x0018)
21 #define AFE_MAS_HADDR_MSB (0x0020)
22 #define AFE_MEMIF_ONE_HEART (0x0024)
23 #define AFE_MUX_SEL_CFG (0x0044)
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_2_offset.h29 // base address: 0x0
30 …DIDT_SQ_CTRL0 0x0000
31 …DIDT_SQ_CTRL2 0x0002
32 …DIDT_SQ_STALL_CTRL 0x0004
33 …DIDT_SQ_TUNING_CTRL 0x0005
34 …DIDT_SQ_STALL_AUTO_RELEASE_CTRL 0x0006
35 …DIDT_SQ_CTRL3 0x0007
36 …DIDT_SQ_STALL_PATTERN_1_2 0x0008
37 …DIDT_SQ_STALL_PATTERN_3_4 0x0009
38 …DIDT_SQ_STALL_PATTERN_5_6 0x000a
[all …]
H A Dgc_9_1_offset.h24 …SQ_DEBUG_STS_GLOBAL 0x0309
25 …ne mmSQ_DEBUG_STS_GLOBAL_BASE_IDX 0
26 …SQ_DEBUG_STS_GLOBAL2 0x0310
27 …ne mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX 0
28 …SQ_DEBUG_STS_GLOBAL3 0x0311
29 …ne mmSQ_DEBUG_STS_GLOBAL3_BASE_IDX 0
32 // base address: 0x8000
33 …GRBM_CNTL 0x0000
34 …ne mmGRBM_CNTL_BASE_IDX 0
35 …GRBM_SKEW_CNTL 0x0001
[all …]
H A Dgc_9_2_1_offset.h24 …SQ_DEBUG_STS_GLOBAL 0x0309
25 …ne mmSQ_DEBUG_STS_GLOBAL_BASE_IDX 0
26 …SQ_DEBUG_STS_GLOBAL2 0x0310
27 …ne mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX 0
28 …SQ_DEBUG_STS_GLOBAL3 0x0311
29 …ne mmSQ_DEBUG_STS_GLOBAL3_BASE_IDX 0
32 // base address: 0x8000
33 …GRBM_CNTL 0x0000
34 …ne mmGRBM_CNTL_BASE_IDX 0
35 …GRBM_SKEW_CNTL 0x0001
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/nbio/
H A Dnbio_7_9_0_offset.h29 // base address: 0x0
30 …BIF_BX0_PCIE_INDEX 0x000c
31 …e regBIF_BX0_PCIE_INDEX_BASE_IDX 0
32 …BIF_BX0_PCIE_DATA 0x000d
33 …e regBIF_BX0_PCIE_DATA_BASE_IDX 0
34 …BIF_BX0_PCIE_INDEX2 0x000e
35 …e regBIF_BX0_PCIE_INDEX2_BASE_IDX 0
36 …BIF_BX0_PCIE_DATA2 0x000f
37 …e regBIF_BX0_PCIE_DATA2_BASE_IDX 0
38 …BIF_BX0_PCIE_INDEX_HI 0x0010
[all …]

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