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/linux/sound/soc/codecs/
H A Drt712-sdca-sdw.h16 …{ SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT712_SDCA_ENT_CS01, RT712_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 0x0…
17 …{ SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT712_SDCA_ENT_CS11, RT712_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 0x0…
18 …{ SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT712_SDCA_ENT_USER_FU05, RT712_SDCA_CTL_FU_MUTE, CH_01), 0x01…
19 …{ SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT712_SDCA_ENT_USER_FU05, RT712_SDCA_CTL_FU_MUTE, CH_02), 0x01…
20 …{ SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT712_SDCA_ENT_USER_FU0F, RT712_SDCA_CTL_FU_MUTE, CH_01), 0x01…
21 …{ SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT712_SDCA_ENT_USER_FU0F, RT712_SDCA_CTL_FU_MUTE, CH_02), 0x01…
22 …{ SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT712_SDCA_ENT_PDE40, RT712_SDCA_CTL_REQ_POWER_STATE, 0), 0x03…
23 …{ SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT712_SDCA_ENT_PDE12, RT712_SDCA_CTL_REQ_POWER_STATE, 0), 0x03…
24 …{ SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT712_SDCA_ENT_CS1C, RT712_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 0x09…
25 …{ SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT712_SDCA_ENT_USER_FU1E, RT712_SDCA_CTL_FU_MUTE, CH_01), 0x01 …
[all …]
/linux/drivers/net/wwan/t7xx/
H A Dt7xx_cldma.h25 #define CLDMA_ALL_Q GENMASK(7, 0)
29 #define TXRX_STATUS_BITMASK GENMASK(7, 0)
40 #define CLDMA0_AO_BASE 0x10049000
41 #define CLDMA0_PD_BASE 0x1021d000
42 #define CLDMA1_AO_BASE 0x1004b000
43 #define CLDMA1_PD_BASE 0x1021f000
45 #define CLDMA_R_AO_BASE 0x10023000
46 #define CLDMA_R_PD_BASE 0x1023d000
49 #define REG_CLDMA_UL_START_ADDRL_0 0x0004
50 #define REG_CLDMA_UL_START_ADDRH_0 0x0008
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_1_offset.h25 // base address: 0x8000
26 …GRBM_CNTL 0x0000
27 …ne mmGRBM_CNTL_BASE_IDX 0
28 …GRBM_SKEW_CNTL 0x0001
29 …ne mmGRBM_SKEW_CNTL_BASE_IDX 0
30 …GRBM_STATUS2 0x0002
31 …ne mmGRBM_STATUS2_BASE_IDX 0
32 …GRBM_PWR_CNTL 0x0003
33 …ne mmGRBM_PWR_CNTL_BASE_IDX 0
34 …GRBM_STATUS 0x0004
[all …]
/linux/drivers/gpu/drm/nouveau/include/nvhw/class/
H A Dcl502d.h26 …_SET_OBJECT 0x0000
27 …_SET_OBJECT_POINTER 15:0
29 …_WAIT_FOR_IDLE 0x0110
30 …_WAIT_FOR_IDLE_V 31:0
32 …_SET_DST_CONTEXT_DMA 0x0184
33 …_SET_DST_CONTEXT_DMA_HANDLE 31:0
35 …_SET_SRC_CONTEXT_DMA 0x0188
36 …_SET_SRC_CONTEXT_DMA_HANDLE 31:0
38 …_SET_SEMAPHORE_CONTEXT_DMA 0x018c
39 …_SET_SEMAPHORE_CONTEXT_DMA_HANDLE 31:0
[all …]
H A Dcl902d.h26 …_SET_OBJECT 0x0000
27 …_SET_OBJECT_CLASS_ID 15:0
30 …_WAIT_FOR_IDLE 0x0110
31 …_WAIT_FOR_IDLE_V 31:0
33 …_SET_DST_FORMAT 0x0200
34 …_SET_DST_FORMAT_V 7:0
35 …_SET_DST_FORMAT_V_A8R8G8B8 0x000000CF
36 …_SET_DST_FORMAT_V_A8RL8GL8BL8 0x000000D0
37 …_SET_DST_FORMAT_V_A2R10G10B10 0x000000DF
38 …_SET_DST_FORMAT_V_A8B8G8R8 0x000000D5
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dnv35.c36 NVKM_MEM_TARGET_INST, 0x577c, 16, true, in nv35_gr_chan_new()
42 nvkm_wo32(chan->inst, 0x0028, 0x00000001 | (chan->chid << 24)); in nv35_gr_chan_new()
43 nvkm_wo32(chan->inst, 0x040c, 0x00000101); in nv35_gr_chan_new()
44 nvkm_wo32(chan->inst, 0x0420, 0x00000111); in nv35_gr_chan_new()
45 nvkm_wo32(chan->inst, 0x0424, 0x00000060); in nv35_gr_chan_new()
46 nvkm_wo32(chan->inst, 0x0440, 0x00000080); in nv35_gr_chan_new()
47 nvkm_wo32(chan->inst, 0x0444, 0xffff0000); in nv35_gr_chan_new()
48 nvkm_wo32(chan->inst, 0x0448, 0x00000001); in nv35_gr_chan_new()
49 nvkm_wo32(chan->inst, 0x045c, 0x44400000); in nv35_gr_chan_new()
50 nvkm_wo32(chan->inst, 0x0488, 0xffff0000); in nv35_gr_chan_new()
[all …]
H A Dnv30.c37 NVKM_MEM_TARGET_INST, 0x5f48, 16, true, in nv30_gr_chan_new()
43 nvkm_wo32(chan->inst, 0x0028, 0x00000001 | (chan->chid << 24)); in nv30_gr_chan_new()
44 nvkm_wo32(chan->inst, 0x0410, 0x00000101); in nv30_gr_chan_new()
45 nvkm_wo32(chan->inst, 0x0424, 0x00000111); in nv30_gr_chan_new()
46 nvkm_wo32(chan->inst, 0x0428, 0x00000060); in nv30_gr_chan_new()
47 nvkm_wo32(chan->inst, 0x0444, 0x00000080); in nv30_gr_chan_new()
48 nvkm_wo32(chan->inst, 0x0448, 0xffff0000); in nv30_gr_chan_new()
49 nvkm_wo32(chan->inst, 0x044c, 0x00000001); in nv30_gr_chan_new()
50 nvkm_wo32(chan->inst, 0x0460, 0x44400000); in nv30_gr_chan_new()
51 nvkm_wo32(chan->inst, 0x048c, 0xffff0000); in nv30_gr_chan_new()
[all …]
/linux/drivers/pci/controller/dwc/
H A Dpcie-visconti.c37 #define PCIE_UL_REG_S_PCIE_MODE 0x00F4
38 #define PCIE_UL_REG_S_PCIE_MODE_EP 0x00
39 #define PCIE_UL_REG_S_PCIE_MODE_RC 0x04
41 #define PCIE_UL_REG_S_PERSTN_CTRL 0x00F8
45 #define PCIE_UL_DIRECT_PERSTN BIT(0)
50 #define PCIE_UL_REG_S_PHY_INIT_02 0x0104
51 #define PCIE_UL_PHY0_SRAM_EXT_LD_DONE BIT(0)
53 #define PCIE_UL_REG_S_PHY_INIT_03 0x0108
54 #define PCIE_UL_PHY0_SRAM_INIT_DONE BIT(0)
56 #define PCIE_UL_REG_S_INT_EVENT_MASK1 0x0138
[all …]
/linux/drivers/gpu/drm/amd/display/dc/sspl/
H A Ddc_spl_isharp_filters.c21 0x03010000,
22 0x0F0B0805,
23 0x211E1813,
24 0x2B292624,
25 0x3533302E,
26 0x3E3C3A37,
27 0x46444240,
28 0x4D4B4A48,
29 0x5352504F,
30 0x59575655,
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/engine/disp/
H A Dg84.c37 const u32 hoff = head * 0x800; in g84_sor_hdmi_infoframe_vsi()
39 nvkm_mask(device, 0x61653c + hoff, 0x00010001, 0x00010000); in g84_sor_hdmi_infoframe_vsi()
45 nvkm_wr32(device, 0x616544 + hoff, vsi.header); in g84_sor_hdmi_infoframe_vsi()
46 nvkm_wr32(device, 0x616548 + hoff, vsi.subpack0_low); in g84_sor_hdmi_infoframe_vsi()
47 nvkm_wr32(device, 0x61654c + hoff, vsi.subpack0_high); in g84_sor_hdmi_infoframe_vsi()
49 /* nvkm_wr32(device, 0x616550 + hoff, vsi.subpack1_low); */ in g84_sor_hdmi_infoframe_vsi()
50 /* nvkm_wr32(device, 0x616554 + hoff, vsi.subpack1_high); */ in g84_sor_hdmi_infoframe_vsi()
52 nvkm_mask(device, 0x61653c + hoff, 0x00010001, 0x00010001); in g84_sor_hdmi_infoframe_vsi()
60 const u32 hoff = head * 0x800; in g84_sor_hdmi_infoframe_avi()
64 nvkm_mask(device, 0x616520 + hoff, 0x00000001, 0x00000000); in g84_sor_hdmi_infoframe_avi()
[all …]
/linux/drivers/net/ethernet/renesas/
H A Drtsn.h14 #define AXIBMI 0x0000
15 #define TSNMHD 0x1000
16 #define RMSO 0x2000
17 #define RMRO 0x3800
20 AXIWC = AXIBMI + 0x0000,
21 AXIRC = AXIBMI + 0x0004,
22 TDPC0 = AXIBMI + 0x0010,
23 TFT = AXIBMI + 0x0090,
24 TATLS0 = AXIBMI + 0x00a0,
25 TATLS1 = AXIBMI + 0x00a4,
[all …]
/linux/drivers/video/fbdev/nvidia/
H A Dnv_hw.c61 VGA_WR08(par->PCIO, 0x3D4, 0x1F); in NVLockUnlock()
62 VGA_WR08(par->PCIO, 0x3D5, Lock ? 0x99 : 0x57); in NVLockUnlock()
64 VGA_WR08(par->PCIO, 0x3D4, 0x11); in NVLockUnlock()
65 cr11 = VGA_RD08(par->PCIO, 0x3D5); in NVLockUnlock()
67 cr11 |= 0x80; in NVLockUnlock()
69 cr11 &= ~0x80; in NVLockUnlock()
70 VGA_WR08(par->PCIO, 0x3D5, cr11); in NVLockUnlock()
77 par->CurrentState->cursor1 = (par->CurrentState->cursor1 & 0xFE) | in NVShowHideCursor()
78 (ShowHide & 0x01); in NVShowHideCursor()
79 VGA_WR08(par->PCIO, 0x3D4, 0x31); in NVShowHideCursor()
[all …]
/linux/drivers/net/ethernet/samsung/sxgbe/
H A Dsxgbe_reg.h13 #define SXGBE_CORE_TX_CONFIG_REG 0x0000
14 #define SXGBE_CORE_RX_CONFIG_REG 0x0004
15 #define SXGBE_CORE_PKT_FILTER_REG 0x0008
16 #define SXGBE_CORE_WATCHDOG_TIMEOUT_REG 0x000C
17 #define SXGBE_CORE_HASH_TABLE_REG0 0x0010
18 #define SXGBE_CORE_HASH_TABLE_REG1 0x0014
19 #define SXGBE_CORE_HASH_TABLE_REG2 0x0018
20 #define SXGBE_CORE_HASH_TABLE_REG3 0x001C
21 #define SXGBE_CORE_HASH_TABLE_REG4 0x0020
22 #define SXGBE_CORE_HASH_TABLE_REG5 0x0024
[all …]
/linux/drivers/gpu/drm/omapdrm/dss/
H A Ddispc.h11 #define DISPC_REVISION 0x0000
12 #define DISPC_SYSCONFIG 0x0010
13 #define DISPC_SYSSTATUS 0x0014
14 #define DISPC_IRQSTATUS 0x0018
15 #define DISPC_IRQENABLE 0x001C
16 #define DISPC_CONTROL 0x0040
17 #define DISPC_CONFIG 0x0044
18 #define DISPC_CAPABLE 0x0048
19 #define DISPC_LINE_STATUS 0x005C
20 #define DISPC_LINE_NUMBER 0x0060
[all …]
/linux/drivers/video/fbdev/omap2/omapfb/dss/
H A Ddispc.h13 #define DISPC_REVISION 0x0000
14 #define DISPC_SYSCONFIG 0x0010
15 #define DISPC_SYSSTATUS 0x0014
16 #define DISPC_IRQSTATUS 0x0018
17 #define DISPC_IRQENABLE 0x001C
18 #define DISPC_CONTROL 0x0040
19 #define DISPC_CONFIG 0x0044
20 #define DISPC_CAPABLE 0x0048
21 #define DISPC_LINE_STATUS 0x005C
22 #define DISPC_LINE_NUMBER 0x0060
[all …]
/linux/drivers/resctrl/
H A Dmpam_internal.h212 COUNT_BOTH = 0,
400 #define MPAM_ARCHITECTURE_V1 0x10
404 #define MPAMF_IDR 0x0000 /* features id register */
405 #define MPAMF_IIDR 0x0018 /* implementer id register */
406 #define MPAMF_AIDR 0x0020 /* architectural id register */
407 #define MPAMF_IMPL_IDR 0x0028 /* imp-def partitioning */
408 #define MPAMF_CPOR_IDR 0x0030 /* cache-portion partitioning */
409 #define MPAMF_CCAP_IDR 0x0038 /* cache-capacity partitioning */
410 #define MPAMF_MBW_IDR 0x0040 /* mem-bw partitioning */
411 #define MPAMF_PRI_IDR 0x0048 /* priority partitioning */
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_scl_filters.c31 // <sharpness> = 0
37 0x1000, 0x0000,
38 0x0FF0, 0x0010,
39 0x0FB0, 0x0050,
40 0x0F34, 0x00CC,
41 0x0E68, 0x0198,
42 0x0D44, 0x02BC,
43 0x0BC4, 0x043C,
44 0x09FC, 0x0604,
45 0x0800, 0x0800
[all …]
/linux/include/uapi/linux/
H A Dzorro_ids.h9 #define ZORRO_MANUF_PACIFIC_PERIPHERALS 0x00D3
10 #define ZORRO_PROD_PACIFIC_PERIPHERALS_SE_2000_A500 ZORRO_ID(PACIFIC_PERIPHERALS, 0x00, 0)
11 #define ZORRO_PROD_PACIFIC_PERIPHERALS_SCSI ZORRO_ID(PACIFIC_PERIPHERALS, 0x0A, 0)
13 #define ZORRO_MANUF_MACROSYSTEMS_USA_2 0x0100
14 #define ZORRO_PROD_MACROSYSTEMS_WARP_ENGINE ZORRO_ID(MACROSYSTEMS_USA_2, 0x13, 0)
16 #define ZORRO_MANUF_KUPKE_1 0x00DD
17 #define ZORRO_PROD_KUPKE_GOLEM_RAM_BOX_2MB ZORRO_ID(KUPKE_1, 0x00, 0)
19 #define ZORRO_MANUF_MEMPHIS 0x0100
20 #define ZORRO_PROD_MEMPHIS_STORMBRINGER ZORRO_ID(MEMPHIS, 0x00, 0)
22 #define ZORRO_MANUF_3_STATE 0x0200
[all …]
/linux/Documentation/driver-api/media/drivers/ccs/
H A Dccs-regs.asc19 module_model_id 0x0000 16
20 module_revision_number_major 0x0002 8
21 frame_count 0x0005 8
22 pixel_order 0x0006 8
23 - e GRBG 0
27 MIPI_CCS_version 0x0007 8
28 - e v1_0 0x10
29 - e v1_1 0x11
31 - f minor 0 3
32 data_pedestal 0x0008 16
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8ulp-pinfunc.h13 #define MX8ULP_PAD_PTD0__PTD0 0x0000 0x0000 0x1 0x0
14 #define MX8ULP_PAD_PTD0__I2S6_RX_BCLK 0x0000 0x0B44 0x7 0x1
15 #define MX8ULP_PAD_PTD0__SDHC0_RESET_B 0x0000 0x0000 0x8 0x0
16 #define MX8ULP_PAD_PTD0__FLEXSPI2_B_DQS 0x0000 0x0974 0x9 0x1
17 #define MX8ULP_PAD_PTD0__CLKOUT2 0x0000 0x0000 0xa 0x0
18 #define MX8ULP_PAD_PTD0__EPDC0_SDCLK_B 0x0000 0x0000 0xb 0x0
19 #define MX8ULP_PAD_PTD0__LP_APD_DBG_MUX_0 0x0000 0x0000 0xc 0x0
20 #define MX8ULP_PAD_PTD0__CLKOUT1 0x0000 0x0000 0xd 0x0
21 #define MX8ULP_PAD_PTD0__DEBUG_MUX0_0 0x0000 0x0000 0xe 0x0
22 #define MX8ULP_PAD_PTD0__DEBUG_MUX1_0 0x0000 0x0000 0xf 0x0
[all …]
/linux/drivers/net/wireless/broadcom/b43/
H A Dradio_2055.c24 #define B2055_INITTAB_ENTRY_OK 0x01
25 #define B2055_INITTAB_UPLOAD 0x02
31 [B2055_SP_PINPD] = { .ghz5 = 0x0080, .ghz2 = 0x0080, NOUPLOAD, },
32 [B2055_C1_SP_RSSI] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
33 [B2055_C1_SP_PDMISC] = { .ghz5 = 0x0027, .ghz2 = 0x0027, NOUPLOAD, },
34 [B2055_C2_SP_RSSI] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
35 [B2055_C2_SP_PDMISC] = { .ghz5 = 0x0027, .ghz2 = 0x0027, NOUPLOAD, },
36 [B2055_C1_SP_RXGC1] = { .ghz5 = 0x007F, .ghz2 = 0x007F, UPLOAD, },
37 [B2055_C1_SP_RXGC2] = { .ghz5 = 0x0007, .ghz2 = 0x0007, UPLOAD, },
38 [B2055_C2_SP_RXGC1] = { .ghz5 = 0x007F, .ghz2 = 0x007F, UPLOAD, },
[all …]
/linux/drivers/gpu/drm/msm/adreno/
H A Da5xx_gpu.c75 for (i = 0; i < submit->nr_cmds; i++) { in a5xx_submit_in_rb()
97 for (i = 0; i < dwords; i++) { in a5xx_submit_in_rb()
132 unsigned int i, ibs = 0; in a5xx_submit()
137 ring->cur_ctx_seqno = 0; in a5xx_submit()
143 OUT_RING(ring, 0x02); in a5xx_submit()
147 OUT_RING(ring, 0); in a5xx_submit()
164 OUT_RING(ring, 0x0); in a5xx_submit()
168 OUT_RING(ring, 0x02); in a5xx_submit()
171 for (i = 0; i < submit->nr_cmds; i++) { in a5xx_submit()
195 if ((ibs % 32) == 0) in a5xx_submit()
[all …]
/linux/include/linux/soc/samsung/
H A Dexynos-regs-pmu.h17 #define S5P_CENTRAL_SEQ_CONFIGURATION 0x0200
21 #define S5P_CENTRAL_SEQ_OPTION 0x0208
42 #define EXYNOS_SWRESET 0x0400
44 #define S5P_WAKEUP_STAT 0x0600
46 #define EXYNOS_EINT_WAKEUP_MASK_DISABLED 0xffffffff
47 #define EXYNOS_EINT_WAKEUP_MASK 0x0604
48 #define S5P_WAKEUP_MASK 0x0608
49 #define S5P_WAKEUP_MASK2 0x0614
52 #define EXYNOS4_MIPI_PHY_CONTROL(n) (0x0710 + (n) * 4)
54 #define EXYNOS4_PHY_ENABLE (1 << 0)
[all...]
/linux/drivers/net/wireless/realtek/rtw88/
H A Dreg.h8 #define REG_SYS_FUNC_EN 0x0002
15 #define BIT_FEN_BB_RSTB BIT(0)
18 #define REG_SYS_PW_CTRL 0x0004
21 #define REG_APS_FSMCO 0x0004
25 #define REG_SYS_CLK_CTRL 0x0008
28 #define REG_SYS_CLKR 0x0008
33 #define REG_RSV_CTRL 0x001C
34 #define DISABLE_PI 0x3
35 #define ENABLE_PI 0x2
37 #define BIT_WLMCU_IOIF BIT(0)
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6sx-pinfunc.h13 #define MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x0014 0x035C 0x07A8 0x0 0x1
14 #define MX6SX_PAD_GPIO1_IO00__USDHC1_VSELECT 0x0014 0x035C 0x0000 0x1 0x0
15 #define MX6SX_PAD_GPIO1_IO00__SPDIF_LOCK 0x0014 0x035C 0x0000 0x2 0x0
16 #define MX6SX_PAD_GPIO1_IO00__CCM_WAIT 0x0014 0x035C 0x0000 0x3 0x0
17 #define MX6SX_PAD_GPIO1_IO00__WDOG1_WDOG_ANY 0x0014 0x035C 0x0000 0x4 0x0
18 #define MX6SX_PAD_GPIO1_IO00__GPIO1_IO_0 0x0014 0x035C 0x0000 0x5 0x0
19 #define MX6SX_PAD_GPIO1_IO00__SNVS_HP_WRAPPER_VIO_5 0x0014 0x035C 0x0000 0x6 0x0
20 #define MX6SX_PAD_GPIO1_IO00__PHY_DTB_1 0x0014 0x035C 0x0000 0x7 0x0
21 #define MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x0018 0x0360 0x07AC 0x0 0x1
22 #define MX6SX_PAD_GPIO1_IO01__USDHC1_RESET_B 0x0018 0x0360 0x0000 0x1 0x0
[all …]

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