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/linux/drivers/net/wireless/broadcom/b43/
H A Dtables.c21 0xFEB93FFD, 0xFEC63FFD, /* 0 */
22 0xFED23FFD, 0xFEDF3FFD,
23 0xFEEC3FFE, 0xFEF83FFE,
24 0xFF053FFE, 0xFF113FFE,
25 0xFF1E3FFE, 0xFF2A3FFF, /* 8 */
26 0xFF373FFF, 0xFF443FFF,
27 0xFF503FFF, 0xFF5D3FFF,
28 0xFF693FFF, 0xFF763FFF,
29 0xFF824000, 0xFF8F4000, /* 16 */
30 0xFF9B4000, 0xFFA84000,
[all …]
H A Dwa.c24 b43_phy_write(dev, B43_PHY_LNAHPFCTL, 0x1FF9); in b43_wa_initgains()
25 b43_phy_mask(dev, B43_PHY_LPFGAINCTL, 0xFF0F); in b43_wa_initgains()
27 b43_ofdmtab_write16(dev, B43_OFDMTAB_LPFGAIN, 0, 0x1FBF); in b43_wa_initgains()
28 b43_radio_write16(dev, 0x0002, 0x1FBF); in b43_wa_initgains()
30 b43_phy_write(dev, 0x0024, 0x4680); in b43_wa_initgains()
31 b43_phy_write(dev, 0x0020, 0x0003); in b43_wa_initgains()
32 b43_phy_write(dev, 0x001D, 0x0F40); in b43_wa_initgains()
33 b43_phy_write(dev, 0x001F, 0x1C00); in b43_wa_initgains()
35 b43_phy_maskset(dev, 0x002A, 0x00FF, 0x0400); in b43_wa_initgains()
37 b43_phy_maskset(dev, 0x002A, 0x00FF, 0x1A00); in b43_wa_initgains()
[all …]
H A Dradio_2059.c17 { 0x051, 0x70 }, { 0x05a, 0x03 }, { 0x079, 0x01 }, { 0x082, 0x70 },
18 { 0x083, 0x00 }, { 0x084, 0x70 }, { 0x09a, 0x7f }, { 0x0b6, 0x10 },
19 { 0x188, 0x05 },
61 RADIOREGS(0x48, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x6c,
62 0x09, 0x0f, 0x0a, 0x00, 0x0a, 0x00, 0x61, 0x73,
63 0x00, 0x00, 0x00, 0xd0, 0x00),
64 PHYREGS(0x03c9, 0x03c5, 0x03c1, 0x043a, 0x043f, 0x0443),
68 RADIOREGS(0x4b, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x71,
69 0x09, 0x0f, 0x0a, 0x00, 0x0a, 0x00, 0x61, 0x73,
70 0x00, 0x00, 0x00, 0xd0, 0x00),
[all …]
/linux/drivers/net/can/m_can/
H A Dtcan4x5x-regmap.c12 #define TCAN4X5X_SPI_INSTRUCTION_WRITE (0x61 << 24)
13 #define TCAN4X5X_SPI_INSTRUCTION_READ (0x41 << 24)
15 #define TCAN4X5X_MAX_REGISTER 0x87fc
63 spi_message_add_tail(&xfer[0], &msg); in tcan4x5x_regmap_read()
70 xfer[0].len = sizeof(buf_tx->cmd); in tcan4x5x_regmap_read()
76 xfer[0].rx_buf = buf_rx; in tcan4x5x_regmap_read()
77 xfer[0].len = sizeof(buf_tx->cmd) + val_len; in tcan4x5x_regmap_read()
80 memset(buf_tx->data, 0x0, val_len); in tcan4x5x_regmap_read()
90 return 0; in tcan4x5x_regmap_read()
95 regmap_reg_range(0x000c, 0x0010),
[all …]
/linux/arch/arm/mach-imx/
H A Diim.h11 #define MXC_IIMSTAT 0x0000
12 #define MXC_IIMSTATM 0x0004
13 #define MXC_IIMERR 0x0008
14 #define MXC_IIMEMASK 0x000C
15 #define MXC_IIMFCTL 0x0010
16 #define MXC_IIMUA 0x0014
17 #define MXC_IIMLA 0x0018
18 #define MXC_IIMSDAT 0x001C
19 #define MXC_IIMPREV 0x0020
20 #define MXC_IIMSREV 0x0024
[all …]
/linux/drivers/media/rc/keymaps/
H A Drc-anysee.c12 { 0x0800, KEY_NUMERIC_0 },
13 { 0x0801, KEY_NUMERIC_1 },
14 { 0x0802, KEY_NUMERIC_2 },
15 { 0x0803, KEY_NUMERIC_3 },
16 { 0x0804, KEY_NUMERIC_4 },
17 { 0x0805, KEY_NUMERIC_5 },
18 { 0x0806, KEY_NUMERIC_6 },
19 { 0x0807, KEY_NUMERIC_7 },
20 { 0x0808, KEY_NUMERIC_8 },
21 { 0x0809, KEY_NUMERIC_9 },
[all …]
H A Drc-asus-ps3-100.c12 { 0x081c, KEY_HOME }, /* home */
13 { 0x081e, KEY_TV }, /* tv */
14 { 0x0803, KEY_TEXT }, /* teletext */
15 { 0x0829, KEY_POWER }, /* close */
17 { 0x080b, KEY_RED }, /* red */
18 { 0x080d, KEY_YELLOW }, /* yellow */
19 { 0x0806, KEY_BLUE }, /* blue */
20 { 0x0807, KEY_GREEN }, /* green */
22 /* Keys 0 to 9 */
23 { 0x082a, KEY_NUMERIC_0 },
[all …]
/linux/drivers/net/wwan/t7xx/
H A Dt7xx_cldma.h25 #define CLDMA_ALL_Q GENMASK(7, 0)
29 #define TXRX_STATUS_BITMASK GENMASK(7, 0)
40 #define CLDMA0_AO_BASE 0x10049000
41 #define CLDMA0_PD_BASE 0x1021d000
42 #define CLDMA1_AO_BASE 0x1004b000
43 #define CLDMA1_PD_BASE 0x1021f000
45 #define CLDMA_R_AO_BASE 0x10023000
46 #define CLDMA_R_PD_BASE 0x1023d000
49 #define REG_CLDMA_UL_START_ADDRL_0 0x0004
50 #define REG_CLDMA_UL_START_ADDRH_0 0x0008
[all …]
/linux/arch/arm/mach-s3c/
H A Dregs-gpio-s3c64xx.h19 #define S3C64XX_GPA_BASE S3C64XX_GPIOREG(0x0000)
20 #define S3C64XX_GPB_BASE S3C64XX_GPIOREG(0x0020)
21 #define S3C64XX_GPC_BASE S3C64XX_GPIOREG(0x0040)
22 #define S3C64XX_GPD_BASE S3C64XX_GPIOREG(0x0060)
23 #define S3C64XX_GPE_BASE S3C64XX_GPIOREG(0x0080)
24 #define S3C64XX_GPF_BASE S3C64XX_GPIOREG(0x00A0)
25 #define S3C64XX_GPG_BASE S3C64XX_GPIOREG(0x00C0)
26 #define S3C64XX_GPH_BASE S3C64XX_GPIOREG(0x00E0)
27 #define S3C64XX_GPI_BASE S3C64XX_GPIOREG(0x0100)
28 #define S3C64XX_GPJ_BASE S3C64XX_GPIOREG(0x0120)
[all …]
/linux/include/video/
H A Datmel_lcdc.h18 #define ATMEL_LCDC_WIRING_BGR 0
37 #define ATMEL_LCDC_DMABADDR1 0x00
38 #define ATMEL_LCDC_DMABADDR2 0x04
39 #define ATMEL_LCDC_DMAFRMPT1 0x08
40 #define ATMEL_LCDC_DMAFRMPT2 0x0c
41 #define ATMEL_LCDC_DMAFRMADD1 0x10
42 #define ATMEL_LCDC_DMAFRMADD2 0x14
44 #define ATMEL_LCDC_DMAFRMCFG 0x18
45 #define ATMEL_LCDC_FRSIZE (0x7fffff << 0)
47 #define ATMEL_LCDC_BLENGTH (0x7f << ATMEL_LCDC_BLENGTH_OFFSET)
[all …]
/linux/drivers/video/fbdev/nvidia/
H A Dnv_hw.c61 VGA_WR08(par->PCIO, 0x3D4, 0x1F); in NVLockUnlock()
62 VGA_WR08(par->PCIO, 0x3D5, Lock ? 0x99 : 0x57); in NVLockUnlock()
64 VGA_WR08(par->PCIO, 0x3D4, 0x11); in NVLockUnlock()
65 cr11 = VGA_RD08(par->PCIO, 0x3D5); in NVLockUnlock()
67 cr11 |= 0x80; in NVLockUnlock()
69 cr11 &= ~0x80; in NVLockUnlock()
70 VGA_WR08(par->PCIO, 0x3D5, cr11); in NVLockUnlock()
77 par->CurrentState->cursor1 = (par->CurrentState->cursor1 & 0xFE) | in NVShowHideCursor()
78 (ShowHide & 0x01); in NVShowHideCursor()
79 VGA_WR08(par->PCIO, 0x3D4, 0x31); in NVShowHideCursor()
[all …]
/linux/drivers/clk/samsung/
H A Dclk-exynos5260.h15 #define MUX_SEL_AUD 0x0200
16 #define MUX_ENABLE_AUD 0x0300
17 #define MUX_STAT_AUD 0x0400
18 #define MUX_IGNORE_AUD 0x0500
19 #define DIV_AUD0 0x0600
20 #define DIV_AUD1 0x0604
21 #define DIV_STAT_AUD0 0x0700
22 #define DIV_STAT_AUD1 0x0704
23 #define EN_ACLK_AUD 0x0800
24 #define EN_PCLK_AUD 0x0900
[all …]
/linux/sound/hda/codecs/cirrus/
H A Dcs8409-tables.c24 .index = 0,
37 .index = 0,
62 { CS8409_PIN_AFG, AC_VERB_SET_GPIO_WAKE_MASK, 0x0018 }, /* WAKE from GPIO 3,4 */
63 { CS8409_PIN_VENDOR_WIDGET, AC_VERB_SET_PROC_STATE, 0x0001 }, /* Enable VPW processing */
64 { CS8409_PIN_VENDOR_WIDGET, AC_VERB_SET_COEF_INDEX, 0x0002 }, /* Configure GPIO 6,7 */
65 { CS8409_PIN_VENDOR_WIDGET, AC_VERB_SET_PROC_COEF, 0x0080 }, /* I2C mode */
66 { CS8409_PIN_VENDOR_WIDGET, AC_VERB_SET_COEF_INDEX, 0x005b }, /* Set I2C bus speed */
67 { CS8409_PIN_VENDOR_WIDGET, AC_VERB_SET_PROC_COEF, 0x0200 }, /* 100kHz I2C_STO = 2 */
72 { CS8409_PIN_ASP1_TRANSMITTER_A, 0x042120f0 }, /* ASP-1-TX */
73 { CS8409_PIN_ASP1_RECEIVER_A, 0x04a1205
[all...]
/linux/drivers/media/usb/gspca/
H A Dw996Xcf.c53 Return 0 on success, -1 otherwise.
61 if (sd->gspca_dev.usb_err < 0) in w9968cf_write_fsb()
69 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), 0, in w9968cf_write_fsb()
71 value, 0x06, sd->gspca_dev.usb_buf, 6, 500); in w9968cf_write_fsb()
72 if (ret < 0) { in w9968cf_write_fsb()
80 Return 0 on success, a negative number otherwise.
86 if (sd->gspca_dev.usb_err < 0) in w9968cf_write_sb()
95 usb_sndctrlpipe(sd->gspca_dev.dev, 0), in w9968cf_write_sb()
96 0, in w9968cf_write_sb()
98 value, 0x01, NULL, 0, 500); in w9968cf_write_sb()
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/engine/disp/
H A Dg84.c37 const u32 hoff = head * 0x800; in g84_sor_hdmi_infoframe_vsi()
39 nvkm_mask(device, 0x61653c + hoff, 0x00010001, 0x00010000); in g84_sor_hdmi_infoframe_vsi()
45 nvkm_wr32(device, 0x616544 + hoff, vsi.header); in g84_sor_hdmi_infoframe_vsi()
46 nvkm_wr32(device, 0x616548 + hoff, vsi.subpack0_low); in g84_sor_hdmi_infoframe_vsi()
47 nvkm_wr32(device, 0x61654c + hoff, vsi.subpack0_high); in g84_sor_hdmi_infoframe_vsi()
49 /* nvkm_wr32(device, 0x616550 + hoff, vsi.subpack1_low); */ in g84_sor_hdmi_infoframe_vsi()
50 /* nvkm_wr32(device, 0x616554 + hoff, vsi.subpack1_high); */ in g84_sor_hdmi_infoframe_vsi()
52 nvkm_mask(device, 0x61653c + hoff, 0x00010001, 0x00010001); in g84_sor_hdmi_infoframe_vsi()
60 const u32 hoff = head * 0x800; in g84_sor_hdmi_infoframe_avi()
64 nvkm_mask(device, 0x616520 + hoff, 0x00000001, 0x00000000); in g84_sor_hdmi_infoframe_avi()
[all …]
/linux/drivers/video/fbdev/kyro/
H A DSTG4000Reg.h54 NO_LUT = 0, RESERVED, GRAPHICS, OVERLAY
59 _8BPP = 0, _15BPP, _16BPP, _24BPP, _32BPP
64 GRAPHICS_MODE = 0, COLOR_KEY, PER_PIXEL_ALPHA, GLOBAL_ALPHA,
75 /* 0h */
76 volatile u32 Thread0Enable; /* 0x0000 */
77 volatile u32 Thread1Enable; /* 0x0004 */
78 volatile u32 Thread0Recover; /* 0x0008 */
79 volatile u32 Thread1Recover; /* 0x000C */
80 volatile u32 Thread0Step; /* 0x0010 */
81 volatile u32 Thread1Step; /* 0x0014 */
[all …]
/linux/sound/soc/codecs/
H A Drt700-sdw.h12 { 0x0000, 0x0000 },
13 { 0x0001, 0x0000 },
14 { 0x0002, 0x0000 },
15 { 0x0003, 0x0000 },
16 { 0x0004, 0x0000 },
17 { 0x0005, 0x0001 },
18 { 0x0020, 0x0000 },
19 { 0x0022, 0x0000 },
20 { 0x0023, 0x0000 },
21 { 0x0024, 0x0000 },
[all …]
/linux/include/linux/mfd/
H A Dmotorola-cpcap.h17 #define CPCAP_VENDOR_ST 0
21 #define CPCAP_REVISION_MINOR(r) ((r) & 0xf)
23 #define CPCAP_REVISION_1_0 0x08
24 #define CPCAP_REVISION_1_1 0x09
25 #define CPCAP_REVISION_2_0 0x10
26 #define CPCAP_REVISION_2_1 0x11
29 #define CPCAP_REG_INT1 0x0000 /* Interrupt 1 */
30 #define CPCAP_REG_INT2 0x0004 /* Interrupt 2 */
31 #define CPCAP_REG_INT3 0x0008 /* Interrupt 3 */
32 #define CPCAP_REG_INT4 0x000c /* Interrupt 4 */
[all …]
/linux/drivers/infiniband/hw/vmw_pvrdma/
H A Dpvrdma.h70 #define PCI_DEVICE_ID_VMWARE_PVRDMA 0x0820
/linux/drivers/net/ethernet/samsung/sxgbe/
H A Dsxgbe_reg.h13 #define SXGBE_CORE_TX_CONFIG_REG 0x0000
14 #define SXGBE_CORE_RX_CONFIG_REG 0x0004
15 #define SXGBE_CORE_PKT_FILTER_REG 0x0008
16 #define SXGBE_CORE_WATCHDOG_TIMEOUT_REG 0x000C
17 #define SXGBE_CORE_HASH_TABLE_REG0 0x0010
18 #define SXGBE_CORE_HASH_TABLE_REG1 0x0014
19 #define SXGBE_CORE_HASH_TABLE_REG2 0x0018
20 #define SXGBE_CORE_HASH_TABLE_REG3 0x001C
21 #define SXGBE_CORE_HASH_TABLE_REG4 0x0020
22 #define SXGBE_CORE_HASH_TABLE_REG5 0x0024
[all …]
/linux/drivers/gpu/drm/omapdrm/dss/
H A Ddispc.h11 #define DISPC_REVISION 0x0000
12 #define DISPC_SYSCONFIG 0x0010
13 #define DISPC_SYSSTATUS 0x0014
14 #define DISPC_IRQSTATUS 0x0018
15 #define DISPC_IRQENABLE 0x001C
16 #define DISPC_CONTROL 0x0040
17 #define DISPC_CONFIG 0x0044
18 #define DISPC_CAPABLE 0x0048
19 #define DISPC_LINE_STATUS 0x005C
20 #define DISPC_LINE_NUMBER 0x0060
[all …]
/linux/drivers/video/fbdev/omap2/omapfb/dss/
H A Ddispc.h13 #define DISPC_REVISION 0x0000
14 #define DISPC_SYSCONFIG 0x0010
15 #define DISPC_SYSSTATUS 0x0014
16 #define DISPC_IRQSTATUS 0x0018
17 #define DISPC_IRQENABLE 0x001C
18 #define DISPC_CONTROL 0x0040
19 #define DISPC_CONFIG 0x0044
20 #define DISPC_CAPABLE 0x0048
21 #define DISPC_LINE_STATUS 0x005C
22 #define DISPC_LINE_NUMBER 0x0060
[all …]
/linux/drivers/clk/renesas/
H A Drcar-gen4-cpg.c31 #define CPG_PLLECR 0x0820 /* PLL Enable Control Register */
36 #define CPG_PLL1CR0 0x830 /* PLLn Control Registers */
37 #define CPG_PLL1CR1 0x8b0
38 #define CPG_PLL2CR0 0x834
39 #define CPG_PLL2CR1 0x8b8
40 #define CPG_PLL3CR0 0x83c
41 #define CPG_PLL3CR1 0x8c0
42 #define CPG_PLL4CR0 0x844
43 #define CPG_PLL4CR1 0x8c8
44 #define CPG_PLL6CR0 0x84c
[all …]
/linux/drivers/resctrl/
H A Dmpam_internal.h212 COUNT_BOTH = 0,
400 #define MPAM_ARCHITECTURE_V1 0x10
404 #define MPAMF_IDR 0x0000 /* features id register */
405 #define MPAMF_IIDR 0x0018 /* implementer id register */
406 #define MPAMF_AIDR 0x0020 /* architectural id register */
407 #define MPAMF_IMPL_IDR 0x0028 /* imp-def partitioning */
408 #define MPAMF_CPOR_IDR 0x0030 /* cache-portion partitioning */
409 #define MPAMF_CCAP_IDR 0x0038 /* cache-capacity partitioning */
410 #define MPAMF_MBW_IDR 0x0040 /* mem-bw partitioning */
411 #define MPAMF_PRI_IDR 0x0048 /* priority partitioning */
[all …]
/linux/drivers/pinctrl/renesas/
H A Dpinctrl-rza2.c33 * Use 16 lower bits [15:0] for pin identifier
36 #define MUX_PIN_ID_MASK GENMASK(15, 0)
55 #define RZA2_PDR(port) (0x0000 + (port) * 2) /* Direction 16-bit */
56 #define RZA2_PODR(port) (0x0040 + (port)) /* Output Data 8-bit */
57 #define RZA2_PIDR(port) (0x0060 + (port)) /* Input Data 8-bit */
58 #define RZA2_PMR(port) (0x0080 + (port)) /* Mode 8-bit */
59 #define RZA2_DSCR(port) (0x0140 + (port) * 2) /* Drive 16-bit */
60 #define RZA2_PFS(port, pin) (0x0200 + ((port) * 8) + (pin)) /* Fnct 8-bit */
62 #define RZA2_PWPR 0x02ff /* Write Protect 8-bit */
63 #define RZA2_PFENET 0x0820 /* Ethernet Pins 8-bit */
[all …]

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