| /linux/drivers/clk/samsung/ |
| H A D | clk-exynos5260.h | 15 #define MUX_SEL_AUD 0x0200
16 #define MUX_ENABLE_AUD 0x0300
17 #define MUX_STAT_AUD 0x0400
18 #define MUX_IGNORE_AUD 0x0500
19 #define DIV_AUD0 0x0600
20 #define DIV_AUD1 0x0604
21 #define DIV_STAT_AUD0 0x0700
22 #define DIV_STAT_AUD1 0x0704
23 #define EN_ACLK_AUD 0x0800
24 #define EN_PCLK_AUD 0x0900
[all …]
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| /linux/drivers/net/wireless/mediatek/mt76/mt76x2/ |
| H A D | mcu.h | 12 #define MT_MCU_CPU_CTL 0x0704
13 #define MT_MCU_CLOCK_CTL 0x0708
14 #define MT_MCU_PCIE_REMAP_BASE1 0x0740
15 #define MT_MCU_PCIE_REMAP_BASE2 0x0744
16 #define MT_MCU_PCIE_REMAP_BASE3 0x0748
18 #define MT_MCU_ROM_PATCH_OFFSET 0x80000
19 #define MT_MCU_ROM_PATCH_ADDR 0x90000
21 #define MT_MCU_ILM_OFFSET 0x80000
23 #define MT_MCU_DLM_OFFSET 0x100000
24 #define MT_MCU_DLM_ADDR 0x90000
[all …]
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| /linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/ |
| H A D | nv35.c | 36 NVKM_MEM_TARGET_INST, 0x577c, 16, true, in nv35_gr_chan_new()
42 nvkm_wo32(chan->inst, 0x0028, 0x00000001 | (chan->chid << 24)); in nv35_gr_chan_new()
43 nvkm_wo32(chan->inst, 0x040c, 0x00000101); in nv35_gr_chan_new()
44 nvkm_wo32(chan->inst, 0x0420, 0x00000111); in nv35_gr_chan_new()
45 nvkm_wo32(chan->inst, 0x0424, 0x00000060); in nv35_gr_chan_new()
46 nvkm_wo32(chan->inst, 0x0440, 0x00000080); in nv35_gr_chan_new()
47 nvkm_wo32(chan->inst, 0x0444, 0xffff0000); in nv35_gr_chan_new()
48 nvkm_wo32(chan->inst, 0x0448, 0x00000001); in nv35_gr_chan_new()
49 nvkm_wo32(chan->inst, 0x045c, 0x44400000); in nv35_gr_chan_new()
50 nvkm_wo32(chan->inst, 0x0488, 0xffff0000); in nv35_gr_chan_new()
[all …]
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| /linux/include/uapi/linux/ |
| H A D | i2c-dev.h | 21 #define I2C_RETRIES 0x0701 /* number of times a device address should
23 #define I2C_TIMEOUT 0x0702 /* set timeout in units of 10 ms */
28 #define I2C_SLAVE 0x0703 /* Use this slave address */
29 #define I2C_SLAVE_FORCE 0x0706 /* Use this slave address, even if it
31 #define I2C_TENBIT 0x0704 /* 0 for 7 bit addrs, != 0 for 10 bit */
33 #define I2C_FUNCS 0x0705 /* Get the adapter functionality mask */
35 #define I2C_RDWR 0x0707 /* Combined R/W transfer (one STOP only) */
37 #define I2C_PEC 0x0708 /* != 0 to use PEC with SMBus */
38 #define I2C_SMBUS 0x0720 /* SMBus transfer */
|
| /linux/include/pcmcia/ |
| H A D | ciscode.h | 17 #define MANFID_3COM 0x0101
18 #define PRODID_3COM_3CXEM556 0x0035
19 #define PRODID_3COM_3CCFEM556 0x0556
20 #define PRODID_3COM_3C562 0x0562
22 #define MANFID_ACCTON 0x01bf
23 #define PRODID_ACCTON_EN2226 0x010a
25 #define MANFID_ADAPTEC 0x012f
26 #define PRODID_ADAPTEC_SCSI 0x0001
28 #define MANFID_ATT 0xffff
29 #define PRODID_ATT_KIT 0x0100
[all …]
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| /linux/sound/soc/mediatek/mt2701/ |
| H A D | mt2701-reg.h | 12 #define AUDIO_TOP_CON0 0x0000
13 #define AUDIO_TOP_CON4 0x0010
14 #define AUDIO_TOP_CON5 0x0014
15 #define AFE_DAIBT_CON0 0x001c
16 #define AFE_MRGIF_CON 0x003c
17 #define ASMI_TIMING_CON1 0x0100
18 #define ASMO_TIMING_CON1 0x0104
19 #define PWR1_ASM_CON1 0x0108
20 #define ASYS_TOP_CON 0x0600
21 #define ASYS_I2SIN1_CON 0x0604
[all …]
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| /linux/drivers/media/platform/samsung/s5p-g2d/ |
| H A D | g2d-regs.h | 10 #define SOFT_RESET_REG 0x0000 /* Software reset reg */
11 #define INTEN_REG 0x0004 /* Interrupt Enable reg */
12 #define INTC_PEND_REG 0x000C /* Interrupt Control Pending reg */
13 #define FIFO_STAT_REG 0x0010 /* Command FIFO Status reg */
14 #define AXI_ID_MODE_REG 0x0014 /* AXI Read ID Mode reg */
15 #define CACHECTL_REG 0x0018 /* Cache & Buffer clear reg */
16 #define AXI_MODE_REG 0x001C /* AXI Mode reg */
19 #define BITBLT_START_REG 0x0100 /* BitBLT Start reg */
20 #define BITBLT_COMMAND_REG 0x0104 /* Command reg for BitBLT */
23 #define ROTATE_REG 0x0200 /* Rotation reg */
[all …]
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| /linux/drivers/clk/mediatek/ |
| H A D | clk-mt7988-apmixed.c | 48 PLL(CLK_APMIXED_NETSYSPLL, "netsyspll", 0x0104, 0x0110, 0x00000001, 0, 0, 32, 0x0104, 4, 0,
49 0, 0, 0x0108, 0, 0x0104),
50 PLL(CLK_APMIXED_MPLL, "mpll", 0x0114, 0x0120, 0xff000001, HAVE_RST_BAR, 23, 32, 0x0114, 4,
51 0, 0, 0, 0x0118, 0, 0x0114),
52 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0124, 0x0130, 0xff000001, HAVE_RST_BAR, 23, 32, 0x0124, 4,
53 0, 0, 0, 0x0128, 0, 0x0124),
54 PLL(CLK_APMIXED_APLL2, "apll2", 0x0134, 0x0140, 0x00000001, 0, 0, 32, 0x0134, 4, 0x0704,
55 0x0700, 1, 0x0138, 0, 0x0134),
56 PLL(CLK_APMIXED_NET1PLL, "net1pll", 0x0144, 0x0150, 0xff000001, HAVE_RST_BAR, 23, 32,
57 0x0144, 4, 0, 0, 0, 0x0148, 0, 0x0144),
[all …]
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| /linux/arch/arm/boot/dts/nxp/imx/ |
| H A D | imx7d-pinfunc.h | 14 #define MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x0000 0x0030 0x0000 0x0 0x0
15 #define MX7D_PAD_LPSR_GPIO1_IO00__PWM4_OUT 0x0000 0x0030 0x0000 0x1 0x0
16 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_ANY 0x0000 0x0030 0x0000 0x2 0x0
17 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x0000 0x0030 0x0000 0x3 0x0
18 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG__RST_B_DEB 0x0000 0x0030 0x0000 0x4 0x0
19 #define MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x0004 0x0034 0x0000 0x0 0x0
20 #define MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x0004 0x0034 0x0000 0x1 0x0
21 #define MX7D_PAD_LPSR_GPIO1_IO01__CCM_ENET_REF_CLK3 0x0004 0x0034 0x0000 0x2 0x0
22 #define MX7D_PAD_LPSR_GPIO1_IO01__SAI1_MCLK 0x0004 0x0034 0x0000 0x3 0x0
23 #define MX7D_PAD_LPSR_GPIO1_IO01__ANATOP_24M_OUT 0x0004 0x0034 0x0000 0x4 0x0
[all …]
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| /linux/include/linux/mfd/mt6397/ |
| H A D | registers.h | 11 #define MT6397_CID 0x0100
12 #define MT6397_TOP_CKPDN 0x0102
13 #define MT6397_TOP_CKPDN_SET 0x0104
14 #define MT6397_TOP_CKPDN_CLR 0x0106
15 #define MT6397_TOP_CKPDN2 0x0108
16 #define MT6397_TOP_CKPDN2_SET 0x010A
17 #define MT6397_TOP_CKPDN2_CLR 0x010C
18 #define MT6397_TOP_GPIO_CKPDN 0x010E
19 #define MT6397_TOP_RST_CON 0x0114
20 #define MT6397_WRP_CKPDN 0x011A
[all …]
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| /linux/include/linux/mfd/mt6323/ |
| H A D | registers.h | 10 #define MT6323_CHR_CON0 0x0000
11 #define MT6323_CHR_CON1 0x0002
12 #define MT6323_CHR_CON2 0x0004
13 #define MT6323_CHR_CON3 0x0006
14 #define MT6323_CHR_CON4 0x0008
15 #define MT6323_CHR_CON5 0x000A
16 #define MT6323_CHR_CON6 0x000C
17 #define MT6323_CHR_CON7 0x000E
18 #define MT6323_CHR_CON8 0x0010
19 #define MT6323_CHR_CON9 0x0012
[all …]
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| /linux/include/video/ |
| H A D | aty128.h | 13 #define CLOCK_CNTL_INDEX 0x0008
14 #define CLOCK_CNTL_DATA 0x000c
15 #define BIOS_0_SCRATCH 0x0010
16 #define BUS_CNTL 0x0030
17 #define BUS_CNTL1 0x0034
18 #define GEN_INT_CNTL 0x0040
19 #define CRTC_GEN_CNTL 0x0050
20 #define CRTC_EXT_CNTL 0x0054
21 #define DAC_CNTL 0x0058
22 #define I2C_CNTL_1 0x0094
[all …]
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| /linux/drivers/net/ethernet/intel/iavf/ |
| H A D | iavf_adminq_cmd.h | 15 #define IAVF_FW_API_VERSION_MAJOR 0x0001
16 #define IAVF_FW_API_VERSION_MINOR_X722 0x0005
17 #define IAVF_FW_API_VERSION_MINOR_X710 0x0008
24 #define IAVF_MINOR_VER_GET_LINK_INFO_XL710 0x0007
29 iavf_aqc_opc_get_version = 0x0001,
30 iavf_aqc_opc_driver_version = 0x0002,
31 iavf_aqc_opc_queue_shutdown = 0x0003,
32 iavf_aqc_opc_set_pf_context = 0x0004,
35 iavf_aqc_opc_request_resource = 0x0008,
36 iavf_aqc_opc_release_resource = 0x0009,
[all …]
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| /linux/drivers/net/ethernet/hisilicon/hns3/hns3_common/ |
| H A D | hclge_comm_cmd.h | 10 #define HCLGE_COMM_CMD_FLAG_IN BIT(0)
18 #define HCLGE_COMM_LINK_EVENT_REPORT_EN_B 0
28 #define HCLGE_COMM_TYPE_CRQ 0
34 #define HCLGE_COMM_NIC_CSQ_BASEADDR_L_REG 0x27000
35 #define HCLGE_COMM_NIC_CSQ_BASEADDR_H_REG 0x27004
36 #define HCLGE_COMM_NIC_CSQ_DEPTH_REG 0x27008
37 #define HCLGE_COMM_NIC_CSQ_TAIL_REG 0x27010
38 #define HCLGE_COMM_NIC_CSQ_HEAD_REG 0x27014
39 #define HCLGE_COMM_NIC_CRQ_BASEADDR_L_REG 0x27018
40 #define HCLGE_COMM_NIC_CRQ_BASEADDR_H_REG 0x2701C
[all …]
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| /linux/sound/soc/codecs/ |
| H A D | rt700-sdw.h | 12 { 0x0000, 0x0000 },
13 { 0x0001, 0x0000 },
14 { 0x0002, 0x0000 },
15 { 0x0003, 0x0000 },
16 { 0x0004, 0x0000 },
17 { 0x0005, 0x0001 },
18 { 0x0020, 0x0000 },
19 { 0x0022, 0x0000 },
20 { 0x0023, 0x0000 },
21 { 0x0024, 0x0000 },
[all …]
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| H A D | rt1011.h | 11 #define RT1011_DEVICE_ID_NUM 0x1011
13 #define RT1011_RESET 0x0000
14 #define RT1011_CLK_1 0x0002
15 #define RT1011_CLK_2 0x0004
16 #define RT1011_CLK_3 0x0006
17 #define RT1011_CLK_4 0x0008
18 #define RT1011_PLL_1 0x000a
19 #define RT1011_PLL_2 0x000c
20 #define RT1011_SRC_1 0x000e
21 #define RT1011_SRC_2 0x0010
[all …]
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| /linux/drivers/net/ethernet/renesas/ |
| H A D | rtsn.h | 14 #define AXIBMI 0x0000
15 #define TSNMHD 0x1000
16 #define RMSO 0x2000
17 #define RMRO 0x3800
20 AXIWC = AXIBMI + 0x0000,
21 AXIRC = AXIBMI + 0x0004,
22 TDPC0 = AXIBMI + 0x0010,
23 TFT = AXIBMI + 0x0090,
24 TATLS0 = AXIBMI + 0x00a0,
25 TATLS1 = AXIBMI + 0x00a4,
[all …]
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| /linux/drivers/media/usb/gspca/ |
| H A D | stk014.c | 37 .priv = 0},
47 if (gspca_dev->usb_err < 0) in reg_r()
48 return 0; in reg_r()
49 ret = usb_control_msg(dev, usb_rcvctrlpipe(dev, 0), in reg_r()
50 0x00, in reg_r()
52 0x00, in reg_r()
56 if (ret < 0) { in reg_r()
59 return 0; in reg_r()
61 return gspca_dev->usb_buf[0]; in reg_r()
71 if (gspca_dev->usb_err < 0) in reg_w()
[all …]
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| /linux/drivers/net/ethernet/intel/i40e/ |
| H A D | i40e_adminq_cmd.h | 18 #define I40E_FW_API_VERSION_MAJOR 0x0001
19 #define I40E_FW_API_VERSION_MINOR_X722 0x000C
20 #define I40E_FW_API_VERSION_MINOR_X710 0x000F
27 #define I40E_MINOR_VER_GET_LINK_INFO_XL710 0x0007
29 #define I40E_MINOR_VER_GET_LINK_INFO_X722 0x0009
31 #define I40E_MINOR_VER_FW_LLDP_STOPPABLE_X722 0x0006
33 #define I40E_MINOR_VER_FW_REQUEST_FEC_X722 0x000A
38 i40e_aqc_opc_get_version = 0x0001,
39 i40e_aqc_opc_driver_version = 0x0002,
40 i40e_aqc_opc_queue_shutdown = 0x0003,
[all …]
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| /linux/drivers/ata/ |
| H A D | pata_pcmcia.c | 45 struct ata_device *master = &link->device[0]; in pcmcia_set_mode()
52 ATA_ID_FW_REV_LEN + ATA_ID_PROD_LEN) == 0) { in pcmcia_set_mode()
56 ATA_ID_SERNO_LEN) == 0 && master->id[ATA_ID_SERNO] >> 8) { in pcmcia_set_mode()
75 return 0; in pcmcia_set_mode_8bit()
126 for (count = 0; (ap->ops->sff_check_status(ap) & ATA_DRQ) in pcmcia_8bit_drain_fifo()
159 if ((pdev->resource[0]->flags & IO_DATA_PATH_WIDTH) in pcmcia_check_one_config()
161 pdev->resource[0]->flags &= ~IO_DATA_PATH_WIDTH; in pcmcia_check_one_config()
162 pdev->resource[0]->flags |= IO_DATA_PATH_WIDTH_AUTO; in pcmcia_check_one_config()
168 pdev->resource[0]->end = 8; in pcmcia_check_one_config()
171 if (pdev->resource[0]->end < 16) in pcmcia_check_one_config()
[all …]
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| /linux/include/linux/soc/samsung/ |
| H A D | exynos-regs-pmu.h | 17 #define S5P_CENTRAL_SEQ_CONFIGURATION 0x0200
21 #define S5P_CENTRAL_SEQ_OPTION 0x0208
42 #define EXYNOS_SWRESET 0x0400
44 #define S5P_WAKEUP_STAT 0x0600
46 #define EXYNOS_EINT_WAKEUP_MASK_DISABLED 0xffffffff
47 #define EXYNOS_EINT_WAKEUP_MASK 0x0604
48 #define S5P_WAKEUP_MASK 0x0608
49 #define S5P_WAKEUP_MASK2 0x0614
52 #define EXYNOS4_MIPI_PHY_CONTROL(n) (0x0710 + (n) * 4)
54 #define EXYNOS4_PHY_ENABLE (1 << 0)
[all …]
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| /linux/drivers/gpio/ |
| H A D | gpio-f7188x.c | 23 #define SIO_LDSEL 0x07 /* Logical device select */
24 #define SIO_DEVID 0x20 /* Device ID (2 bytes) */
26 #define SIO_UNLOCK_KEY 0x87 /* Key to enable Super-I/O */
27 #define SIO_LOCK_KEY 0xAA /* Key to disable Super-I/O */
32 #define SIO_FINTEK_DEVREV 0x22 /* Fintek Device revision */
33 #define SIO_FINTEK_MANID 0x23 /* Fintek ID (2 bytes) */
35 #define SIO_FINTEK_ID 0x1934 /* Manufacturer ID */
37 #define SIO_F71869_ID 0x0814 /* F71869 chipset ID */
38 #define SIO_F71869A_ID 0x1007 /* F71869A chipset ID */
39 #define SIO_F71882_ID 0x0541 /* F71882 chipset ID */
[all …]
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| /linux/drivers/watchdog/ |
| H A D | f71808e_wdt.c | 21 #define SIO_F71808FG_LD_WDT 0x07 /* Watchdog timer logical device */
22 #define SIO_UNLOCK_KEY 0x87 /* Key to enable Super-I/O */
23 #define SIO_LOCK_KEY 0xAA /* Key to disable Super-I/O */
25 #define SIO_REG_LDSEL 0x07 /* Logical device select */
26 #define SIO_REG_DEVID 0x20 /* Device ID (2 bytes) */
27 #define SIO_REG_DEVREV 0x22 /* Device revision */
28 #define SIO_REG_MANID 0x23 /* Fintek ID (2 bytes) */
29 #define SIO_REG_CLOCK_SEL 0x26 /* Clock select */
30 #define SIO_REG_ROM_ADDR_SEL 0x27 /* ROM address select */
31 #define SIO_F81866_REG_PORT_SEL 0x27 /* F81866 Multi-Function Register */
[all …]
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| /linux/drivers/usb/mtu3/ |
| H A D | mtu3_hw_regs.h | 14 #define SSUSB_DEV_BASE 0x0000
15 #define SSUSB_EPCTL_CSR_BASE 0x0800
16 #define SSUSB_USB3_MAC_CSR_BASE 0x1400
17 #define SSUSB_USB3_SYS_CSR_BASE 0x1400
18 #define SSUSB_USB2_CSR_BASE 0x2400
21 #define SSUSB_SIFSLV_IPPC_BASE 0x0000
25 #define U3D_LV1ISR (SSUSB_DEV_BASE + 0x0000)
26 #define U3D_LV1IER (SSUSB_DEV_BASE + 0x0004)
27 #define U3D_LV1IESR (SSUSB_DEV_BASE + 0x0008)
28 #define U3D_LV1IECR (SSUSB_DEV_BASE + 0x000C)
[all …]
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| /linux/drivers/mfd/ |
| H A D | wm8994-regmap.c | 18 { 0x0001, 0x0000 }, /* R1 - Power Management (1) */
19 { 0x0002, 0x6000 }, /* R2 - Power Management (2) */
20 { 0x0003, 0x0000 }, /* R3 - Power Management (3) */
21 { 0x0004, 0x0000 }, /* R4 - Power Management (4) */
22 { 0x0005, 0x0000 }, /* R5 - Power Management (5) */
23 { 0x0006, 0x0000 }, /* R6 - Power Management (6) */
24 { 0x0015, 0x0000 }, /* R21 - Input Mixer (1) */
25 { 0x0018, 0x008B }, /* R24 - Left Line Input 1&2 Volume */
26 { 0x0019, 0x008B }, /* R25 - Left Line Input 3&4 Volume */
27 { 0x001A, 0x008B }, /* R26 - Right Line Input 1&2 Volume */
[all …]
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