Lines Matching +full:0 +full:x0704
18 #define I40E_FW_API_VERSION_MAJOR 0x0001
19 #define I40E_FW_API_VERSION_MINOR_X722 0x000C
20 #define I40E_FW_API_VERSION_MINOR_X710 0x000F
27 #define I40E_MINOR_VER_GET_LINK_INFO_XL710 0x0007
29 #define I40E_MINOR_VER_GET_LINK_INFO_X722 0x0009
31 #define I40E_MINOR_VER_FW_LLDP_STOPPABLE_X722 0x0006
33 #define I40E_MINOR_VER_FW_REQUEST_FEC_X722 0x000A
38 i40e_aqc_opc_get_version = 0x0001,
39 i40e_aqc_opc_driver_version = 0x0002,
40 i40e_aqc_opc_queue_shutdown = 0x0003,
41 i40e_aqc_opc_set_pf_context = 0x0004,
44 i40e_aqc_opc_request_resource = 0x0008,
45 i40e_aqc_opc_release_resource = 0x0009,
47 i40e_aqc_opc_list_func_capabilities = 0x000A,
48 i40e_aqc_opc_list_dev_capabilities = 0x000B,
51 i40e_aqc_opc_set_proxy_config = 0x0104,
52 i40e_aqc_opc_set_ns_proxy_table_entry = 0x0105,
55 i40e_aqc_opc_mac_address_read = 0x0107,
56 i40e_aqc_opc_mac_address_write = 0x0108,
59 i40e_aqc_opc_clear_pxe_mode = 0x0110,
62 i40e_aqc_opc_set_wol_filter = 0x0120,
63 i40e_aqc_opc_get_wake_reason = 0x0121,
66 i40e_aqc_opc_get_switch_config = 0x0200,
67 i40e_aqc_opc_add_statistics = 0x0201,
68 i40e_aqc_opc_remove_statistics = 0x0202,
69 i40e_aqc_opc_set_port_parameters = 0x0203,
70 i40e_aqc_opc_get_switch_resource_alloc = 0x0204,
71 i40e_aqc_opc_set_switch_config = 0x0205,
72 i40e_aqc_opc_rx_ctl_reg_read = 0x0206,
73 i40e_aqc_opc_rx_ctl_reg_write = 0x0207,
75 i40e_aqc_opc_add_vsi = 0x0210,
76 i40e_aqc_opc_update_vsi_parameters = 0x0211,
77 i40e_aqc_opc_get_vsi_parameters = 0x0212,
79 i40e_aqc_opc_add_pv = 0x0220,
80 i40e_aqc_opc_update_pv_parameters = 0x0221,
81 i40e_aqc_opc_get_pv_parameters = 0x0222,
83 i40e_aqc_opc_add_veb = 0x0230,
84 i40e_aqc_opc_update_veb_parameters = 0x0231,
85 i40e_aqc_opc_get_veb_parameters = 0x0232,
87 i40e_aqc_opc_delete_element = 0x0243,
89 i40e_aqc_opc_add_macvlan = 0x0250,
90 i40e_aqc_opc_remove_macvlan = 0x0251,
91 i40e_aqc_opc_add_vlan = 0x0252,
92 i40e_aqc_opc_remove_vlan = 0x0253,
93 i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254,
94 i40e_aqc_opc_add_tag = 0x0255,
95 i40e_aqc_opc_remove_tag = 0x0256,
96 i40e_aqc_opc_add_multicast_etag = 0x0257,
97 i40e_aqc_opc_remove_multicast_etag = 0x0258,
98 i40e_aqc_opc_update_tag = 0x0259,
99 i40e_aqc_opc_add_control_packet_filter = 0x025A,
100 i40e_aqc_opc_remove_control_packet_filter = 0x025B,
101 i40e_aqc_opc_add_cloud_filters = 0x025C,
102 i40e_aqc_opc_remove_cloud_filters = 0x025D,
103 i40e_aqc_opc_clear_wol_switch_filters = 0x025E,
105 i40e_aqc_opc_add_mirror_rule = 0x0260,
106 i40e_aqc_opc_delete_mirror_rule = 0x0261,
109 i40e_aqc_opc_write_personalization_profile = 0x0270,
110 i40e_aqc_opc_get_personalization_profile_list = 0x0271,
113 i40e_aqc_opc_dcb_ignore_pfc = 0x0301,
114 i40e_aqc_opc_dcb_updated = 0x0302,
115 i40e_aqc_opc_set_dcb_parameters = 0x0303,
118 i40e_aqc_opc_configure_vsi_bw_limit = 0x0400,
119 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406,
120 i40e_aqc_opc_configure_vsi_tc_bw = 0x0407,
121 i40e_aqc_opc_query_vsi_bw_config = 0x0408,
122 i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A,
123 i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410,
125 i40e_aqc_opc_enable_switching_comp_ets = 0x0413,
126 i40e_aqc_opc_modify_switching_comp_ets = 0x0414,
127 i40e_aqc_opc_disable_switching_comp_ets = 0x0415,
128 i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416,
129 i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417,
130 i40e_aqc_opc_query_switching_comp_ets_config = 0x0418,
131 i40e_aqc_opc_query_port_ets_config = 0x0419,
132 i40e_aqc_opc_query_switching_comp_bw_config = 0x041A,
133 i40e_aqc_opc_suspend_port_tx = 0x041B,
134 i40e_aqc_opc_resume_port_tx = 0x041C,
135 i40e_aqc_opc_configure_partition_bw = 0x041D,
137 i40e_aqc_opc_query_hmc_resource_profile = 0x0500,
138 i40e_aqc_opc_set_hmc_resource_profile = 0x0501,
141 i40e_aqc_opc_get_phy_abilities = 0x0600,
142 i40e_aqc_opc_set_phy_config = 0x0601,
143 i40e_aqc_opc_set_mac_config = 0x0603,
144 i40e_aqc_opc_set_link_restart_an = 0x0605,
145 i40e_aqc_opc_get_link_status = 0x0607,
146 i40e_aqc_opc_set_phy_int_mask = 0x0613,
147 i40e_aqc_opc_get_local_advt_reg = 0x0614,
148 i40e_aqc_opc_set_local_advt_reg = 0x0615,
149 i40e_aqc_opc_get_partner_advt = 0x0616,
150 i40e_aqc_opc_set_lb_modes = 0x0618,
151 i40e_aqc_opc_get_phy_wol_caps = 0x0621,
152 i40e_aqc_opc_set_phy_debug = 0x0622,
153 i40e_aqc_opc_upload_ext_phy_fm = 0x0625,
154 i40e_aqc_opc_run_phy_activity = 0x0626,
155 i40e_aqc_opc_set_phy_register = 0x0628,
156 i40e_aqc_opc_get_phy_register = 0x0629,
159 i40e_aqc_opc_nvm_read = 0x0701,
160 i40e_aqc_opc_nvm_erase = 0x0702,
161 i40e_aqc_opc_nvm_update = 0x0703,
162 i40e_aqc_opc_nvm_config_read = 0x0704,
163 i40e_aqc_opc_nvm_config_write = 0x0705,
164 i40e_aqc_opc_oem_post_update = 0x0720,
165 i40e_aqc_opc_thermal_sensor = 0x0721,
168 i40e_aqc_opc_send_msg_to_pf = 0x0801,
169 i40e_aqc_opc_send_msg_to_vf = 0x0802,
170 i40e_aqc_opc_send_msg_to_peer = 0x0803,
173 i40e_aqc_opc_alternate_write = 0x0900,
174 i40e_aqc_opc_alternate_write_indirect = 0x0901,
175 i40e_aqc_opc_alternate_read = 0x0902,
176 i40e_aqc_opc_alternate_read_indirect = 0x0903,
177 i40e_aqc_opc_alternate_write_done = 0x0904,
178 i40e_aqc_opc_alternate_set_mode = 0x0905,
179 i40e_aqc_opc_alternate_clear_port = 0x0906,
182 i40e_aqc_opc_lldp_get_mib = 0x0A00,
183 i40e_aqc_opc_lldp_update_mib = 0x0A01,
184 i40e_aqc_opc_lldp_add_tlv = 0x0A02,
185 i40e_aqc_opc_lldp_update_tlv = 0x0A03,
186 i40e_aqc_opc_lldp_delete_tlv = 0x0A04,
187 i40e_aqc_opc_lldp_stop = 0x0A05,
188 i40e_aqc_opc_lldp_start = 0x0A06,
189 i40e_aqc_opc_get_cee_dcb_cfg = 0x0A07,
190 i40e_aqc_opc_lldp_set_local_mib = 0x0A08,
191 i40e_aqc_opc_lldp_stop_start_spec_agent = 0x0A09,
192 i40e_aqc_opc_lldp_restore = 0x0A0A,
195 i40e_aqc_opc_add_udp_tunnel = 0x0B00,
196 i40e_aqc_opc_del_udp_tunnel = 0x0B01,
197 i40e_aqc_opc_set_rss_key = 0x0B02,
198 i40e_aqc_opc_set_rss_lut = 0x0B03,
199 i40e_aqc_opc_get_rss_key = 0x0B04,
200 i40e_aqc_opc_get_rss_lut = 0x0B05,
203 i40e_aqc_opc_event_lan_overflow = 0x1001,
206 i40e_aqc_opc_oem_parameter_change = 0xFE00,
207 i40e_aqc_opc_oem_device_status_change = 0xFE01,
208 i40e_aqc_opc_oem_ocsd_initialize = 0xFE02,
209 i40e_aqc_opc_oem_ocbb_initialize = 0xFE03,
212 i40e_aqc_opc_debug_read_reg = 0xFF03,
213 i40e_aqc_opc_debug_write_reg = 0xFF04,
214 i40e_aqc_opc_debug_modify_reg = 0xFF07,
215 i40e_aqc_opc_debug_dump_internals = 0xFF08,
237 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) }
244 /* internal (0x00XX) commands */
246 /* Get version (direct 0x0001) */
256 /* Queue Shutdown (direct 0x0003) */
259 #define I40E_AQ_DRIVER_UNLOADING 0x1
265 /* Set PF context (0x0004, direct) */
273 /* Set CPPM Configuration (direct 0x0103) */
286 /* Set ARP Proxy command / response (indirect 0x0104) */
296 I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data);
298 /* Set NS Proxy Table Entry Command (indirect 0x0105) */
312 I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data);
314 /* Manage LAA Command (0x0106) - obsolete */
325 /* Manage MAC Address Read Command (indirect 0x0107) */
328 #define I40E_AQC_LAN_ADDR_VALID 0x10
329 #define I40E_AQC_PORT_ADDR_VALID 0x40
346 /* Manage MAC Address Write Command (0x0108) */
349 #define I40E_AQC_MC_MAG_EN 0x0100
350 #define I40E_AQC_WOL_PRESERVE_ON_PFR 0x0200
351 #define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000
352 #define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000
353 #define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000
362 /* PXE commands (0x011x) */
364 /* Clear PXE Command and response (direct 0x0110) */
372 /* Set WoL Filter (0x0120) */
391 I40E_CHECK_STRUCT_LEN(0x90, i40e_aqc_set_wol_filter_data);
393 /* Get Wake Reason (0x0121) */
403 /* Switch configuration commands (0x02xx) */
417 /* Get Switch Configuration command (indirect 0x0200)
440 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp);
442 /* Get Switch Configuration (indirect 0x0200)
451 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp);
453 /* Add Statistics (direct 0x0201)
454 * Remove Statistics (direct 0x0202)
465 /* Set Port Parameters command (direct 0x0203) */
475 /* Get Switch Resource Allocation (indirect 0x0204) */
496 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp);
498 /* Set Switch Configuration (direct 0x0205) */
502 #define I40E_AQ_SET_SWITCH_CFG_PROMISC 0x0001
506 * of 0x88a8 (802.1ad). Should be zero for firmware API
514 * zero for their defaults of 0x8100 (802.1Q). Should be zero
520 * Bit 7 : 0 : No action, 1: Switch to mode defined by bits 6:0
521 * Bit 6 : 0 : Destination Port, 1: source port
523 * 0: rsvd
527 * Bits 3:0 Mode
528 * 0: default mode
533 #define I40E_AQ_SET_SWITCH_BIT7_VALID 0x80
536 #define I40E_AQ_SET_SWITCH_L4_TYPE_TCP 0x10
538 #define I40E_AQ_SET_SWITCH_MODE_NON_TUNNEL 0x02
545 /* Read Receive control registers (direct 0x0206)
546 * Write Receive control registers (direct 0x0207)
559 /* Add VSI (indirect 0x0210)
563 * Update VSI (indirect 0x211)
566 * Get VSI (indirect 0x0212)
572 #define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1
577 #define I40E_AQ_VSI_TYPE_VF 0x0
578 #define I40E_AQ_VSI_TYPE_VMDQ2 0x1
579 #define I40E_AQ_VSI_TYPE_PF 0x2
600 #define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001
601 #define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002
602 #define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004
603 #define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040
604 #define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080
605 #define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200
608 #define I40E_AQ_VSI_SW_ID_SHIFT 0x0000
609 #define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT)
610 #define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000
611 #define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000
615 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02
616 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04
622 #define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00
623 #define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \
625 #define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01
626 #define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03
627 #define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04
628 #define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03
629 #define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \
631 #define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0
632 #define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10
633 #define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18
644 #define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0
645 #define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1
648 #define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0
652 #define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10
653 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40
663 #define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF
671 /* Add Port Virtualizer (direct 0x0220)
672 * also used for update PV (direct 0x0221) but only flags are used
692 /* Get PV Params (direct 0x0222)
706 /* Add VEB (direct 0x0230) */
711 #define I40E_AQC_ADD_VEB_FLOATING 0x1
712 #define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2
713 #define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4
714 #define I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS 0x10
733 /* Get VEB Parameters (direct 0x0232)
739 __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */
748 /* Delete Element (direct 0x0243)
752 /* Add MAC-VLAN (indirect 0x0250) */
758 #define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000
770 #define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001
771 #define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004
772 #define I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC 0x0010
776 #define I40E_AQC_MM_ERR_NO_RES 0xFF
791 /* Remove MAC-VLAN (indirect 0x0251)
800 #define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01
801 #define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08
808 /* Add VLAN (indirect 0x0252)
809 * Remove VLAN (indirect 0x0253)
828 /* Set VSI Promiscuous Modes (direct 0x0254) */
833 #define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01
834 #define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02
835 #define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04
836 #define I40E_AQC_SET_VSI_DEFAULT 0x08
837 #define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10
838 #define I40E_AQC_SET_VSI_PROMISC_RX_ONLY 0x8000
841 #define I40E_AQC_SET_VSI_VLAN_VALID 0x8000
847 /* Add S/E-tag command (direct 0x0255)
868 /* Remove S/E-tag command (direct 0x0256)
879 /* Add multicast E-Tag (direct 0x0257)
880 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields
905 /* Update S/E-Tag (direct 0x0259) */
923 /* Add Control Packet filter (direct 0x025A)
924 * Remove Control Packet filter (direct 0x025B)
932 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001
933 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002
934 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008
935 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000
953 /* Add Cloud filters (indirect 0x025C)
954 * Remove Cloud filters (indirect 0x025D)
988 /* 0x0000 reserved */
989 /* 0x0001 reserved */
990 /* 0x0002 reserved */
991 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003
992 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004
993 /* 0x0005 reserved */
994 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006
995 /* 0x0007 reserved */
996 /* 0x0008 reserved */
997 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009
998 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A
999 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B
1000 #define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C
1001 /* 0x000D reserved */
1002 /* 0x000E reserved */
1003 /* 0x000F reserved */
1004 /* 0x0010 to 0x0017 is for custom filters */
1005 #define I40E_AQC_ADD_CLOUD_FILTER_IP_PORT 0x0010 /* Dest IP + L4 Port */
1006 #define I40E_AQC_ADD_CLOUD_FILTER_MAC_PORT 0x0011 /* Dest MAC + L4 Port */
1007 #define I40E_AQC_ADD_CLOUD_FILTER_MAC_VLAN_PORT 0x0012 /* Dest MAC + VLAN + L4 Port */
1009 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0
1010 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100
1013 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00
1026 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_cloud_filters_element_data);
1037 I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_cloud_filters_element_bb);
1050 /* Replace filter Command 0x025F
1078 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_replace_cloud_filters_cmd_buf);
1080 /* Add Mirror Rule (indirect or direct 0x0260)
1081 * Delete Mirror Rule (indirect or direct 0x0261)
1088 #define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0
1089 #define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \
1141 /* DCB 0x03xx*/
1143 /* PFC Ignore (direct 0x0301)
1154 /* DCB Update (direct 0x0302) uses the i40e_aq_desc structure
1158 /* TX scheduler 0x04xx */
1177 /* Configure VSI BW limits (direct 0x0400) */
1183 u8 max_credit; /* 0-3, limit = 2^max */
1189 /* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406)
1197 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1202 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data);
1204 /* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407)
1215 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data);
1217 /* Query vsi bw configuration (indirect 0x0408) */
1226 u8 max_bw; /* 0-3, limit = 2^max */
1230 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp);
1232 /* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */
1239 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1243 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp);
1245 /* Configure Switching Component Bandwidth Limit (direct 0x0410) */
1251 u8 max_bw; /* 0-3, limit = 2^max */
1257 /* Enable Physical Port ETS (indirect 0x0413)
1258 * Modify Physical Port ETS (indirect 0x0414)
1259 * Disable Physical Port ETS (indirect 0x0415)
1271 I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data);
1273 /* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */
1279 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1284 I40E_CHECK_STRUCT_LEN(0x40,
1288 * (indirect 0x0417)
1298 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data);
1300 /* Query Switching Component Configuration (indirect 0x0418) */
1306 u8 tc_bw_max; /* 0-3, limit = 2^max */
1310 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp);
1312 /* Query PhysicalPort ETS Configuration (indirect 0x0419) */
1322 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */
1327 I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp);
1330 * (indirect 0x041A)
1339 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1343 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp);
1346 * (direct 0x041B and 0x041C) uses the generic SEID struct
1350 * (indirect 0x041D)
1358 I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data);
1361 * (direct 0x0500) and (direct 0x0501)
1372 /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */
1378 /* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */
1381 #define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001
1382 #define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002
1385 I40E_PHY_TYPE_SGMII = 0x0,
1386 I40E_PHY_TYPE_1000BASE_KX = 0x1,
1387 I40E_PHY_TYPE_10GBASE_KX4 = 0x2,
1388 I40E_PHY_TYPE_10GBASE_KR = 0x3,
1389 I40E_PHY_TYPE_40GBASE_KR4 = 0x4,
1390 I40E_PHY_TYPE_XAUI = 0x5,
1391 I40E_PHY_TYPE_XFI = 0x6,
1392 I40E_PHY_TYPE_SFI = 0x7,
1393 I40E_PHY_TYPE_XLAUI = 0x8,
1394 I40E_PHY_TYPE_XLPPI = 0x9,
1395 I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA,
1396 I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB,
1397 I40E_PHY_TYPE_10GBASE_AOC = 0xC,
1398 I40E_PHY_TYPE_40GBASE_AOC = 0xD,
1399 I40E_PHY_TYPE_UNRECOGNIZED = 0xE,
1400 I40E_PHY_TYPE_UNSUPPORTED = 0xF,
1401 I40E_PHY_TYPE_100BASE_TX = 0x11,
1402 I40E_PHY_TYPE_1000BASE_T = 0x12,
1403 I40E_PHY_TYPE_10GBASE_T = 0x13,
1404 I40E_PHY_TYPE_10GBASE_SR = 0x14,
1405 I40E_PHY_TYPE_10GBASE_LR = 0x15,
1406 I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16,
1407 I40E_PHY_TYPE_10GBASE_CR1 = 0x17,
1408 I40E_PHY_TYPE_40GBASE_CR4 = 0x18,
1409 I40E_PHY_TYPE_40GBASE_SR4 = 0x19,
1410 I40E_PHY_TYPE_40GBASE_LR4 = 0x1A,
1411 I40E_PHY_TYPE_1000BASE_SX = 0x1B,
1412 I40E_PHY_TYPE_1000BASE_LX = 0x1C,
1413 I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D,
1414 I40E_PHY_TYPE_20GBASE_KR2 = 0x1E,
1415 I40E_PHY_TYPE_25GBASE_KR = 0x1F,
1416 I40E_PHY_TYPE_25GBASE_CR = 0x20,
1417 I40E_PHY_TYPE_25GBASE_SR = 0x21,
1418 I40E_PHY_TYPE_25GBASE_LR = 0x22,
1419 I40E_PHY_TYPE_25GBASE_AOC = 0x23,
1420 I40E_PHY_TYPE_25GBASE_ACC = 0x24,
1421 I40E_PHY_TYPE_2_5GBASE_T = 0x26,
1422 I40E_PHY_TYPE_5GBASE_T = 0x27,
1423 I40E_PHY_TYPE_2_5GBASE_T_LINK_STATUS = 0x30,
1424 I40E_PHY_TYPE_5GBASE_T_LINK_STATUS = 0x31,
1426 I40E_PHY_TYPE_NOT_SUPPORTED_HIGH_TEMP = 0xFD,
1427 I40E_PHY_TYPE_EMPTY = 0xFE,
1428 I40E_PHY_TYPE_DEFAULT = 0xFF,
1470 #define I40E_LINK_SPEED_2_5GB_SHIFT 0x0
1471 #define I40E_LINK_SPEED_100MB_SHIFT 0x1
1472 #define I40E_LINK_SPEED_1000MB_SHIFT 0x2
1473 #define I40E_LINK_SPEED_10GB_SHIFT 0x3
1474 #define I40E_LINK_SPEED_40GB_SHIFT 0x4
1475 #define I40E_LINK_SPEED_20GB_SHIFT 0x5
1476 #define I40E_LINK_SPEED_25GB_SHIFT 0x6
1477 #define I40E_LINK_SPEED_5GB_SHIFT 0x7
1480 I40E_LINK_SPEED_UNKNOWN = 0,
1499 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc);
1505 #define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01
1506 #define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02
1511 #define I40E_AQ_PHY_TYPE_EXT_25G_KR 0X01
1512 #define I40E_AQ_PHY_TYPE_EXT_25G_CR 0X02
1513 #define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04
1514 #define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08
1516 #define I40E_AQ_REQUEST_FEC_KR 0x04
1517 #define I40E_AQ_REQUEST_FEC_RS 0x08
1518 #define I40E_AQ_ENABLE_FEC_AUTO 0x10
1528 I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp);
1530 /* Set PHY Config (direct 0x0601) */
1535 /* bits 0-2 use the values from get_phy_abilities_resp */
1536 #define I40E_AQ_PHY_ENABLE_LINK 0x08
1537 #define I40E_AQ_PHY_ENABLE_AN 0x10
1538 #define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20
1543 #define I40E_AQ_PHY_TYPE_EXT_25G_KR 0X01
1544 #define I40E_AQ_PHY_TYPE_EXT_25G_CR 0X02
1545 #define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04
1546 #define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08
1548 #define I40E_AQ_SET_FEC_ABILITY_KR BIT(0)
1553 #define I40E_AQ_PHY_FEC_CONFIG_SHIFT 0x0
1554 #define I40E_AQ_PHY_FEC_CONFIG_MASK (0x1F << I40E_AQ_PHY_FEC_CONFIG_SHIFT)
1560 /* Set MAC Config command data structure (direct 0x0603) */
1573 /* Restart Auto-Negotiation (direct 0x605) */
1576 #define I40E_AQ_PHY_RESTART_AN 0x02
1577 #define I40E_AQ_PHY_LINK_ENABLE 0x04
1583 /* Get Link Status cmd & response data structure (direct 0x0607) */
1586 #define I40E_AQ_LSE_DISABLE 0x2
1587 #define I40E_AQ_LSE_ENABLE 0x3
1589 #define I40E_AQ_LSE_IS_ENABLED 0x1
1593 #define I40E_AQ_LINK_UP 0x01 /* obsolete */
1594 #define I40E_AQ_MEDIA_AVAILABLE 0x40
1596 #define I40E_AQ_AN_COMPLETED 0x01
1597 #define I40E_AQ_LINK_PAUSE_TX 0x20
1598 #define I40E_AQ_LINK_PAUSE_RX 0x40
1599 #define I40E_AQ_QUALIFIED_MODULE 0x80
1603 #define I40E_AQ_LOOPBACK_MASK 0x07
1606 #define I40E_AQ_CONFIG_FEC_KR_ENA 0x01
1607 #define I40E_AQ_CONFIG_FEC_RS_ENA 0x02
1608 #define I40E_AQ_CONFIG_CRC_ENA 0x04
1609 #define I40E_AQ_CONFIG_PACING_MASK 0x78
1624 /* Set event mask command (direct 0x613) */
1628 #define I40E_AQ_EVENT_LINK_UPDOWN 0x0002
1629 #define I40E_AQ_EVENT_MEDIA_NA 0x0004
1630 #define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100
1636 /* Get Local AN advt register (direct 0x0614)
1637 * Set Local AN advt register (direct 0x0615)
1638 * Get Link Partner AN advt register (direct 0x0616)
1648 /* Set Loopback mode (0x0618) */
1651 #define I40E_LEGACY_LOOPBACK_NVM_VER 0x6000
1652 #define I40E_AQ_LB_MAC_LOCAL 0x01
1653 #define I40E_AQ_LB_PHY_LOCAL 0x05
1654 #define I40E_AQ_LB_PHY_REMOTE 0x06
1655 #define I40E_AQ_LB_MAC_LOCAL_LEGACY 0x04
1661 /* Set PHY Debug command (0x0622) */
1665 #define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10
1667 #define I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW 0x20
1674 I40E_AQC_PHY_REG_INTERNAL = 0x1,
1675 I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2,
1676 I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3
1679 /* Run PHY Activity (0x0626) */
1691 /* Set PHY Register command (0x0628) */
1692 /* Get PHY Register command (0x0629) */
1699 #define I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE 0x01
1700 #define I40E_AQ_PHY_REG_ACCESS_SET_MDIO_IF_NUMBER 0x02
1702 #define I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_MASK (0x3 << \
1712 /* NVM Read command (indirect 0x0701)
1713 * NVM Erase commands (direct 0x0702)
1714 * NVM Update commands (indirect 0x0703)
1718 #define I40E_AQ_NVM_LAST_CMD 0x01
1719 #define I40E_AQ_NVM_REARRANGE_TO_FLAT 0x20
1720 #define I40E_AQ_NVM_REARRANGE_TO_STRUCT 0x40
1722 #define I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED 0x03
1723 #define I40E_AQ_NVM_PRESERVATION_FLAGS_ALL 0x01
1733 /* NVM Config Read (indirect 0x0704) */
1745 /* NVM Config Write (indirect 0x0705) */
1756 /* Used for 0x0704 as well as for 0x0705 commands */
1763 I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature);
1772 I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field);
1774 /* OEM Post Update (indirect 0x0720)
1782 I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update);
1791 I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer);
1793 /* Thermal Sensor (indirect 0x0721)
1806 /* Send to PF command (indirect 0x0801) id is only used by PF
1807 * Send to VF command (indirect 0x0802) id is only used by PF
1808 * Send to Peer PF command (indirect 0x0803)
1821 /* Direct write (direct 0x0900)
1822 * Direct read (direct 0x0902)
1833 /* Indirect write (indirect 0x0901)
1834 * Indirect read (indirect 0x0903)
1846 /* Done alternate write (direct 0x0904)
1856 /* Set OEM mode (direct 0x0905) */
1864 /* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */
1866 /* async events 0x10xx */
1868 /* Lan Queue Overflow Event (direct, 0x1001) */
1877 /* Get LLDP MIB (indirect 0x0A00) */
1881 #define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3
1882 #define I40E_AQ_LLDP_MIB_LOCAL 0x0
1883 #define I40E_AQ_LLDP_MIB_REMOTE 0x1
1884 #define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC
1885 #define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2
1886 #define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0
1897 /* Configure LLDP MIB Change Event (direct 0x0A01)
1902 #define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1
1910 /* Add LLDP TLV (indirect 0x0A02)
1911 * Delete LLDP TLV (indirect 0x0A04)
1914 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
1924 /* Update LLDP TLV (indirect 0x0A03) */
1926 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
1937 /* Stop LLDP (direct 0x0A05) */
1940 #define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1
1941 #define I40E_AQ_LLDP_AGENT_STOP_PERSIST 0x2
1947 /* Start LLDP (direct 0x0A06) */
1950 #define I40E_AQ_LLDP_AGENT_START 0x1
1951 #define I40E_AQ_LLDP_AGENT_START_PERSIST 0x2
1957 /* Set DCB (direct 0x0303) */
1960 #define I40E_AQ_DCB_SET_AGENT 0x1
1961 #define I40E_DCB_VALID 0x1
1968 /* Get CEE DCBX Oper Config (0x0A07)
1973 #define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0
1974 #define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT)
1975 #define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3
1976 #define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT)
1977 #define I40E_AQC_CEE_APP_FIP_SHIFT 0x8
1978 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)
1980 #define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0
1981 #define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT)
1982 #define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3
1983 #define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT)
1984 #define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8
1985 #define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT)
1986 #define I40E_AQC_CEE_FCOE_STATUS_SHIFT 0x8
1987 #define I40E_AQC_CEE_FCOE_STATUS_MASK (0x7 << I40E_AQC_CEE_FCOE_STATUS_SHIFT)
1988 #define I40E_AQC_CEE_ISCSI_STATUS_SHIFT 0xB
1989 #define I40E_AQC_CEE_ISCSI_STATUS_MASK (0x7 << I40E_AQC_CEE_ISCSI_STATUS_SHIFT)
1990 #define I40E_AQC_CEE_FIP_STATUS_SHIFT 0x10
1991 #define I40E_AQC_CEE_FIP_STATUS_MASK (0x7 << I40E_AQC_CEE_FIP_STATUS_SHIFT)
2014 I40E_CHECK_STRUCT_LEN(0x18, i40e_aqc_get_cee_dcb_cfg_v1_resp);
2022 #define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0
2023 #define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT)
2024 #define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3
2025 #define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT)
2026 #define I40E_AQC_CEE_APP_FIP_SHIFT 0x8
2027 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)
2028 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)
2030 #define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0
2031 #define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT)
2032 #define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3
2033 #define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT)
2034 #define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8
2035 #define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT)
2039 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp);
2041 /* Set Local LLDP MIB (indirect 0x0A08)
2045 #define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT 0
2048 #define SET_LOCAL_MIB_AC_TYPE_LOCAL_MIB 0x0
2052 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS 0x1
2063 /* Stop/Start LLDP Agent (direct 0x0A09)
2073 /* Restore LLDP Agent factory settings (direct 0x0A0A) */
2076 #define I40E_AQ_LLDP_AGENT_RESTORE 0x1
2082 /* Add Udp Tunnel command and completion (direct 0x0B00) */
2087 #define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00
2088 #define I40E_AQC_TUNNEL_TYPE_NGE 0x01
2104 /* remove UDP Tunnel command (0x0B01) */
2107 u8 index; /* 0 to 15 */
2115 u8 index; /* 0 to 15 */
2125 #define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0
2126 #define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \
2137 u8 standard_rss_key[0x28];
2138 u8 extended_hash_key[0xc];
2141 I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data);
2145 #define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0
2146 #define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \
2149 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0
2152 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0
2162 /* tunnel key structure 0x0B10 */
2167 u8 key1_len; /* 0 to 15 */
2168 u8 key2_len; /* 0 to 15 */
2176 /* OEM mode commands (direct 0xFE0x) */
2193 /* Initialize OCSD (0xFE02, direct) */
2204 /* Initialize OCBB (0xFE03, direct) */
2217 /* get device id (0xFF00) uses the generic structure */
2219 /* set test more (0xFF01, internal) */
2232 /* Debug Read Register command (0xFF03)
2233 * Debug Write Register command (0xFF04)
2244 /* Scatter/gather Reg Read (indirect 0xFF05)
2245 * Scatter/gather Reg Write (indirect 0xFF06)
2254 /* Debug Modify register (direct 0xFF07) */
2264 /* dump internal data (0xFF08, indirect) */