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12

/linux/arch/arm/mach-omap1/
H A Dopp_data.c21 { 216000000, 12000000, 216000000, 0x050d, 0x2910, /* 1/1/2/2/2/8 */
23 { 195000000, 13000000, 195000000, 0x050e, 0x2790, /* 1/1/2/2/4/8 */
25 { 192000000, 19200000, 192000000, 0x050f, 0x2510, /* 1/1/2/2/8/8 */
27 { 192000000, 12000000, 192000000, 0x050f, 0x2810, /* 1/1/2/2/8/8 */
29 { 96000000, 12000000, 192000000, 0x055f, 0x2810, /* 2/2/2/2/8/8 */
31 { 48000000, 12000000, 192000000, 0x0baf, 0x2810, /* 4/4/4/8/8/8 */
33 { 24000000, 12000000, 192000000, 0x0fff, 0x2810, /* 8/8/8/8/8/8 */
35 { 182000000, 13000000, 182000000, 0x050e, 0x2710, /* 1/1/2/2/4/8 */
37 { 168000000, 12000000, 168000000, 0x010f, 0x2710, /* 1/1/1/2/8/8 */
39 { 150000000, 12000000, 150000000, 0x010a, 0x2cb0, /* 1/1/1/2/4/4 */
[all …]
/linux/drivers/media/rc/keymaps/
H A Drc-avermedia-rm-ks.c15 { 0x0501, KEY_POWER2 }, /* Power (RED POWER BUTTON) */
16 { 0x0502, KEY_CHANNELUP }, /* Channel+ */
17 { 0x0503, KEY_CHANNELDOWN }, /* Channel- */
18 { 0x0504, KEY_VOLUMEUP }, /* Volume+ */
19 { 0x0505, KEY_VOLUMEDOWN }, /* Volume- */
20 { 0x0506, KEY_MUTE }, /* Mute */
21 { 0x0507, KEY_AGAIN }, /* Recall */
22 { 0x0508, KEY_VIDEO }, /* Source */
23 { 0x0509, KEY_NUMERIC_1 }, /* 1 */
24 { 0x050a, KEY_NUMERIC_2 }, /* 2 */
[all …]
/linux/drivers/net/dsa/microchip/
H A Dksz_ptp_reg.h9 #define REG_SW_GLOBAL_LED_OVR__4 0x0120
11 #define LED_OVR_1 BIT(0)
13 #define REG_SW_GLOBAL_LED_SRC__4 0x0128
18 #define REG_PTP_CLK_CTRL 0x0500
26 #define PTP_CLK_RESET BIT(0)
28 #define REG_PTP_RTC_SUB_NANOSEC__2 0x0502
30 #define PTP_RTC_SUB_NANOSEC_M 0x0007
31 #define PTP_RTC_0NS 0x00
33 #define REG_PTP_RTC_NANOSEC 0x0504
35 #define REG_PTP_RTC_SEC 0x0508
[all …]
H A Dksz9477_reg.h11 #define KS_PRIO_M 0x7
14 /* 0 - Operation */
15 #define REG_CHIP_ID0__1 0x0000
17 #define REG_CHIP_ID1__1 0x0001
19 #define FAMILY_ID 0x95
20 #define FAMILY_ID_94 0x94
21 #define FAMILY_ID_95 0x95
22 #define FAMILY_ID_85 0x85
23 #define FAMILY_ID_98 0x98
24 #define FAMILY_ID_88 0x88
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/
H A Dgpcgk104.fuc3.h3 /* 0x0000: gpc_mmio_list_head */
4 0x0000006c,
5 /* 0x0004: gpc_mmio_list_tail */
6 /* 0x0004: tpc_mmio_list_head */
7 0x0000006c,
8 /* 0x0008: tpc_mmio_list_tail */
9 /* 0x0008: unk_mmio_list_head */
10 0x0000006c,
11 /* 0x000c: unk_mmio_list_tail */
12 0x0000006c,
[all …]
H A Dgpcgk110.fuc3.h3 /* 0x0000: gpc_mmio_list_head */
4 0x0000006c,
5 /* 0x0004: gpc_mmio_list_tail */
6 /* 0x0004: tpc_mmio_list_head */
7 0x0000006c,
8 /* 0x0008: tpc_mmio_list_tail */
9 /* 0x0008: unk_mmio_list_head */
10 0x0000006c,
11 /* 0x000c: unk_mmio_list_tail */
12 0x0000006c,
[all …]
H A Dgpcgf117.fuc3.h3 /* 0x0000: gpc_mmio_list_head */
4 0x0000006c,
5 /* 0x0004: gpc_mmio_list_tail */
6 /* 0x0004: tpc_mmio_list_head */
7 0x0000006c,
8 /* 0x0008: tpc_mmio_list_tail */
9 /* 0x0008: unk_mmio_list_head */
10 0x0000006c,
11 /* 0x000c: unk_mmio_list_tail */
12 0x0000006c,
[all …]
/linux/include/linux/mfd/mt6323/
H A Dregisters.h10 #define MT6323_CHR_CON0 0x0000
11 #define MT6323_CHR_CON1 0x0002
12 #define MT6323_CHR_CON2 0x0004
13 #define MT6323_CHR_CON3 0x0006
14 #define MT6323_CHR_CON4 0x0008
15 #define MT6323_CHR_CON5 0x000A
16 #define MT6323_CHR_CON6 0x000C
17 #define MT6323_CHR_CON7 0x000E
18 #define MT6323_CHR_CON8 0x0010
19 #define MT6323_CHR_CON9 0x0012
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_offset.h27 // base address: 0x1fb00
28 …UVD_PGFSM_CONFIG 0x00c0
30 …UVD_PGFSM_STATUS 0x00c1
32 …UVD_POWER_STATUS 0x00c4
34 …CC_UVD_HARVESTING 0x00c7
36 …UVD_DPG_LMA_CTL 0x00d1
38 …UVD_DPG_LMA_DATA 0x00d2
40 …UVD_DPG_LMA_MASK 0x00d3
42 …UVD_DPG_PAUSE 0x00d4
44 …UVD_SCRATCH1 0x00d5
[all …]
/linux/sound/soc/codecs/
H A Drt1011.h11 #define RT1011_DEVICE_ID_NUM 0x1011
13 #define RT1011_RESET 0x0000
14 #define RT1011_CLK_1 0x0002
15 #define RT1011_CLK_2 0x0004
16 #define RT1011_CLK_3 0x0006
17 #define RT1011_CLK_4 0x0008
18 #define RT1011_PLL_1 0x000a
19 #define RT1011_PLL_2 0x000c
20 #define RT1011_SRC_1 0x000e
21 #define RT1011_SRC_2 0x0010
[all …]
H A Dwm5100-tables.c815 { 0x0000, 0x0000 }, /* R0 - software reset */
816 { 0x0001, 0x0000 }, /* R1 - Device Revision */
817 { 0x0010, 0x0801 }, /* R16 - Ctrl IF 1 */
818 { 0x0020, 0x0000 }, /* R32 - Tone Generator 1 */
819 { 0x0030, 0x0000 }, /* R48 - PWM Drive 1 */
820 { 0x0031, 0x0100 }, /* R49 - PWM Drive 2 */
821 { 0x0032, 0x0100 }, /* R50 - PWM Drive 3 */
822 { 0x0100, 0x0002 }, /* R256 - Clocking 1 */
823 { 0x0101, 0x0000 }, /* R257 - Clocking 3 */
824 { 0x0102, 0x0011 }, /* R258 - Clocking 4 */
[all …]
/linux/fs/exfat/
H A Dnls.c16 #define UTBL_COUNT (0x10000)
24 0x0000, 0x0001, 0x0002, 0x0003, 0x0004, 0x0005, 0x0006, 0x0007,
25 0x0008, 0x0009, 0x000a, 0x000b, 0x000c, 0x000d, 0x000e, 0x000f,
26 0x0010, 0x0011, 0x0012, 0x0013, 0x0014, 0x0015, 0x0016, 0x0017,
27 0x0018, 0x0019, 0x001a, 0x001b, 0x001c, 0x001d, 0x001e, 0x001f,
28 0x0020, 0x0021, 0x0022, 0x0023, 0x0024, 0x0025, 0x0026, 0x0027,
29 0x0028, 0x0029, 0x002a, 0x002b, 0x002c, 0x002d, 0x002e, 0x002f,
30 0x0030, 0x0031, 0x0032, 0x0033, 0x0034, 0x0035, 0x0036, 0x0037,
31 0x0038, 0x0039, 0x003a, 0x003b, 0x003c, 0x003d, 0x003e, 0x003f,
32 0x0040, 0x0041, 0x0042, 0x0043, 0x0044, 0x0045, 0x0046, 0x0047,
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/gmc/
H A Dgmc_6_0_d.h26 #define ixMC_IO_DEBUG_ACMD_CLKSEL_D0 0x00CE
27 #define ixMC_IO_DEBUG_ACMD_CLKSEL_D1 0x00DE
28 #define ixMC_IO_DEBUG_ACMD_MISC_D0 0x00AE
29 #define ixMC_IO_DEBUG_ACMD_MISC_D1 0x00BE
30 #define ixMC_IO_DEBUG_ACMD_OFSCAL_D0 0x00EE
31 #define ixMC_IO_DEBUG_ACMD_OFSCAL_D1 0x00FE
32 #define ixMC_IO_DEBUG_ACMD_RXPHASE_D0 0x010E
33 #define ixMC_IO_DEBUG_ACMD_RXPHASE_D1 0x011E
34 #define ixMC_IO_DEBUG_ACMD_TXBST_PD_D0 0x018E
35 #define ixMC_IO_DEBUG_ACMD_TXBST_PD_D1 0x019E
[all …]
/linux/drivers/gpu/drm/msm/adreno/
H A Da6xx_gpu_state.h16 0x8000, 0x8006, 0x8010, 0x8092, 0x8094, 0x809d, 0x80a0, 0x80a6,
17 0x80af, 0x80f1, 0x8100, 0x8107, 0x8109, 0x8109, 0x8110, 0x8110,
18 0x8400, 0x840b,
22 0x8800, 0x8806, 0x8809, 0x8811, 0x8818, 0x881e, 0x8820, 0x8865,
23 0x8870, 0x8879, 0x8880, 0x8889, 0x8890, 0x8891, 0x8898, 0x8898,
24 0x88c0, 0x88c1, 0x88d0, 0x88e3, 0x8900, 0x890c, 0x890f, 0x891a,
25 0x8c00, 0x8c01, 0x8c08, 0x8c10, 0x8c17, 0x8c1f, 0x8c26, 0x8c33,
29 0x88f0, 0x88f3, 0x890d, 0x890e, 0x8927, 0x8928, 0x8bf0, 0x8bf1,
30 0x8c02, 0x8c07, 0x8c11, 0x8c16, 0x8c20, 0x8c25,
34 0x9200, 0x9216, 0x9218, 0x9236, 0x9300, 0x9306,
[all …]
/linux/drivers/media/dvb-frontends/
H A Dlgdt3305.c37 __ret = (ret < 0); \
58 #define LGDT3305_GEN_CTRL_1 0x0000
59 #define LGDT3305_GEN_CTRL_2 0x0001
60 #define LGDT3305_GEN_CTRL_3 0x0002
61 #define LGDT3305_GEN_STATUS 0x0003
62 #define LGDT3305_GEN_CONTROL 0x0007
63 #define LGDT3305_GEN_CTRL_4 0x000a
64 #define LGDT3305_DGTL_AGC_REF_1 0x0012
65 #define LGDT3305_DGTL_AGC_REF_2 0x0013
66 #define LGDT3305_CR_CTR_FREQ_1 0x0106
[all …]
/linux/drivers/net/wireless/broadcom/b43legacy/
H A Dmain.c55 MODULE_PARM_DESC(pio, "enable(1) / disable(0) PIO mode");
57 # define modparam_pio 0
64 MODULE_PARM_DESC(bad_frames_preempt, "enable(1) / disable(0) Bad Frames"
95 RATETAB_ENT(B43legacy_CCK_RATE_1MB, 0),
99 RATETAB_ENT(B43legacy_OFDM_RATE_6MB, 0),
100 RATETAB_ENT(B43legacy_OFDM_RATE_9MB, 0),
101 RATETAB_ENT(B43legacy_OFDM_RATE_12MB, 0),
102 RATETAB_ENT(B43legacy_OFDM_RATE_18MB, 0),
103 RATETAB_ENT(B43legacy_OFDM_RATE_24MB, 0),
104 RATETAB_ENT(B43legacy_OFDM_RATE_36MB, 0),
[all …]
/linux/fs/smb/client/
H A Dwinucase.c23 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
24 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
25 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
26 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
27 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
28 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
29 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
30 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
31 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
32 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_offset.h12 // base address: 0x0
13 …VGA_MEM_WRITE_PAGE_ADDR 0x0000
14 …ne mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0
15 …VGA_MEM_READ_PAGE_ADDR 0x0001
16 …ne mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 0
17 …VGA_RENDER_CONTROL 0x0000
19 …VGA_SEQUENCER_RESET_CONTROL 0x0001
21 …VGA_MODE_CONTROL 0x0002
23 …VGA_SURFACE_PITCH_SELECT 0x0003
25 …VGA_MEMORY_BASE_ADDRESS 0x0004
[all …]
H A Ddcn_2_0_1_offset.h27 // base address: 0x0
28 …PHYPLLA_PIXCLK_RESYNC_CNTL 0x0040
30 …PHYPLLB_PIXCLK_RESYNC_CNTL 0x0041
32 …DP_DTO_DBUF_EN 0x0044
34 …DPREFCLK_CGTT_BLK_CTRL_REG 0x0048
36 …REFCLK_CNTL 0x0049
38 …REFCLK_CGTT_BLK_CTRL_REG 0x004b
40 …DCCG_PERFMON_CNTL2 0x004e
42 …DCCG_DS_DTO_INCR 0x0053
44 …DCCG_DS_DTO_MODULO 0x0054
[all …]
H A Ddcn_3_0_1_offset.h27 // base address: 0x48
28 …VGA_MEM_WRITE_PAGE_ADDR 0x0000
29 …ne mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0
30 …VGA_MEM_READ_PAGE_ADDR 0x0001
31 …ne mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 0
35 // base address: 0x3b4
36 …CRTC8_IDX 0x002d
38 …CRTC8_DATA 0x002d
40 …GENFC_WT 0x002e
42 …GENS1 0x002e
[all …]
H A Ddcn_3_2_0_offset.h27 // base address: 0x0
28 …DENTIST_DISPCLK_CNTL 0x0064
33 // base address: 0x0
34 …PHYPLLA_PIXCLK_RESYNC_CNTL 0x0040
36 …PHYPLLB_PIXCLK_RESYNC_CNTL 0x0041
38 …PHYPLLC_PIXCLK_RESYNC_CNTL 0x0042
40 …PHYPLLD_PIXCLK_RESYNC_CNTL 0x0043
42 …DP_DTO_DBUF_EN 0x0044
44 …DSCCLK3_DTO_PARAM 0x0045
46 …DPREFCLK_CGTT_BLK_CTRL_REG 0x0048
[all …]
H A Ddcn_3_2_1_offset.h27 // base address: 0x0
28 …DENTIST_DISPCLK_CNTL 0x0064
33 // base address: 0x0
34 …PHYPLLA_PIXCLK_RESYNC_CNTL 0x0040
36 …PHYPLLB_PIXCLK_RESYNC_CNTL 0x0041
38 …PHYPLLC_PIXCLK_RESYNC_CNTL 0x0042
40 …PHYPLLD_PIXCLK_RESYNC_CNTL 0x0043
42 …DP_DTO_DBUF_EN 0x0044
44 …DSCCLK3_DTO_PARAM 0x0045
46 …DPREFCLK_CGTT_BLK_CTRL_REG 0x0048
[all …]
/linux/fs/hfsplus/
H A Dtables.c24 // High-byte indices ( == 0 iff no case mapping and no ignorables )
27 /* 0 */ 0x0100, 0x0200, 0x0000, 0x0300, 0x0400, 0x0500, 0x0000, 0x0000,
28 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
29 /* 1 */ 0x0600, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
30 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
31 /* 2 */ 0x0700, 0x0800, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
32 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
33 /* 3 */ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
34 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
35 /* 4 */ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
[all …]
/linux/drivers/mfd/
H A Dcs47l92-tables.c21 { 0x3A2, 0x2C29 },
22 { 0x3A3, 0x0E00 },
23 { 0x281, 0x0000 },
24 { 0x282, 0x0000 },
25 { 0x4EA, 0x0100 },
26 { 0x22B, 0x0000 },
27 { 0x4A0, 0x0080 },
28 { 0x4A1, 0x0000 },
29 { 0x4A2, 0x0000 },
30 { 0x180B, 0x033F },
[all …]
/linux/sound/usb/
H A Dmixer_quirks.c84 cval->min = 0; in snd_create_std_mono_ctl_offset()
86 cval->res = 0; in snd_create_std_mono_ctl_offset()
87 cval->dBmin = 0; in snd_create_std_mono_ctl_offset()
88 cval->dBmax = 0; in snd_create_std_mono_ctl_offset()
104 kctl->vd[0].access |= in snd_create_std_mono_ctl_offset()
121 val_type, 0 /* Offset */, in snd_create_std_mono_ctl()
137 if (err < 0) in snd_create_std_mono_table()
142 return 0; in snd_create_std_mono_table()
189 { USB_ID(0x041e, 0x3000), 0, 1, 2, 1, 18, 0x0013 }, /* Extigy */
190 { USB_ID(0x041e, 0x3020), 2, 1, 6, 6, 18, 0x0013 }, /* Audigy 2 NX */
[all …]

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