Lines Matching +full:0 +full:x050e
37 __ret = (ret < 0); \
58 #define LGDT3305_GEN_CTRL_1 0x0000
59 #define LGDT3305_GEN_CTRL_2 0x0001
60 #define LGDT3305_GEN_CTRL_3 0x0002
61 #define LGDT3305_GEN_STATUS 0x0003
62 #define LGDT3305_GEN_CONTROL 0x0007
63 #define LGDT3305_GEN_CTRL_4 0x000a
64 #define LGDT3305_DGTL_AGC_REF_1 0x0012
65 #define LGDT3305_DGTL_AGC_REF_2 0x0013
66 #define LGDT3305_CR_CTR_FREQ_1 0x0106
67 #define LGDT3305_CR_CTR_FREQ_2 0x0107
68 #define LGDT3305_CR_CTR_FREQ_3 0x0108
69 #define LGDT3305_CR_CTR_FREQ_4 0x0109
70 #define LGDT3305_CR_MSE_1 0x011b
71 #define LGDT3305_CR_MSE_2 0x011c
72 #define LGDT3305_CR_LOCK_STATUS 0x011d
73 #define LGDT3305_CR_CTRL_7 0x0126
74 #define LGDT3305_AGC_POWER_REF_1 0x0300
75 #define LGDT3305_AGC_POWER_REF_2 0x0301
76 #define LGDT3305_AGC_DELAY_PT_1 0x0302
77 #define LGDT3305_AGC_DELAY_PT_2 0x0303
78 #define LGDT3305_RFAGC_LOOP_FLTR_BW_1 0x0306
79 #define LGDT3305_RFAGC_LOOP_FLTR_BW_2 0x0307
80 #define LGDT3305_IFBW_1 0x0308
81 #define LGDT3305_IFBW_2 0x0309
82 #define LGDT3305_AGC_CTRL_1 0x030c
83 #define LGDT3305_AGC_CTRL_4 0x0314
84 #define LGDT3305_EQ_MSE_1 0x0413
85 #define LGDT3305_EQ_MSE_2 0x0414
86 #define LGDT3305_EQ_MSE_3 0x0415
87 #define LGDT3305_PT_MSE_1 0x0417
88 #define LGDT3305_PT_MSE_2 0x0418
89 #define LGDT3305_PT_MSE_3 0x0419
90 #define LGDT3305_FEC_BLOCK_CTRL 0x0504
91 #define LGDT3305_FEC_LOCK_STATUS 0x050a
92 #define LGDT3305_FEC_PKT_ERR_1 0x050c
93 #define LGDT3305_FEC_PKT_ERR_2 0x050d
94 #define LGDT3305_TP_CTRL_1 0x050e
95 #define LGDT3305_BERT_PERIOD 0x0801
96 #define LGDT3305_BERT_ERROR_COUNT_1 0x080a
97 #define LGDT3305_BERT_ERROR_COUNT_2 0x080b
98 #define LGDT3305_BERT_ERROR_COUNT_3 0x080c
99 #define LGDT3305_BERT_ERROR_COUNT_4 0x080d
104 u8 buf[] = { reg >> 8, reg & 0xff, val }; in lgdt3305_write_reg()
106 .addr = state->cfg->i2c_addr, .flags = 0, in lgdt3305_write_reg()
110 lg_reg("reg: 0x%04x, val: 0x%02x\n", reg, val); in lgdt3305_write_reg()
116 msg.buf[0], msg.buf[1], msg.buf[2], ret); in lgdt3305_write_reg()
117 if (ret < 0) in lgdt3305_write_reg()
122 return 0; in lgdt3305_write_reg()
128 u8 reg_buf[] = { reg >> 8, reg & 0xff }; in lgdt3305_read_reg()
131 .flags = 0, .buf = reg_buf, .len = 2 }, in lgdt3305_read_reg()
136 lg_reg("reg: 0x%04x\n", reg); in lgdt3305_read_reg()
143 if (ret < 0) in lgdt3305_read_reg()
148 return 0; in lgdt3305_read_reg()
156 __val = 0; \
166 lg_reg("reg: 0x%04x, bit: %d, level: %d\n", reg, bit, onoff); in lgdt3305_set_reg_bit()
192 for (i = 0; i < len - 1; i++) { in lgdt3305_write_regs()
197 return 0; in lgdt3305_write_regs()
208 ret = lgdt3305_set_reg_bit(state, LGDT3305_GEN_CTRL_3, 0, 0); in lgdt3305_soft_reset()
213 ret = lgdt3305_set_reg_bit(state, LGDT3305_GEN_CTRL_3, 0, 1); in lgdt3305_soft_reset()
239 val &= ~0x09; in lgdt3305_mpeg_mode_polarity()
242 val |= 0x08; in lgdt3305_mpeg_mode_polarity()
244 val |= 0x40; in lgdt3305_mpeg_mode_polarity()
246 val |= 0x01; in lgdt3305_mpeg_mode_polarity()
269 opermode &= ~0x03; in lgdt3305_set_modulation()
273 opermode |= 0x03; in lgdt3305_set_modulation()
276 opermode |= 0x00; in lgdt3305_set_modulation()
279 opermode |= 0x01; in lgdt3305_set_modulation()
296 val = 0; in lgdt3305_set_filter_extension()
307 return lgdt3305_set_reg_bit(state, 0x043f, 2, val); in lgdt3305_set_filter_extension()
319 agc_ref = 0x32c4; in lgdt3305_passband_digital_agc()
322 agc_ref = 0x2a00; in lgdt3305_passband_digital_agc()
325 agc_ref = 0x2a80; in lgdt3305_passband_digital_agc()
331 lg_dbg("agc ref: 0x%04x\n", agc_ref); in lgdt3305_passband_digital_agc()
334 lgdt3305_write_reg(state, LGDT3305_DGTL_AGC_REF_2, agc_ref & 0xff); in lgdt3305_passband_digital_agc()
336 return 0; in lgdt3305_passband_digital_agc()
346 agcdelay = 0x04c0; in lgdt3305_rfagc_loop()
347 rfbw = 0x8000; in lgdt3305_rfagc_loop()
348 ifbw = 0x8000; in lgdt3305_rfagc_loop()
352 agcdelay = 0x046b; in lgdt3305_rfagc_loop()
353 rfbw = 0x8889; in lgdt3305_rfagc_loop()
357 ifbw = 0x6666; in lgdt3305_rfagc_loop()
359 ifbw = 0x8888; in lgdt3305_rfagc_loop()
366 lg_dbg("agcdelay: 0x%04x, rfbw: 0x%04x\n", agcdelay, rfbw); in lgdt3305_rfagc_loop()
372 agcdelay & 0xff); in lgdt3305_rfagc_loop()
377 rfbw & 0xff); in lgdt3305_rfagc_loop()
379 lg_dbg("ifbw: 0x%04x\n", ifbw); in lgdt3305_rfagc_loop()
383 lgdt3305_write_reg(state, LGDT3305_IFBW_2, ifbw & 0xff); in lgdt3305_rfagc_loop()
386 return 0; in lgdt3305_rfagc_loop()
396 lockdten = 0; in lgdt3305_agc_setup()
397 acqen = 0; in lgdt3305_agc_setup()
413 lgdt3305_write_reg(state, 0x0314, 0xe1 | lockdten << 1); in lgdt3305_agc_setup()
414 lgdt3305_set_reg_bit(state, 0x030e, 2, acqen); in lgdt3305_agc_setup()
417 lgdt3305_write_reg(state, LGDT3305_AGC_CTRL_4, 0xe1 | lockdten << 1); in lgdt3305_agc_setup()
430 u16 usref = 0; in lgdt3305_set_agc_power_ref()
450 lg_dbg("set manual mode: 0x%04x\n", usref); in lgdt3305_set_agc_power_ref()
455 0xff & (usref >> 8)); in lgdt3305_set_agc_power_ref()
457 0xff & (usref >> 0)); in lgdt3305_set_agc_power_ref()
459 return 0; in lgdt3305_set_agc_power_ref()
475 inversion ? 0xf9 : 0x79); in lgdt3305_spectral_inversion()
480 inversion ? 0xfd : 0xff); in lgdt3305_spectral_inversion()
523 nco1 = (nco >> 24) & 0x3f; in lgdt3305_set_if()
524 nco1 |= 0x40; in lgdt3305_set_if()
525 nco2 = (nco >> 16) & 0xff; in lgdt3305_set_if()
526 nco3 = (nco >> 8) & 0xff; in lgdt3305_set_if()
527 nco4 = nco & 0xff; in lgdt3305_set_if()
537 return 0; in lgdt3305_set_if()
547 return 0; in lgdt3305_i2c_gate_ctrl()
552 enable ? 0 : 1); in lgdt3305_i2c_gate_ctrl()
566 gen_ctrl_3 &= ~0x01; in lgdt3305_sleep()
568 gen_ctrl_3 |= 0x02; in lgdt3305_sleep()
570 gen_ctrl_3 |= 0x04; in lgdt3305_sleep()
573 gen_ctrl_4 &= ~0x01; in lgdt3305_sleep()
575 gen_ctrl_4 &= ~0x02; in lgdt3305_sleep()
580 return 0; in lgdt3305_sleep()
589 { .reg = LGDT3305_GEN_CTRL_1, .val = 0x03, }, in lgdt3305_init()
590 { .reg = 0x000d, .val = 0x02, }, in lgdt3305_init()
591 { .reg = 0x000e, .val = 0x02, }, in lgdt3305_init()
592 { .reg = LGDT3305_DGTL_AGC_REF_1, .val = 0x32, }, in lgdt3305_init()
593 { .reg = LGDT3305_DGTL_AGC_REF_2, .val = 0xc4, }, in lgdt3305_init()
594 { .reg = LGDT3305_CR_CTR_FREQ_1, .val = 0x00, }, in lgdt3305_init()
595 { .reg = LGDT3305_CR_CTR_FREQ_2, .val = 0x00, }, in lgdt3305_init()
596 { .reg = LGDT3305_CR_CTR_FREQ_3, .val = 0x00, }, in lgdt3305_init()
597 { .reg = LGDT3305_CR_CTR_FREQ_4, .val = 0x00, }, in lgdt3305_init()
598 { .reg = LGDT3305_CR_CTRL_7, .val = 0xf9, }, in lgdt3305_init()
599 { .reg = 0x0112, .val = 0x17, }, in lgdt3305_init()
600 { .reg = 0x0113, .val = 0x15, }, in lgdt3305_init()
601 { .reg = 0x0114, .val = 0x18, }, in lgdt3305_init()
602 { .reg = 0x0115, .val = 0xff, }, in lgdt3305_init()
603 { .reg = 0x0116, .val = 0x3c, }, in lgdt3305_init()
604 { .reg = 0x0214, .val = 0x67, }, in lgdt3305_init()
605 { .reg = 0x0424, .val = 0x8d, }, in lgdt3305_init()
606 { .reg = 0x0427, .val = 0x12, }, in lgdt3305_init()
607 { .reg = 0x0428, .val = 0x4f, }, in lgdt3305_init()
608 { .reg = LGDT3305_IFBW_1, .val = 0x80, }, in lgdt3305_init()
609 { .reg = LGDT3305_IFBW_2, .val = 0x00, }, in lgdt3305_init()
610 { .reg = 0x030a, .val = 0x08, }, in lgdt3305_init()
611 { .reg = 0x030b, .val = 0x9b, }, in lgdt3305_init()
612 { .reg = 0x030d, .val = 0x00, }, in lgdt3305_init()
613 { .reg = 0x030e, .val = 0x1c, }, in lgdt3305_init()
614 { .reg = 0x0314, .val = 0xe1, }, in lgdt3305_init()
615 { .reg = 0x000d, .val = 0x82, }, in lgdt3305_init()
616 { .reg = LGDT3305_TP_CTRL_1, .val = 0x5b, }, in lgdt3305_init()
617 { .reg = LGDT3305_TP_CTRL_1, .val = 0x5b, }, in lgdt3305_init()
621 { .reg = LGDT3305_GEN_CTRL_1, .val = 0x03, }, in lgdt3305_init()
622 { .reg = LGDT3305_GEN_CTRL_2, .val = 0xb0, }, in lgdt3305_init()
623 { .reg = LGDT3305_GEN_CTRL_3, .val = 0x01, }, in lgdt3305_init()
624 { .reg = LGDT3305_GEN_CONTROL, .val = 0x6f, }, in lgdt3305_init()
625 { .reg = LGDT3305_GEN_CTRL_4, .val = 0x03, }, in lgdt3305_init()
626 { .reg = LGDT3305_DGTL_AGC_REF_1, .val = 0x32, }, in lgdt3305_init()
627 { .reg = LGDT3305_DGTL_AGC_REF_2, .val = 0xc4, }, in lgdt3305_init()
628 { .reg = LGDT3305_CR_CTR_FREQ_1, .val = 0x00, }, in lgdt3305_init()
629 { .reg = LGDT3305_CR_CTR_FREQ_2, .val = 0x00, }, in lgdt3305_init()
630 { .reg = LGDT3305_CR_CTR_FREQ_3, .val = 0x00, }, in lgdt3305_init()
631 { .reg = LGDT3305_CR_CTR_FREQ_4, .val = 0x00, }, in lgdt3305_init()
632 { .reg = LGDT3305_CR_CTRL_7, .val = 0x79, }, in lgdt3305_init()
633 { .reg = LGDT3305_AGC_POWER_REF_1, .val = 0x32, }, in lgdt3305_init()
634 { .reg = LGDT3305_AGC_POWER_REF_2, .val = 0xc4, }, in lgdt3305_init()
635 { .reg = LGDT3305_AGC_DELAY_PT_1, .val = 0x0d, }, in lgdt3305_init()
636 { .reg = LGDT3305_AGC_DELAY_PT_2, .val = 0x30, }, in lgdt3305_init()
637 { .reg = LGDT3305_RFAGC_LOOP_FLTR_BW_1, .val = 0x80, }, in lgdt3305_init()
638 { .reg = LGDT3305_RFAGC_LOOP_FLTR_BW_2, .val = 0x00, }, in lgdt3305_init()
639 { .reg = LGDT3305_IFBW_1, .val = 0x80, }, in lgdt3305_init()
640 { .reg = LGDT3305_IFBW_2, .val = 0x00, }, in lgdt3305_init()
641 { .reg = LGDT3305_AGC_CTRL_1, .val = 0x30, }, in lgdt3305_init()
642 { .reg = LGDT3305_AGC_CTRL_4, .val = 0x61, }, in lgdt3305_init()
643 { .reg = LGDT3305_FEC_BLOCK_CTRL, .val = 0xff, }, in lgdt3305_init()
644 { .reg = LGDT3305_TP_CTRL_1, .val = 0x1b, }, in lgdt3305_init()
680 fe->ops.i2c_gate_ctrl(fe, 0); in lgdt3304_set_parameters()
698 /* reg 0x030d is 3304-only... seen in vsb and qam usbsnoops... */ in lgdt3304_set_parameters()
701 lgdt3305_write_reg(state, 0x030d, 0x00); in lgdt3304_set_parameters()
702 lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_1, 0x4f); in lgdt3304_set_parameters()
703 lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_2, 0x0c); in lgdt3304_set_parameters()
704 lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_3, 0xac); in lgdt3304_set_parameters()
705 lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_4, 0xba); in lgdt3304_set_parameters()
709 lgdt3305_write_reg(state, 0x030d, 0x14); in lgdt3304_set_parameters()
721 ? 1 : 0); in lgdt3304_set_parameters()
748 fe->ops.i2c_gate_ctrl(fe, 0); in lgdt3305_set_parameters()
769 ret = lgdt3305_write_reg(state, LGDT3305_GEN_CONTROL, 0x2f); in lgdt3305_set_parameters()
781 ? 1 : 0); in lgdt3305_set_parameters()
810 return 0; in lgdt3305_get_frontend()
822 *locked = 0; in lgdt3305_read_cr_lock_status()
834 switch (val & 0x07) { in lgdt3305_read_cr_lock_status()
835 case 0: in lgdt3305_read_cr_lock_status()
872 *locked = 0; in lgdt3305_read_fec_lock_status()
882 mpeg_lock = (val & (1 << 0)) ? 1 : 0; in lgdt3305_read_fec_lock_status()
883 fec_lock = (val & (1 << 2)) ? 1 : 0; in lgdt3305_read_fec_lock_status()
884 viterbi_lock = (val & (1 << 3)) ? 1 : 0; in lgdt3305_read_fec_lock_status()
908 *status = 0; in lgdt3305_read_status()
914 signal = (val & (1 << 4)) ? 1 : 0; in lgdt3305_read_status()
915 inlock = (val & (1 << 3)) ? 0 : 1; in lgdt3305_read_status()
916 sync_lock = (val & (1 << 2)) ? 1 : 0; in lgdt3305_read_status()
917 nofecerr = (val & (1 << 1)) ? 1 : 0; in lgdt3305_read_status()
918 snrgood = (val & (1 << 0)) ? 1 : 0; in lgdt3305_read_status()
970 if (mse == 0) /* no signal */ in calculate_snr()
971 return 0; in calculate_snr()
977 API only allows for unsigned values, so just return 0 */ in calculate_snr()
978 return 0; in calculate_snr()
994 noise = ((read_reg(state, LGDT3305_PT_MSE_1) & 0x07) << 16) | in lgdt3305_read_snr()
996 (read_reg(state, LGDT3305_PT_MSE_3) & 0xff); in lgdt3305_read_snr()
1001 noise = ((read_reg(state, LGDT3305_EQ_MSE_1) & 0x0f) << 16) | in lgdt3305_read_snr()
1003 (read_reg(state, LGDT3305_EQ_MSE_3) & 0xff); in lgdt3305_read_snr()
1010 (read_reg(state, LGDT3305_CR_MSE_2) & 0xff); in lgdt3305_read_snr()
1022 lg_dbg("noise = 0x%08x, snr = %d.%02d dB\n", noise, in lgdt3305_read_snr()
1023 state->snr >> 24, (((state->snr >> 8) & 0xffff) * 100) >> 16); in lgdt3305_read_snr()
1025 return 0; in lgdt3305_read_snr()
1042 *strength = 0; in lgdt3305_read_signal_strength()
1048 /* scale the range 0 - 35*2^24 into 0 - 65535 */ in lgdt3305_read_signal_strength()
1049 if (state->snr >= 8960 * 0x10000) in lgdt3305_read_signal_strength()
1050 *strength = 0xffff; in lgdt3305_read_signal_strength()
1061 *ber = 0; in lgdt3305_read_ber()
1062 return 0; in lgdt3305_read_ber()
1071 (read_reg(state, LGDT3305_FEC_PKT_ERR_2) & 0xff); in lgdt3305_read_ucblocks()
1073 return 0; in lgdt3305_read_ucblocks()
1082 return 0; in lgdt3305_get_tune_settings()
1103 i2c_adap ? i2c_adapter_id(i2c_adap) : 0, in lgdt3305_attach()
1104 config ? config->i2c_addr : 0); in lgdt3305_attach()
1129 if ((lg_fail(ret)) | (val == 0)) in lgdt3305_attach()
1131 ret = lgdt3305_write_reg(state, 0x0808, 0x80); in lgdt3305_attach()
1134 ret = lgdt3305_read_reg(state, 0x0808, &val); in lgdt3305_attach()
1135 if ((lg_fail(ret)) | (val != 0x80)) in lgdt3305_attach()
1137 ret = lgdt3305_write_reg(state, 0x0808, 0x00); in lgdt3305_attach()