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/freebsd/sys/contrib/device-tree/Bindings/display/msm/
H A Dhdmi.txt29 - pinctrl-0: the default pinctrl state (active)
40 - #phy-cells: Number of cells in a PHY specifier; Should be 0.
63 reg = <0x04a00000 0x2f0>;
64 interrupts = <GIC_SPI 79 0>;
80 pinctrl-0 = <&hpd_active &ddc_active &cec_active>;
91 reg = <0x4a00400 0x60>,
92 <0x4a00500 0x100>;
93 #phy-cells = <0>;
H A Dhdmi.yaml90 port@0:
101 - port@0
164 reg = <0x04a00000 0x2f0>;
176 pinctrl-0 = <&hpd_active &ddc_active &cec_active>;
189 reg = <0x009a0000 0x50c>,
190 <0x00070000 0x6158>,
191 <0x009e0000 0xfff>;
214 pinctrl-0 = <&hdmi_hpd_active &hdmi_ddc_active>;
222 #size-cells = <0>;
224 port@0 {
[all …]
/freebsd/sys/contrib/device-tree/Bindings/display/ti/
H A Dti,am65x-dss.yaml85 port@0:
123 port@0: false
144 reg = <0x04a00000 0x1000>, /* common */
145 <0x04a02000 0x1000>, /* vidl1 */
146 <0x04a06000 0x1000>, /* vid */
147 <0x04a0700
[all...]
H A Dti,j721e-dss.yaml27 - description: common_s0 DSS Shared common 0
91 - description: common_s0 DSS Shared common 0
113 port@0:
159 reg = <0x04a00000 0x10000>, /* common_m */
160 <0x04a10000 0x10000>, /* common_s0*/
161 <0x04b00000 0x10000>, /* common_s1*/
162 <0x04b10000 0x10000>, /* common_s2*/
163 <0x04a20000 0x10000>, /* vidl1 */
164 <0x04a30000 0x10000>, /* vidl2 */
165 <0x04a50000 0x10000>, /* vid1 */
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/ti/
H A Dk3-am62-mcu.dtsi12 reg = <0x00 0x04084000 0x00 0x88>;
15 pinctrl-single,function-mask = <0xffffffff>;
21 reg = <0x00 0x4100000 0x00 0x1000>;
22 ti,esm-pins = <0>, <
[all...]
H A Dk3-am62a-mcu.dtsi11 reg = <0x00 0x04084000 0x00 0x88>;
14 pinctrl-single,function-mask = <0xffffffff>;
25 reg = <0x00 0x4800000 0x00 0x400>;
35 reg = <0x0
[all...]
H A Dk3-am64-mcu.dtsi16 reg = <0x00 0x4800000 0x00 0x400>;
26 reg = <0x00 0x4810000 0x00 0x400>;
36 reg = <0x00 0x482000
[all...]
H A Dk3-am65-main.dtsi12 reg = <0x0 0x70000000 0x0 0x200000>;
15 ranges = <0x0 0x0 0x70000000 0x200000>;
17 atf-sram@0 {
18 reg = <0x
[all...]
H A Dk3-j721e-main.dtsi15 #clock-cells = <0>;
17 clock-frequency = <0>;
21 #clock-cells = <0>;
23 clock-frequency = <0>;
30 reg = <0x0 0x70000000 0x0 0x800000>;
33 ranges = <0x0 0x
[all...]
/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dsm6125.dtsi24 #clock-cells = <0>;
30 #clock-cells = <0>;
38 #size-cells = <0>;
40 CPU0: cpu@0 {
43 reg = <0x0 0x0>;
57 reg = <0x0 0x1>;
66 reg = <0x0 0x
[all...]
H A Dqcm2290.dtsi30 #clock-cells = <0>;
36 #clock-cells = <0>;
42 #size-cells = <0>;
44 CPU0: cpu@0 {
47 reg = <0x0 0x0>;
48 clocks = <&cpufreq_hw 0>;
53 qcom,freq-domain = <&cpufreq_hw 0>;
66 reg = <0x0 0x
[all...]
H A Dsm6375.dtsi27 #clock-cells = <0>;
33 #clock-cells = <0>;
39 #size-cells = <0>;
41 CPU0: cpu@0 {
44 reg = <0x0 0x0>;
45 clocks = <&cpufreq_hw 0>;
48 qcom,freq-domain = <&cpufreq_hw 0>;
70 reg = <0x0 0x10
[all...]
H A Dsm6115.dtsi29 #clock-cells = <0>;
34 #clock-cells = <0>;
40 #size-cells = <0>;
42 CPU0: cpu@0 {
45 reg = <0x0 0x0>;
46 clocks = <&cpufreq_hw 0>;
51 qcom,freq-domain = <&cpufreq_hw 0>;
64 reg = <0x0 0x
[all...]
/freebsd/sys/contrib/device-tree/src/arm/qcom/
H A Dqcom-apq8064.dtsi25 reg = <0x80000000 0x200000>;
30 reg = <0x8f000000 0x700000>;
37 #size-cells = <0>;
39 CPU0: cpu@0 {
43 reg = <0>;
100 memory@0 {
102 reg = <0x0 0x
[all...]
/freebsd/tools/test/iconv/ref/
H A DUTF-32BE-rev1 0x00 = 0x00000000
2 0x01 = 0x01000000
3 0x02 = 0x02000000
4 0x03 = 0x03000000
5 0x04 = 0x04000000
6 0x05 = 0x05000000
7 0x06 = 0x06000000
8 0x07 = 0x07000000
9 0x08 = 0x08000000
10 0x09 = 0x09000000
[all …]
/freebsd/sys/dev/qlnx/qlnxe/
H A Decore_init_values.h35 0x00030003, 0xffff0000, /* if phase != 'engine', skip 3 ops (no DMAE) */
36 0x00020002, 0x00020000, /* if mode != '!asic', skip 2 ops */
37 0x0280c201, 0x00000000, /* write 0x0 to address 0x50184 */
38 0x02810201, 0x00000000, /* write 0x0 to address 0x50204 */
40 0x00110003, 0xffff0000, /* if phase != 'engine', skip 17 ops (no DMAE) */
41 0x00030002, 0x00020000, /* if mode != '!asic', skip 3 ops */
42 0x0048c201, 0x00000000, /* write 0x0 to address 0x9184 */
43 0x0048d201, 0x00000000, /* write 0x0 to address 0x91a4 */
44 0x004ba601, 0x00000001, /* write 0x1 to address 0x974c */
45 0x00020002, 0x00be0000, /* if mode != '(!asic)&bb', skip 2 ops */
[all …]