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/linux/arch/arm/include/debug/
H A Dclps711x.S7 #define CLPS711X_UART_PADDR (0x80000000 + 0x0000)
8 #define CLPS711X_UART_VADDR (0xfeff4000 + 0x0000)
10 #define CLPS711X_UART_PADDR (0x80000000 + 0x1000)
11 #define CLPS711X_UART_VADDR (0xfeff4000 + 0x1000)
14 #define SYSFLG (0x0140)
16 #define UARTDR (0x0480)
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6ul-pinfunc.h13 #define MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x0014 0x02a0 0x0000 5 0
14 #define MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x0018 0x02a4 0x0000 5 0
16 #define MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x001c 0x02a8 0x0000 5 0
17 #define MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x0020 0x02ac 0x0000 5 0
18 #define MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0024 0x02b0 0x0000 5 0
19 #define MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0028 0x02b4 0x0000 5 0
20 #define MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x002c 0x02b8 0x0000 5 0
21 #define MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0030 0x02bc 0x0000 5 0
22 #define MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0034 0x02c0 0x0000 5 0
23 #define MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0038 0x02c4 0x0000 5 0
[all …]
H A Dimx6sll-pinfunc.h15 #define MX6SLL_PAD_WDOG_B__WDOG1_B 0x0014 0x02DC 0x0000 0x0 0x0
16 #define MX6SLL_PAD_WDOG_B__WDOG1_RESET_B_DEB 0x0014 0x02DC 0x0000 0x1 0x0
17 #define MX6SLL_PAD_WDOG_B__UART5_RI_B 0x0014 0x02DC 0x0000 0x2 0x0
18 #define MX6SLL_PAD_WDOG_B__GPIO3_IO18 0x0014 0x02DC 0x0000 0x5 0x0
19 #define MX6SLL_PAD_REF_CLK_24M__XTALOSC_REF_CLK_24M 0x0018 0x02E0 0x0000 0x0 0x0
20 #define MX6SLL_PAD_REF_CLK_24M__I2C3_SCL 0x0018 0x02E0 0x068C 0x1 0x0
21 #define MX6SLL_PAD_REF_CLK_24M__PWM3_OUT 0x0018 0x02E0 0x0000 0x2 0x0
22 #define MX6SLL_PAD_REF_CLK_24M__USB_OTG2_ID 0x0018 0x02E0 0x0560 0x3 0x0
23 #define MX6SLL_PAD_REF_CLK_24M__CCM_PMIC_READY 0x0018 0x02E0 0x05AC 0x4 0x0
24 #define MX6SLL_PAD_REF_CLK_24M__GPIO3_IO21 0x0018 0x02E0 0x0000 0x5 0x0
[all …]
H A Dimx7d-pinfunc.h14 #define MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x0000 0x0030 0x0000 0x0 0x0
15 #define MX7D_PAD_LPSR_GPIO1_IO00__PWM4_OUT 0x0000 0x0030 0x0000 0x1 0x0
16 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_ANY 0x0000 0x0030 0x0000 0x2 0x0
17 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x0000 0x0030 0x0000 0x3 0x0
18 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG__RST_B_DEB 0x0000 0x0030 0x0000 0x4 0x0
19 #define MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x0004 0x0034 0x0000 0x0 0x0
20 #define MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x0004 0x0034 0x0000 0x1 0x0
21 #define MX7D_PAD_LPSR_GPIO1_IO01__CCM_ENET_REF_CLK3 0x0004 0x0034 0x0000 0x2 0x0
22 #define MX7D_PAD_LPSR_GPIO1_IO01__SAI1_MCLK 0x0004 0x0034 0x0000 0x3 0x0
23 #define MX7D_PAD_LPSR_GPIO1_IO01__ANATOP_24M_OUT 0x0004 0x0034 0x0000 0x4 0x0
[all …]
H A Dimx6ull-pinfunc.h16 #define MX6UL_PAD_UART5_TX_DATA__UART5_DTE_RX 0x00BC 0x0348 0x0644 0x0 0x6
18 #define MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x00C0 0x034C 0x0644 0x0 0x7
20 #define MX6UL_PAD_ENET1_RX_EN__UART5_DCE_RTS 0x00CC 0x0358 0x0640 0x1 0x5
22 #define MX6UL_PAD_ENET1_TX_DATA0__UART5_DTE_RTS 0x00D0 0x035C 0x0640 0x1 0x6
24 #define MX6UL_PAD_CSI_DATA02__UART5_DCE_RTS 0x01EC 0x0478 0x0640 0x8 0x7
27 #define MX6ULL_PAD_UART1_TX_DATA__UART5_DCE_TX 0x0084 0x0310 0x0000 0x9 0x0
28 #define MX6ULL_PAD_UART1_TX_DATA__UART5_DTE_RX 0x0084 0x0310 0x0644 0x9 0x4
29 #define MX6ULL_PAD_UART1_RX_DATA__UART5_DCE_RX 0x0088 0x0314 0x0644 0x9 0x5
30 #define MX6ULL_PAD_UART1_RX_DATA__UART5_DTE_TX 0x0088 0x0314 0x0000 0x9 0x0
31 #define MX6ULL_PAD_UART1_CTS_B__UART5_DCE_CTS 0x008C 0x0318 0x0000 0x9 0x0
[all …]
H A Dimx6sx-pinfunc.h13 #define MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x0014 0x035C 0x07A8 0x0 0x1
14 #define MX6SX_PAD_GPIO1_IO00__USDHC1_VSELECT 0x0014 0x035C 0x0000 0x1 0x0
15 #define MX6SX_PAD_GPIO1_IO00__SPDIF_LOCK 0x0014 0x035C 0x0000 0x2 0x0
16 #define MX6SX_PAD_GPIO1_IO00__CCM_WAIT 0x0014 0x035C 0x0000 0x3 0x0
17 #define MX6SX_PAD_GPIO1_IO00__WDOG1_WDOG_ANY 0x0014 0x035C 0x0000 0x4 0x0
18 #define MX6SX_PAD_GPIO1_IO00__GPIO1_IO_0 0x0014 0x035C 0x0000 0x5 0x0
19 #define MX6SX_PAD_GPIO1_IO00__SNVS_HP_WRAPPER_VIO_5 0x0014 0x035C 0x0000 0x6 0x0
20 #define MX6SX_PAD_GPIO1_IO00__PHY_DTB_1 0x0014 0x035C 0x0000 0x7 0x0
21 #define MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x0018 0x0360 0x07AC 0x0 0x1
22 #define MX6SX_PAD_GPIO1_IO01__USDHC1_RESET_B 0x0018 0x0360 0x0000 0x1 0x0
[all …]
/linux/Documentation/devicetree/bindings/pinctrl/
H A Damlogic,meson-pinctrl-a1.yaml27 "^bank@[0-9a-f]+$":
58 reg = <0x0400 0x003c>,
59 <0x0480 0x0118>;
63 gpio-ranges = <&periphs_pinctrl 0 0 62>;
/linux/arch/powerpc/include/asm/
H A Dcell-regs.h28 #define HID0_CBE_THERM_WAKEUP 0x0000020000000000ul
29 #define HID0_CBE_SYSERR_WAKEUP 0x0000008000000000ul
30 #define HID0_CBE_THERM_INT_EN 0x0000000400000000ul
31 #define HID0_CBE_SYSERR_INT_EN 0x0000000200000000ul
57 u64 pad_0x0000; /* 0x0000 */
59 u64 group_control; /* 0x0008 */
61 u8 pad_0x0010_0x00a8 [0x00a8 - 0x0010]; /* 0x0010 */
63 u64 debug_bus_control; /* 0x00a8 */
65 u8 pad_0x00b0_0x0100 [0x0100 - 0x00b0]; /* 0x00b0 */
67 u64 trace_aux_data; /* 0x0100 */
[all …]
H A Dprom.h20 #define OF_DT_BEGIN_NODE 0x1 /* Start of node, full name */
21 #define OF_DT_END_NODE 0x2 /* End node */
22 #define OF_DT_PROP 0x3 /* Property: name off, size,
24 #define OF_DT_NOP 0x4 /* nop */
25 #define OF_DT_END 0x9
27 #define OF_DT_VERSION 0x10
41 * ends when size is 0
102 #define OV_IGNORE 0x80 /* ignore this vector */
103 #define OV_CESSATION_POLICY 0x40 /* halt if unsupported option present*/
106 #define OV1_PPC_2_00 0x80 /* set if we support PowerPC 2.00 */
[all …]
/linux/arch/arm/mach-omap2/
H A Dctrl_module_wkup_44xx.h22 #define OMAP4_CTRL_MODULE_WKUP 0x4a30c000
25 #define OMAP4_CTRL_MODULE_WKUP_IP_REVISION 0x0000
26 #define OMAP4_CTRL_MODULE_WKUP_IP_HWINFO 0x0004
27 #define OMAP4_CTRL_MODULE_WKUP_IP_SYSCONFIG 0x0010
28 #define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_0 0x0460
29 #define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_1 0x0464
30 #define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_2 0x0468
31 #define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_3 0x046c
32 #define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_4 0x0470
33 #define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_5 0x0474
[all …]
/linux/Documentation/arch/arm/
H A Dnetwinder.rst15 0x0000 0x000f DMA1
16 0x0020 0x0021 PIC1
17 0x0060 0x006f Keyboard
18 0x0070 0x007f RTC
19 0x0080 0x0087 DMA1
20 0x0088 0x008f DMA2
21 0x00a0 0x00a3 PIC2
22 0x00c0 0x00df DMA2
23 0x0180 0x0187 IRDA
24 0x01f0 0x01f6 ide0
[all …]
/linux/arch/mips/include/asm/octeon/
H A Dcvmx-ciu-defs.h13 (CVMX_ADD_IO_SEG(0x0001070000000000ull + addr##ull) + \
16 #define CVMX_CIU_EN2_PPX_IP4(c) CVMX_CIU_ADDR(0xA400, c, 0x0F, 8)
17 #define CVMX_CIU_EN2_PPX_IP4_W1C(c) CVMX_CIU_ADDR(0xCC00, c, 0x0F, 8)
18 #define CVMX_CIU_EN2_PPX_IP4_W1S(c) CVMX_CIU_ADDR(0xAC00, c, 0x0F, 8)
19 #define CVMX_CIU_FUSE CVMX_CIU_ADDR(0x0728, 0, 0x00, 0)
20 #define CVMX_CIU_INT_SUM1 CVMX_CIU_ADDR(0x0108, 0, 0x00, 0)
21 #define CVMX_CIU_INTX_EN0(c) CVMX_CIU_ADDR(0x0200, c, 0x3F, 16)
22 #define CVMX_CIU_INTX_EN0_W1C(c) CVMX_CIU_ADDR(0x2200, c, 0x3F, 16)
23 #define CVMX_CIU_INTX_EN0_W1S(c) CVMX_CIU_ADDR(0x6200, c, 0x3F, 16)
24 #define CVMX_CIU_INTX_EN1(c) CVMX_CIU_ADDR(0x0208, c, 0x3F, 16)
[all …]
/linux/arch/arm/mach-footbridge/
H A Ddma-isa.c24 #define ISA_DMA_MASK 0
34 { 0x0a, 0x0b, 0x0c, 0x487, 0x087, 0x00, 0x01 },
35 { 0x0a, 0x0b, 0x0c, 0x483, 0x083, 0x02, 0x03 },
36 { 0x0a, 0x0b, 0x0c, 0x481, 0x081, 0x04, 0x05 },
37 { 0x0a, 0x0b, 0x0c, 0x482, 0x082, 0x06, 0x07 },
38 { 0xd4, 0xd6, 0xd8, 0x000, 0x000, 0xc0, 0xc2 },
39 { 0xd4, 0xd6, 0xd8, 0x48b, 0x08b, 0xc4, 0xc6 },
40 { 0xd4, 0xd6, 0xd8, 0x489, 0x089, 0xc8, 0xca },
41 { 0xd4, 0xd6, 0xd8, 0x48a, 0x08a, 0xcc, 0xce }
57 .coherent_dma_mask = ~(dma_addr_t)0,
[all …]
/linux/drivers/media/platform/ti/vpe/
H A Dsc_coeff.h17 HS_UP_SCALE = 0,
31 0x001F, 0x1F90, 0x00D2, 0x06FE, 0x00D2, 0x1F90, 0x001F,
32 0x001C, 0x1F9E, 0x009F, 0x06FB, 0x0108, 0x1F82, 0x0022,
33 0x0019, 0x1FAC, 0x006F, 0x06F3, 0x0140, 0x1F74, 0x0025,
34 0x0016, 0x1FB9, 0x0041, 0x06E7, 0x017B, 0x1F66, 0x0028,
35 0x0013, 0x1FC6, 0x0017, 0x06D6, 0x01B7, 0x1F58, 0x002B,
36 0x0010, 0x1FD3, 0x1FEF, 0x06C0, 0x01F6, 0x1F4B, 0x002D,
37 0x000E, 0x1FDF, 0x1FCB, 0x06A5, 0x0235, 0x1F3F, 0x002F,
38 0x000B, 0x1FEA, 0x1FAA, 0x0686, 0x0277, 0x1F33, 0x0031,
39 0x0009, 0x1FF5, 0x1F8C, 0x0663, 0x02B8, 0x1F28, 0x0033,
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dnv34.c36 NVKM_MEM_TARGET_INST, 0x46dc, 16, true, in nv34_gr_chan_new()
42 nvkm_wo32(chan->inst, 0x0028, 0x00000001 | (chan->chid << 24)); in nv34_gr_chan_new()
43 nvkm_wo32(chan->inst, 0x040c, 0x01000101); in nv34_gr_chan_new()
44 nvkm_wo32(chan->inst, 0x0420, 0x00000111); in nv34_gr_chan_new()
45 nvkm_wo32(chan->inst, 0x0424, 0x00000060); in nv34_gr_chan_new()
46 nvkm_wo32(chan->inst, 0x0440, 0x00000080); in nv34_gr_chan_new()
47 nvkm_wo32(chan->inst, 0x0444, 0xffff0000); in nv34_gr_chan_new()
48 nvkm_wo32(chan->inst, 0x0448, 0x00000001); in nv34_gr_chan_new()
49 nvkm_wo32(chan->inst, 0x045c, 0x44400000); in nv34_gr_chan_new()
50 nvkm_wo32(chan->inst, 0x0480, 0xffff0000); in nv34_gr_chan_new()
[all …]
/linux/drivers/clk/mediatek/
H A Dclk-mt8195-apmixedsys.c17 .set_ofs = 0x8,
18 .clr_ofs = 0x8,
19 .sta_ofs = 0x8,
62 PLL(CLK_APMIXED_NNAPLL, "nnapll", 0x0390, 0x03a0, 0,
63 0, 0, 22, 0x0398, 24, 0, 0, 0, 0x0398, 0, 0x0398, 0, 9),
64 PLL(CLK_APMIXED_RESPLL, "respll", 0x0190, 0x0320, 0,
65 0, 0, 22, 0x0198, 24, 0, 0, 0, 0x0198, 0, 0x0198, 0, 9),
66 PLL(CLK_APMIXED_ETHPLL, "ethpll", 0x0360, 0x0370, 0,
67 0, 0, 22, 0x0368, 24, 0, 0, 0, 0x0368, 0, 0x0368, 0, 9),
68 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0710, 0x0720, 0,
[all …]
/linux/drivers/gpu/drm/nouveau/dispnv04/
H A Darb.c74 found = 0; in nv04_calc_arb()
95 if ((p1 < m1 && m1 > 0) || clwm > 519) { in nv04_calc_arb()
149 mclks += (arb->memory_type == 0 ? 2 : 1) in nv10_calc_arb()
210 if ((pdev->device & 0xffff) == 0x01a0 /*CHIPSET_NFORCE*/ || in nv04_update_arb()
211 (pdev->device & 0xffff) == 0x01f0 /*CHIPSET_NFORCE2*/) { in nv04_update_arb()
215 pci_read_config_dword(pci_get_domain_bus_and_slot(domain, 0, 1), in nv04_update_arb()
216 0x7c, &type); in nv04_update_arb()
223 sim_data.memory_type = nvif_rd32(device, NV04_PFB_CFG0) & 0x1; in nv04_update_arb()
224 sim_data.memory_width = (nvif_rd32(device, NV_PEXTDEV_BOOT_0) & 0x10) ? 128 : 64; in nv04_update_arb()
225 sim_data.mem_latency = cfg1 & 0xf; in nv04_update_arb()
[all …]
/linux/drivers/net/wireless/realtek/rtl818x/rtl8180/
H A Drtl8225.c29 bangdata = (data << 4) | (addr & 0xf); in rtl8225_write()
31 reg80 = rtl818x_ioread16(priv, &priv->map->RFPinsOutput) & 0xfff3; in rtl8225_write()
34 rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, reg82 | 0x7); in rtl8225_write()
37 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, reg84 | 0x7 | 0x400); in rtl8225_write()
48 for (i = 15; i >= 0; i--) { in rtl8225_write()
69 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, reg84 | 0x400); in rtl8225_write()
70 rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, 0x1FFF); in rtl8225_write()
81 reg84 = rtl818x_ioread16(priv, &priv->map->RFPinsSelect) | 0x400; in rtl8225_read()
83 reg80 &= ~0xF; in rtl8225_read()
85 rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, reg82 | 0x000F); in rtl8225_read()
[all …]
/linux/drivers/media/i2c/
H A Dmsp3400-kthreads.c28 { 0x0000, 0, 0, "could not detect sound standard", V4L2_STD_ALL },
29 { 0x0001, 0, 0, "autodetect start", V4L2_STD_ALL },
30 { 0x0002, MSP_CARRIER(4.5), MSP_CARRIER(4.72),
32 { 0x0003, MSP_CARRIER(5.5), MSP_CARRIER(5.7421875),
34 { 0x0004, MSP_CARRIER(6.5), MSP_CARRIER(6.2578125),
36 { 0x0005, MSP_CARRIER(6.5), MSP_CARRIER(6.7421875),
38 { 0x0006, MSP_CARRIER(6.5), MSP_CARRIER(6.5),
40 { 0x0007, MSP_CARRIER(6.5), MSP_CARRIER(5.7421875),
42 { 0x0008, MSP_CARRIER(5.5), MSP_CARRIER(5.85),
44 { 0x0009, MSP_CARRIER(6.5), MSP_CARRIER(5.85),
[all …]
/linux/drivers/phy/cadence/
H A Dphy-cadence-salvo.c19 #define USB3_PHY_OFFSET 0x0
20 #define USB2_PHY_OFFSET 0x38000
22 #define PHY_PMA_CMN_CTRL1 0xC800
23 #define TB_ADDR_CMN_DIAG_HSCLK_SEL 0x01e0
24 #define TB_ADDR_CMN_PLL0_VCOCAL_INIT_TMR 0x0084
25 #define TB_ADDR_CMN_PLL0_VCOCAL_ITER_TMR 0x0085
26 #define TB_ADDR_CMN_PLL0_INTDIV 0x0094
27 #define TB_ADDR_CMN_PLL0_FRACDIV 0x0095
28 #define TB_ADDR_CMN_PLL0_HIGH_THR 0x0096
29 #define TB_ADDR_CMN_PLL0_SS_CTRL1 0x0098
[all …]
/linux/drivers/media/usb/au0828/
H A Dau0828-cards.c20 au0828_set(dev, REG_000, 0x10); in hvr950q_cs5340_audio()
22 au0828_clear(dev, REG_000, 0x10); in hvr950q_cs5340_audio()
39 .tuner_addr = 0x61,
66 .tuner_addr = 0x61,
93 .tuner_addr = 0x61,
99 .tuner_addr = 0x61,
105 .tuner_addr = 0x60,
124 if (command == 0) { in au0828_tuner_callback()
131 return 0; in au0828_tuner_callback()
139 return 0; /* Should never be here */ in au0828_tuner_callback()
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/engine/disp/
H A Dgk104.c37 const u32 hoff = head * 0x400; in gk104_sor_hdmi_infoframe_vsi()
42 nvkm_mask(device, 0x690100 + hoff, 0x00010001, 0x00000000); in gk104_sor_hdmi_infoframe_vsi()
46 nvkm_wr32(device, 0x690108 + hoff, vsi.header); in gk104_sor_hdmi_infoframe_vsi()
47 nvkm_wr32(device, 0x69010c + hoff, vsi.subpack0_low); in gk104_sor_hdmi_infoframe_vsi()
48 nvkm_wr32(device, 0x690110 + hoff, vsi.subpack0_high); in gk104_sor_hdmi_infoframe_vsi()
50 nvkm_mask(device, 0x690100 + hoff, 0x00000001, 0x00000001); in gk104_sor_hdmi_infoframe_vsi()
58 const u32 hoff = head * 0x400; in gk104_sor_hdmi_infoframe_avi()
63 nvkm_mask(device, 0x690000 + hoff, 0x00000001, 0x00000000); in gk104_sor_hdmi_infoframe_avi()
67 nvkm_wr32(device, 0x690008 + hoff, avi.header); in gk104_sor_hdmi_infoframe_avi()
68 nvkm_wr32(device, 0x69000c + hoff, avi.subpack0_low); in gk104_sor_hdmi_infoframe_avi()
[all …]
/linux/drivers/net/wireless/broadcom/b43legacy/
H A Dradio.c30 0x0002, 0x0003, 0x0001, 0x000F,
31 0x0006, 0x0007, 0x0005, 0x000F,
32 0x000A, 0x000B, 0x0009, 0x000F,
33 0x000E, 0x000F, 0x000D, 0x000F,
41 u16 flipped = 0x0000; in flip_4bit()
43 B43legacy_BUG_ON(!((value & ~0x000F) == 0x0000)); in flip_4bit()
45 flipped |= (value & 0x0001) << 3; in flip_4bit()
46 flipped |= (value & 0x0002) << 1; in flip_4bit()
47 flipped |= (value & 0x0004) >> 1; in flip_4bit()
48 flipped |= (value & 0x0008) >> 3; in flip_4bit()
[all …]
/linux/drivers/gpu/drm/panel/
H A Dpanel-raspberrypi-touchscreen.c62 REG_ID = 0x80,
84 #define D0W_DPHYCONTTX 0x0004
85 #define CLW_DPHYCONTRX 0x0020
86 #define D0W_DPHYCONTRX 0x0024
87 #define D1W_DPHYCONTRX 0x0028
88 #define COM_DPHYCONTRX 0x0038
89 #define CLW_CNTRL 0x0040
90 #define D0W_CNTRL 0x0044
91 #define D1W_CNTRL 0x0048
92 #define DFTMODE_CNTRL 0x0054
[all …]
/linux/arch/arm/mach-omap1/
H A Ddma.c31 #define OMAP1_DMA_BASE (0xfffed800)
36 [GCR] = { 0x0400, 0x00, OMAP_DMA_REG_16BIT },
37 [GSCR] = { 0x0404, 0x00, OMAP_DMA_REG_16BIT },
38 [GRST1] = { 0x0408, 0x00, OMAP_DMA_REG_16BIT },
39 [HW_ID] = { 0x0442, 0x00, OMAP_DMA_REG_16BIT },
40 [PCH2_ID] = { 0x0444, 0x00, OMAP_DMA_REG_16BIT },
41 [PCH0_ID] = { 0x0446, 0x00, OMAP_DMA_REG_16BIT },
42 [PCH1_ID] = { 0x0448, 0x00, OMAP_DMA_REG_16BIT },
43 [PCHG_ID] = { 0x044a, 0x00, OMAP_DMA_REG_16BIT },
44 [PCHD_ID] = { 0x044c, 0x00, OMAP_DMA_REG_16BIT },
[all …]

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