| /linux/drivers/gpu/drm/amd/include/asic_reg/nbio/ |
| H A D | nbio_7_4_offset.h | 27 // base address: 0x0
28 …PSWUSCFG0_VENDOR_ID 0x0000
29 …PSWUSCFG0_DEVICE_ID 0x0002
30 …PSWUSCFG0_COMMAND 0x0004
31 …PSWUSCFG0_STATUS 0x0006
32 …PSWUSCFG0_REVISION_ID 0x0008
33 …PSWUSCFG0_PROG_INTERFACE 0x0009
34 …PSWUSCFG0_SUB_CLASS 0x000a
35 …PSWUSCFG0_BASE_CLASS 0x000b
36 …PSWUSCFG0_CACHE_LINE 0x000c
[all …]
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| H A D | nbio_2_3_offset.h | 27 // base address: 0x0
28 …BIF_BX_PF_MM_INDEX 0x0000
29 …ne mmBIF_BX_PF_MM_INDEX_BASE_IDX 0
30 …BIF_BX_PF_MM_DATA 0x0001
31 …ne mmBIF_BX_PF_MM_DATA_BASE_IDX 0
32 …BIF_BX_PF_MM_INDEX_HI 0x0006
33 …ne mmBIF_BX_PF_MM_INDEX_HI_BASE_IDX 0
37 // base address: 0x0
38 …SYSHUB_INDEX_OVLP 0x0008
39 …ne mmSYSHUB_INDEX_OVLP_BASE_IDX 0
[all …]
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| /linux/drivers/clk/samsung/ |
| H A D | clk-exynos5260.h | 15 #define MUX_SEL_AUD 0x0200
16 #define MUX_ENABLE_AUD 0x0300
17 #define MUX_STAT_AUD 0x0400
18 #define MUX_IGNORE_AUD 0x0500
19 #define DIV_AUD0 0x0600
20 #define DIV_AUD1 0x0604
21 #define DIV_STAT_AUD0 0x0700
22 #define DIV_STAT_AUD1 0x0704
23 #define EN_ACLK_AUD 0x0800
24 #define EN_PCLK_AUD 0x0900
[all …]
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| /linux/arch/s390/include/asm/ |
| H A D | lowcore.h | 23 #define LOWCORE_ALT_ADDRESS _AC(0x70000, UL)
32 __u8 pad_0x0000[0x0014-0x0000]; /* 0x0000 */
33 __u32 ipl_parmblock_ptr; /* 0x0014 */
34 __u8 pad_0x0018[0x0080-0x0018]; /* 0x0018 */
35 __u32 ext_params; /* 0x0080 */
38 __u16 ext_cpu_addr; /* 0x0084 */
39 __u16 ext_int_code; /* 0x0086 */
43 __u32 svc_int_code; /* 0x0088 */
46 __u16 pgm_ilc; /* 0x008c */
47 __u16 pgm_code; /* 0x008e */
[all …]
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| /linux/drivers/clk/bcm/ |
| H A D | clk-bcm281xx.c | 16 .gate = HW_SW_GATE(0x214, 16, 0, 1),
17 .trig = TRIGGER(0x0e04, 0),
18 .div = FRAC_DIVIDER(0x0e00, 0, 22, 16),
34 .gate = HW_SW_GATE(0x0414, 16, 0, 1),
38 .sel = SELECTOR(0x0a10, 0, 2),
39 .trig = TRIGGER(0x0a40, 4),
43 .gate = HW_SW_GATE(0x0418, 16, 0, 1),
47 .sel = SELECTOR(0x0a04, 0, 2),
48 .div = DIVIDER(0x0a04, 3, 4),
49 .trig = TRIGGER(0x0a40, 0),
[all …]
|
| H A D | clk-bcm21664.c | 16 .gate = HW_SW_GATE(0x214, 16, 0, 1),
33 .gate = HW_SW_GATE(0x0414, 16, 0, 1),
34 .hyst = HYST(0x0414, 8, 9),
38 .sel = SELECTOR(0x0a10, 0, 2),
39 .trig = TRIGGER(0x0a40, 4),
45 .enable = CCU_LVM_EN(0x0034, 0),
46 .control = CCU_POLICY_CTL(0x000c, 0, 1, 2),
58 .gate = HW_SW_GATE(0x0358, 18, 2, 3),
64 .sel = SELECTOR(0x0a28, 0, 3),
65 .div = DIVIDER(0x0a28, 4, 14),
[all …]
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| /linux/drivers/media/rc/keymaps/ |
| H A D | rc-avermedia-m733a-rm-k6.c | 17 { 0x0401, KEY_POWER2 },
18 { 0x0406, KEY_MUTE },
19 { 0x0408, KEY_MODE }, /* TV/FM */
21 { 0x0409, KEY_NUMERIC_1 },
22 { 0x040a, KEY_NUMERIC_2 },
23 { 0x040b, KEY_NUMERIC_3 },
24 { 0x040c, KEY_NUMERIC_4 },
25 { 0x040d, KEY_NUMERIC_5 },
26 { 0x040e, KEY_NUMERIC_6 },
27 { 0x040f, KEY_NUMERIC_7 },
[all …]
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| H A D | rc-avermedia-m135a.c | 23 { 0x0200, KEY_POWER2 },
24 { 0x022e, KEY_DOT }, /* '.' */
25 { 0x0201, KEY_MODE }, /* TV/FM or SOURCE */
27 { 0x0205, KEY_NUMERIC_1 },
28 { 0x0206, KEY_NUMERIC_2 },
29 { 0x0207, KEY_NUMERIC_3 },
30 { 0x0209, KEY_NUMERIC_4 },
31 { 0x020a, KEY_NUMERIC_5 },
32 { 0x020b, KEY_NUMERIC_6 },
33 { 0x020d, KEY_NUMERIC_7 },
[all …]
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| /linux/arch/arm/boot/dts/nxp/imx/ |
| H A D | imx6ul-pinfunc.h | 13 #define MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x0014 0x02a0 0x0000 5 0
14 #define MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x0018 0x02a4 0x0000 5 0
16 #define MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x001c 0x02a8 0x0000 5 0
17 #define MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x0020 0x02ac 0x0000 5 0
18 #define MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0024 0x02b0 0x0000 5 0
19 #define MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0028 0x02b4 0x0000 5 0
20 #define MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x002c 0x02b8 0x0000 5 0
21 #define MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0030 0x02bc 0x0000 5 0
22 #define MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0034 0x02c0 0x0000 5 0
23 #define MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0038 0x02c4 0x0000 5 0
[all …]
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| H A D | imx6sll-pinfunc.h | 15 #define MX6SLL_PAD_WDOG_B__WDOG1_B 0x0014 0x02DC 0x0000 0x0 0x0
16 #define MX6SLL_PAD_WDOG_B__WDOG1_RESET_B_DEB 0x0014 0x02DC 0x0000 0x1 0x0
17 #define MX6SLL_PAD_WDOG_B__UART5_RI_B 0x0014 0x02DC 0x0000 0x2 0x0
18 #define MX6SLL_PAD_WDOG_B__GPIO3_IO18 0x0014 0x02DC 0x0000 0x5 0x0
19 #define MX6SLL_PAD_REF_CLK_24M__XTALOSC_REF_CLK_24M 0x0018 0x02E0 0x0000 0x0 0x0
20 #define MX6SLL_PAD_REF_CLK_24M__I2C3_SCL 0x0018 0x02E0 0x068C 0x1 0x0
21 #define MX6SLL_PAD_REF_CLK_24M__PWM3_OUT 0x0018 0x02E0 0x0000 0x2 0x0
22 #define MX6SLL_PAD_REF_CLK_24M__USB_OTG2_ID 0x0018 0x02E0 0x0560 0x3 0x0
23 #define MX6SLL_PAD_REF_CLK_24M__CCM_PMIC_READY 0x0018 0x02E0 0x05AC 0x4 0x0
24 #define MX6SLL_PAD_REF_CLK_24M__GPIO3_IO21 0x0018 0x02E0 0x0000 0x5 0x0
[all …]
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| H A D | imx6sx-pinfunc.h | 13 #define MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x0014 0x035C 0x07A8 0x0 0x1
14 #define MX6SX_PAD_GPIO1_IO00__USDHC1_VSELECT 0x0014 0x035C 0x0000 0x1 0x0
15 #define MX6SX_PAD_GPIO1_IO00__SPDIF_LOCK 0x0014 0x035C 0x0000 0x2 0x0
16 #define MX6SX_PAD_GPIO1_IO00__CCM_WAIT 0x0014 0x035C 0x0000 0x3 0x0
17 #define MX6SX_PAD_GPIO1_IO00__WDOG1_WDOG_ANY 0x0014 0x035C 0x0000 0x4 0x0
18 #define MX6SX_PAD_GPIO1_IO00__GPIO1_IO_0 0x0014 0x035C 0x0000 0x5 0x0
19 #define MX6SX_PAD_GPIO1_IO00__SNVS_HP_WRAPPER_VIO_5 0x0014 0x035C 0x0000 0x6 0x0
20 #define MX6SX_PAD_GPIO1_IO00__PHY_DTB_1 0x0014 0x035C 0x0000 0x7 0x0
21 #define MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x0018 0x0360 0x07AC 0x0 0x1
22 #define MX6SX_PAD_GPIO1_IO01__USDHC1_RESET_B 0x0018 0x0360 0x0000 0x1 0x0
[all …]
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| /linux/drivers/gpu/drm/nouveau/nvkm/engine/disp/ |
| H A D | gk104.c | 37 const u32 hoff = head * 0x400; in gk104_sor_hdmi_infoframe_vsi()
42 nvkm_mask(device, 0x690100 + hoff, 0x00010001, 0x00000000); in gk104_sor_hdmi_infoframe_vsi()
46 nvkm_wr32(device, 0x690108 + hoff, vsi.header); in gk104_sor_hdmi_infoframe_vsi()
47 nvkm_wr32(device, 0x69010c + hoff, vsi.subpack0_low); in gk104_sor_hdmi_infoframe_vsi()
48 nvkm_wr32(device, 0x690110 + hoff, vsi.subpack0_high); in gk104_sor_hdmi_infoframe_vsi()
50 nvkm_mask(device, 0x690100 + hoff, 0x00000001, 0x00000001); in gk104_sor_hdmi_infoframe_vsi()
58 const u32 hoff = head * 0x400; in gk104_sor_hdmi_infoframe_avi()
63 nvkm_mask(device, 0x690000 + hoff, 0x00000001, 0x00000000); in gk104_sor_hdmi_infoframe_avi()
67 nvkm_wr32(device, 0x690008 + hoff, avi.header); in gk104_sor_hdmi_infoframe_avi()
68 nvkm_wr32(device, 0x69000c + hoff, avi.subpack0_low); in gk104_sor_hdmi_infoframe_avi()
[all …]
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| /linux/arch/sh/include/mach-common/mach/ |
| H A D | highlander.h | 6 #define PA_NORFLASH_ADDR 0x00000000
7 #define PA_NORFLASH_SIZE 0x04000000
10 #define PA_BCR 0xa4000000 /* FPGA */
13 #define PA_IRLMSK (PA_BCR+0x0000) /* Interrupt Mask control */
14 #define PA_IRLMON (PA_BCR+0x0002) /* Interrupt Status control */
15 #define PA_IRLPRI1 (PA_BCR+0x0004) /* Interrupt Priorty 1 */
16 #define PA_IRLPRI2 (PA_BCR+0x0006) /* Interrupt Priorty 2 */
17 #define PA_IRLPRI3 (PA_BCR+0x0008) /* Interrupt Priorty 3 */
18 #define PA_IRLPRI4 (PA_BCR+0x000a) /* Interrupt Priorty 4 */
19 #define PA_RSTCTL (PA_BCR+0x000c) /* Reset Control */
[all …]
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| /linux/Documentation/arch/arm/ |
| H A D | netwinder.rst | 15 0x0000 0x000f DMA1
16 0x0020 0x0021 PIC1
17 0x0060 0x006f Keyboard
18 0x0070 0x007f RTC
19 0x0080 0x0087 DMA1
20 0x0088 0x008f DMA2
21 0x00a0 0x00a3 PIC2
22 0x00c0 0x00df DMA2
23 0x0180 0x0187 IRDA
24 0x01f0 0x01f6 ide0
[all …]
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| /linux/drivers/gpu/drm/amd/include/asic_reg/nbif/ |
| H A D | nbif_6_3_1_offset.h | 28 // base address: 0x0
29 …IRQ_BRIDGE_CNTL 0x003e
33 // base address: 0x0
34 …BIF_CFG_DEV0_EPF0_VENDOR_ID 0x0000
35 …BIF_CFG_DEV0_EPF0_DEVICE_ID 0x0002
36 …BIF_CFG_DEV0_EPF0_COMMAND 0x0004
37 …BIF_CFG_DEV0_EPF0_STATUS 0x0006
38 …BIF_CFG_DEV0_EPF0_REVISION_ID 0x0008
39 …BIF_CFG_DEV0_EPF0_PROG_INTERFACE 0x0009
40 …BIF_CFG_DEV0_EPF0_SUB_CLASS 0x000a
[all …]
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| /linux/include/linux/bcma/ |
| H A D | bcma_regs.h | 7 #define BCMA_CLKCTLST 0x01E0 /* Clock control and status */
8 #define BCMA_CLKCTLST_FORCEALP 0x00000001 /* Force ALP request */
9 #define BCMA_CLKCTLST_FORCEHT 0x00000002 /* Force HT request */
10 #define BCMA_CLKCTLST_FORCEILP 0x00000004 /* Force ILP request */
11 #define BCMA_CLKCTLST_HAVEALPREQ 0x00000008 /* ALP available request */
12 #define BCMA_CLKCTLST_HAVEHTREQ 0x00000010 /* HT available request */
13 #define BCMA_CLKCTLST_HWCROFF 0x00000020 /* Force HW clock request off */
14 #define BCMA_CLKCTLST_HQCLKREQ 0x00000040 /* HQ Clock */
15 #define BCMA_CLKCTLST_EXTRESREQ 0x00000700 /* Mask of external resource requests */
17 #define BCMA_CLKCTLST_HAVEALP 0x00010000 /* ALP available */
[all …]
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| /linux/drivers/media/platform/samsung/s5p-g2d/ |
| H A D | g2d-regs.h | 10 #define SOFT_RESET_REG 0x0000 /* Software reset reg */
11 #define INTEN_REG 0x0004 /* Interrupt Enable reg */
12 #define INTC_PEND_REG 0x000C /* Interrupt Control Pending reg */
13 #define FIFO_STAT_REG 0x0010 /* Command FIFO Status reg */
14 #define AXI_ID_MODE_REG 0x0014 /* AXI Read ID Mode reg */
15 #define CACHECTL_REG 0x0018 /* Cache & Buffer clear reg */
16 #define AXI_MODE_REG 0x001C /* AXI Mode reg */
19 #define BITBLT_START_REG 0x0100 /* BitBLT Start reg */
20 #define BITBLT_COMMAND_REG 0x0104 /* Command reg for BitBLT */
23 #define ROTATE_REG 0x0200 /* Rotation reg */
[all …]
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| /linux/arch/arm64/boot/dts/freescale/ |
| H A D | imx94-pinfunc.h | 10 #define IMX94_DSE_X1 0x2
11 #define IMX94_DSE_X2 0x6
12 #define IMX94_DSE_X3 0xe
13 #define IMX94_DSE_X4 0x1e
14 #define IMX94_DSE_X5 0x3e
15 #define IMX94_DSE_X6 0x7e
18 #define IMX94_FSEL_FAST 0x180
19 #define IMX94_FSEL_SLOW 0x100
22 #define IMX94_PU_ENABLE 0x200
23 #define IMX94_PU_DISABLE 0x0
[all …]
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| /linux/drivers/gpu/drm/nouveau/nvkm/engine/sw/ |
| H A D | nv50.c | 46 nvkm_wr32(device, 0x001704, chan->base.fifo->inst->addr >> 12); in nv50_sw_chan_vblsem_release()
47 nvkm_wr32(device, 0x001710, 0x80000000 | chan->vblank.ctxdma); in nv50_sw_chan_vblsem_release()
50 if (device->chipset == 0x50) { in nv50_sw_chan_vblsem_release()
51 nvkm_wr32(device, 0x001570, chan->vblank.offset); in nv50_sw_chan_vblsem_release()
52 nvkm_wr32(device, 0x001574, chan->vblank.value); in nv50_sw_chan_vblsem_release()
54 nvkm_wr32(device, 0x060010, chan->vblank.offset); in nv50_sw_chan_vblsem_release()
55 nvkm_wr32(device, 0x060014, chan->vblank.value); in nv50_sw_chan_vblsem_release()
68 case 0x018c: chan->vblank.ctxdma = data; return true; in nv50_sw_chan_mthd()
69 case 0x0400: chan->vblank.offset = data; return true; in nv50_sw_chan_mthd()
70 case 0x0404: chan->vblank.value = data; return true; in nv50_sw_chan_mthd()
[all …]
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| H A D | gf100.c | 47 nvkm_wr32(device, 0x001718, 0x80000000 | inst); in gf100_sw_chan_vblsem_release()
49 nvkm_wr32(device, 0x06000c, upper_32_bits(chan->vblank.offset)); in gf100_sw_chan_vblsem_release()
50 nvkm_wr32(device, 0x060010, lower_32_bits(chan->vblank.offset)); in gf100_sw_chan_vblsem_release()
51 nvkm_wr32(device, 0x060014, chan->vblank.value); in gf100_sw_chan_vblsem_release()
63 case 0x0400: in gf100_sw_chan_mthd()
64 chan->vblank.offset &= 0x00ffffffffULL; in gf100_sw_chan_mthd()
67 case 0x0404: in gf100_sw_chan_mthd()
68 chan->vblank.offset &= 0xff00000000ULL; in gf100_sw_chan_mthd()
71 case 0x0408: in gf100_sw_chan_mthd()
74 case 0x040c: in gf100_sw_chan_mthd()
[all …]
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| /linux/drivers/clk/mediatek/ |
| H A D | clk-mt8188-apmixedsys.c | 16 .set_ofs = 0x8,
17 .clr_ofs = 0x8,
18 .sta_ofs = 0x8,
61 PLL(CLK_APMIXED_ETHPLL, "ethpll", 0x044C, 0x0458, 0,
62 0, 0, 22, 0x0450, 24, 0, 0, 0, 0x0450, 0, 0, 0, 9),
63 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0514, 0x0520, 0,
64 0, 0, 22, 0x0518, 24, 0, 0, 0, 0x0518, 0, 0, 0, 9),
65 PLL(CLK_APMIXED_TVDPLL1, "tvdpll1", 0x0524, 0x0530, 0,
66 0, 0, 22, 0x0528, 24, 0, 0, 0, 0x0528, 0, 0, 0, 9),
67 PLL(CLK_APMIXED_TVDPLL2, "tvdpll2", 0x0534, 0x0540, 0,
[all …]
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| /linux/drivers/media/platform/ti/vpe/ |
| H A D | vpe_regs.h | 16 #define VPE_PID 0x0000
17 #define VPE_PID_MINOR_MASK 0x3f
18 #define VPE_PID_MINOR_SHIFT 0
19 #define VPE_PID_CUSTOM_MASK 0x03
21 #define VPE_PID_MAJOR_MASK 0x07
23 #define VPE_PID_RTL_MASK 0x1f
25 #define VPE_PID_FUNC_MASK 0xfff
27 #define VPE_PID_SCHEME_MASK 0x03
30 #define VPE_SYSCONFIG 0x0010
31 #define VPE_SYSCONFIG_IDLE_MASK 0x03
[all …]
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| /linux/drivers/scsi/megaraid/ |
| H A D | megaraid_mbox.h | 27 #define PCI_DEVICE_ID_PERC4_DI_DISCOVERY 0x000E
28 #define PCI_SUBSYS_ID_PERC4_DI_DISCOVERY 0x0123
30 #define PCI_DEVICE_ID_PERC4_SC 0x1960
31 #define PCI_SUBSYS_ID_PERC4_SC 0x0520
33 #define PCI_DEVICE_ID_PERC4_DC 0x1960
34 #define PCI_SUBSYS_ID_PERC4_DC 0x0518
36 #define PCI_DEVICE_ID_VERDE 0x0407
38 #define PCI_DEVICE_ID_PERC4_DI_EVERGLADES 0x000F
39 #define PCI_SUBSYS_ID_PERC4_DI_EVERGLADES 0x014A
41 #define PCI_DEVICE_ID_PERC4E_SI_BIGBEND 0x0013
[all …]
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| /linux/include/linux/mfd/mt6397/ |
| H A D | registers.h | 11 #define MT6397_CID 0x0100
12 #define MT6397_TOP_CKPDN 0x0102
13 #define MT6397_TOP_CKPDN_SET 0x0104
14 #define MT6397_TOP_CKPDN_CLR 0x0106
15 #define MT6397_TOP_CKPDN2 0x0108
16 #define MT6397_TOP_CKPDN2_SET 0x010A
17 #define MT6397_TOP_CKPDN2_CLR 0x010C
18 #define MT6397_TOP_GPIO_CKPDN 0x010E
19 #define MT6397_TOP_RST_CON 0x0114
20 #define MT6397_WRP_CKPDN 0x011A
[all …]
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| /linux/include/linux/mfd/mt6323/ |
| H A D | registers.h | 10 #define MT6323_CHR_CON0 0x0000
11 #define MT6323_CHR_CON1 0x0002
12 #define MT6323_CHR_CON2 0x0004
13 #define MT6323_CHR_CON3 0x0006
14 #define MT6323_CHR_CON4 0x0008
15 #define MT6323_CHR_CON5 0x000A
16 #define MT6323_CHR_CON6 0x000C
17 #define MT6323_CHR_CON7 0x000E
18 #define MT6323_CHR_CON8 0x0010
19 #define MT6323_CHR_CON9 0x0012
[all …]
|