Searched +full:0 +full:x03500000 (Results 1 – 8 of 8) sorted by relevance
67 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-1][0-9]|12[0-2])$"108 reg = <0x03100000 0x300000>,109 <0x03500000 0x300000>,110 <0x03c00000 0x300000>;113 gpio-ranges = <&tlmm 0 0 124>;
67 - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-8])$"115 reg = <0x03500000 0x300000>,116 <0x03900000 0x300000>,117 <0x03d00000 0x300000>;120 gpio-ranges = <&tlmm 0 0 120>;
61 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-8][0-9])$"108 reg = <0x03100000 0x300000>,109 <0x03500000 0x700000>,110 <0x03d00000 0x300000>;117 gpio-ranges = <&tlmm 0 0 190>;
23 cpu0: cpu@0 {26 reg = <0x0>;27 clocks = <&clockgen QORIQ_CLK_CMUX 0>;36 reg = <0x1>;37 clocks = <&clockgen QORIQ_CLK_CMUX 0>;46 reg = <0x100>;56 reg = <0x101>;66 reg = <0x200>;76 reg = <0x201>;86 reg = <0x300>;[all …]
37 #size-cells = <0>;45 cpu0: cpu@0 {48 reg = <0x0>;49 clocks = <&clockgen QORIQ_CLK_CMUX 0>;58 reg = <0x1>;59 clocks = <&clockgen QORIQ_CLK_CMUX 0>;68 reg = <0x2>;69 clocks = <&clockgen QORIQ_CLK_CMUX 0>;78 reg = <0x3>;79 clocks = <&clockgen QORIQ_CLK_CMUX 0>;[all …]
46 reg = <0xf 0xffe1e000 0 0x2000>;47 ranges = <0x0 0x0 0xf 0xec000000 0x0400000048 0x1 0x0 0xf 0xff800000 0x0001000049 0x2 0x0 0xf 0xffdf0000 0x00010000>;54 ranges = <0x0 0xf 0xffe00000 0x100000>;58 reg = <0xf 0xffe0a000 0 0x1000>;59 ranges = <0x2000000 0x0 0x80000000 0xc 0x00000000 0x0 0x2000000060 0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>;61 pcie@0 {62 ranges = <0x2000000 0x0 0x80000000[all …]
12 #define ARM_R0 029 #define ARM_COND_EQ 0x0 /* == */30 #define ARM_COND_NE 0x1 /* != */31 #define ARM_COND_CS 0x2 /* unsigned >= */33 #define ARM_COND_CC 0x3 /* unsigned < */35 #define ARM_COND_MI 0x4 /* < 0 */36 #define ARM_COND_PL 0x5 /* >= 0 */37 #define ARM_COND_VS 0x6 /* Signed Overflow */38 #define ARM_COND_VC 0x7 /* No Signed Overflow */39 #define ARM_COND_HI 0x8 /* unsigned > */[all …]