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/linux/drivers/media/i2c/
H A Dimx355.c14 #define IMX355_REG_MODE_SELECT 0x0100
15 #define IMX355_MODE_STANDBY 0x00
16 #define IMX355_MODE_STREAMING 0x01
19 #define IMX355_REG_CHIP_ID 0x0016
20 #define IMX355_CHIP_ID 0x0355
23 #define IMX355_REG_FLL 0x0340
24 #define IMX355_FLL_MAX 0xffff
27 #define IMX355_REG_EXPOSURE 0x0202
30 #define IMX355_EXPOSURE_DEFAULT 0x0282
33 #define IMX355_REG_ANALOG_GAIN 0x0204
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6ull-pinfunc.h16 #define MX6UL_PAD_UART5_TX_DATA__UART5_DTE_RX 0x00BC 0x0348 0x0644 0x0 0x6
18 #define MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x00C0 0x034C 0x0644 0x0 0x7
20 #define MX6UL_PAD_ENET1_RX_EN__UART5_DCE_RTS 0x00CC 0x0358 0x0640 0x1 0x5
22 #define MX6UL_PAD_ENET1_TX_DATA0__UART5_DTE_RTS 0x00D0 0x035C 0x0640 0x1 0x6
24 #define MX6UL_PAD_CSI_DATA02__UART5_DCE_RTS 0x01EC 0x0478 0x0640 0x8 0x7
27 #define MX6ULL_PAD_UART1_TX_DATA__UART5_DCE_TX 0x0084 0x0310 0x0000 0x9 0x0
28 #define MX6ULL_PAD_UART1_TX_DATA__UART5_DTE_RX 0x0084 0x0310 0x0644 0x9 0x4
29 #define MX6ULL_PAD_UART1_RX_DATA__UART5_DCE_RX 0x0088 0x0314 0x0644 0x9 0x5
30 #define MX6ULL_PAD_UART1_RX_DATA__UART5_DTE_TX 0x0088 0x0314 0x0000 0x9 0x0
31 #define MX6ULL_PAD_UART1_CTS_B__UART5_DCE_CTS 0x008C 0x0318 0x0000 0x9 0x0
[all …]
H A Dimx6ul-pinfunc.h13 #define MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x0014 0x02a0 0x0000 5 0
14 #define MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x0018 0x02a4 0x0000 5 0
16 #define MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x001c 0x02a8 0x0000 5 0
17 #define MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x0020 0x02ac 0x0000 5 0
18 #define MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0024 0x02b0 0x0000 5 0
19 #define MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0028 0x02b4 0x0000 5 0
20 #define MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x002c 0x02b8 0x0000 5 0
21 #define MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0030 0x02bc 0x0000 5 0
22 #define MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0034 0x02c0 0x0000 5 0
23 #define MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0038 0x02c4 0x0000 5 0
[all …]
H A Dimx7d-pinfunc.h14 #define MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x0000 0x0030 0x0000 0x0 0x0
15 #define MX7D_PAD_LPSR_GPIO1_IO00__PWM4_OUT 0x0000 0x0030 0x0000 0x1 0x0
16 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_ANY 0x0000 0x0030 0x0000 0x2 0x0
17 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x0000 0x0030 0x0000 0x3 0x0
18 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG__RST_B_DEB 0x0000 0x0030 0x0000 0x4 0x0
19 #define MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x0004 0x0034 0x0000 0x0 0x0
20 #define MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x0004 0x0034 0x0000 0x1 0x0
21 #define MX7D_PAD_LPSR_GPIO1_IO01__CCM_ENET_REF_CLK3 0x0004 0x0034 0x0000 0x2 0x0
22 #define MX7D_PAD_LPSR_GPIO1_IO01__SAI1_MCLK 0x0004 0x0034 0x0000 0x3 0x0
23 #define MX7D_PAD_LPSR_GPIO1_IO01__ANATOP_24M_OUT 0x0004 0x0034 0x0000 0x4 0x0
[all …]
/linux/drivers/clk/mediatek/
H A Dclk-mt8365-apmixedsys.c56 { .div = 0, .freq = MT8365_PLL_FMAX },
65 { .div = 0, .freq = MT8365_PLL_FMAX },
74 { .div = 0, .freq = MT8365_PLL_FMAX },
83 PLL_B(CLK_APMIXED_ARMPLL, "armpll", 0x030C, 0x0318, 0x00000001, PLL_AO,
84 22, 0x0310, 24, 0, 0, 0, 0x0310, 0, armpll_div_table, 0, 0),
85 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0228, 0x0234, 0xFF000001,
86 HAVE_RST_BAR, 22, 0x022C, 24, 0, 0, 0, 0x022C, 0, CON0_MT8365_RST_BAR, 0),
87 PLL(CLK_APMIXED_UNIVPLL, "univpll2", 0x0208, 0x0214, 0xFF000001,
88 HAVE_RST_BAR, 22, 0x020C, 24, 0, 0, 0, 0x020C, 0, CON0_MT8365_RST_BAR, 0),
89 PLL_B(CLK_APMIXED_MFGPLL, "mfgpll", 0x0218, 0x0224, 0x00000001, 0, 22,
[all …]
H A Dclk-mt7988-apmixed.c48 PLL(CLK_APMIXED_NETSYSPLL, "netsyspll", 0x0104, 0x0110, 0x00000001, 0, 0, 32, 0x0104, 4, 0,
49 0, 0, 0x0108, 0, 0x0104),
50 PLL(CLK_APMIXED_MPLL, "mpll", 0x0114, 0x0120, 0xff000001, HAVE_RST_BAR, 23, 32, 0x0114, 4,
51 0, 0, 0, 0x0118, 0, 0x0114),
52 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0124, 0x0130, 0xff000001, HAVE_RST_BAR, 23, 32, 0x0124, 4,
53 0, 0, 0, 0x0128, 0, 0x0124),
54 PLL(CLK_APMIXED_APLL2, "apll2", 0x0134, 0x0140, 0x00000001, 0, 0, 32, 0x0134, 4, 0x0704,
55 0x0700, 1, 0x0138, 0, 0x0134),
56 PLL(CLK_APMIXED_NET1PLL, "net1pll", 0x0144, 0x0150, 0xff000001, HAVE_RST_BAR, 23, 32,
57 0x0144, 4, 0, 0, 0, 0x0148, 0, 0x0144),
[all …]
/linux/include/linux/
H A Drio_ids.h12 #define RIO_VID_IDT 0x0038
13 #define RIO_DID_IDT70K200 0x0310
14 #define RIO_DID_IDTCPS8 0x035c
15 #define RIO_DID_IDTCPS12 0x035d
16 #define RIO_DID_IDTCPS16 0x035b
17 #define RIO_DID_IDTCPS6Q 0x035f
18 #define RIO_DID_IDTCPS10Q 0x035e
19 #define RIO_DID_IDTCPS1848 0x0374
20 #define RIO_DID_IDTCPS1432 0x0375
21 #define RIO_DID_IDTCPS1616 0x0379
[all …]
/linux/drivers/media/rc/keymaps/
H A Drc-msi-digivox-ii.c12 { 0x0302, KEY_NUMERIC_2 },
13 { 0x0303, KEY_UP }, /* up */
14 { 0x0304, KEY_NUMERIC_3 },
15 { 0x0305, KEY_CHANNELDOWN },
16 { 0x0308, KEY_NUMERIC_5 },
17 { 0x0309, KEY_NUMERIC_0 },
18 { 0x030b, KEY_NUMERIC_8 },
19 { 0x030d, KEY_DOWN }, /* down */
20 { 0x0310, KEY_NUMERIC_9 },
21 { 0x0311, KEY_NUMERIC_7 },
[all …]
H A Drc-leadtek-y04g0051.c12 { 0x0300, KEY_POWER2 },
13 { 0x0303, KEY_SCREEN },
14 { 0x0304, KEY_RIGHT },
15 { 0x0305, KEY_NUMERIC_1 },
16 { 0x0306, KEY_NUMERIC_2 },
17 { 0x0307, KEY_NUMERIC_3 },
18 { 0x0308, KEY_LEFT },
19 { 0x0309, KEY_NUMERIC_4 },
20 { 0x030a, KEY_NUMERIC_5 },
21 { 0x030b, KEY_NUMERIC_6 },
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx93-pinfunc.h13 #define MX93_PAD_DAP_TDI__JTAG_MUX_TDI 0x0000 0x01B0 0x03D8 0x0 0x0
14 #define MX93_PAD_DAP_TDI__MQS2_LEFT 0x0000 0x01B0 0x0000 0x1 0x0
15 #define MX93_PAD_DAP_TDI__CAN2_TX 0x0000 0x01B0 0x0000 0x3 0x0
16 #define MX93_PAD_DAP_TDI__FLEXIO2_FLEXIO30 0x0000 0x01B0 0x0000 0x4 0x0
17 #define MX93_PAD_DAP_TDI__GPIO3_IO28 0x0000 0x01B0 0x0000 0x5 0x0
18 #define MX93_PAD_DAP_TDI__LPUART5_RX 0x0000 0x01B0 0x0430 0x6 0x0
19 #define MX93_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x0004 0x01B4 0x03DC 0x0 0x0
20 #define MX93_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO31 0x0004 0x01B4 0x0000 0x4 0x0
21 #define MX93_PAD_DAP_TMS_SWDIO__GPIO3_IO29 0x0004 0x01B4 0x0000 0x5 0x0
22 #define MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x0004 0x01B4 0x0000 0x6 0x0
[all …]
/linux/drivers/gpu/drm/radeon/
H A Davivod.h31 #define D1CRTC_CONTROL 0x6080
32 #define CRTC_EN (1 << 0)
33 #define D1CRTC_STATUS 0x609c
34 #define D1CRTC_UPDATE_LOCK 0x60E8
35 #define D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110
36 #define D1GRPH_SECONDARY_SURFACE_ADDRESS 0x6118
38 #define D2CRTC_CONTROL 0x6880
39 #define D2CRTC_STATUS 0x689c
40 #define D2CRTC_UPDATE_LOCK 0x68E8
41 #define D2GRPH_PRIMARY_SURFACE_ADDRESS 0x6910
[all …]
/linux/drivers/gpu/drm/nouveau/include/nvhw/class/
H A Dcl9039.h26 …_SET_OBJECT 0x0000
27 …_SET_OBJECT_CLASS_ID 15:0
30 …_OFFSET_OUT_UPPER 0x0238
31 …_OFFSET_OUT_UPPER_VALUE 7:0
33 …_OFFSET_OUT 0x023c
34 …_OFFSET_OUT_VALUE 31:0
36 …_LAUNCH_DMA 0x0300
37 …_LAUNCH_DMA_SRC_INLINE 0:0
38 …_LAUNCH_DMA_SRC_INLINE_FALSE 0x00000000
39 …_LAUNCH_DMA_SRC_INLINE_TRUE 0x00000001
[all …]
H A Dcl5039.h26 …_SET_OBJECT 0x0000
27 …_SET_OBJECT_POINTER 15:0
29 …_NO_OPERATION 0x0100
30 …_NO_OPERATION_V 31:0
32 …_SET_CONTEXT_DMA_NOTIFY 0x0180
33 …_SET_CONTEXT_DMA_NOTIFY_HANDLE 31:0
35 …_SET_CONTEXT_DMA_BUFFER_IN 0x0184
36 …_SET_CONTEXT_DMA_BUFFER_IN_HANDLE 31:0
38 …_SET_CONTEXT_DMA_BUFFER_OUT 0x0188
39 …_SET_CONTEXT_DMA_BUFFER_OUT_HANDLE 31:0
[all …]
/linux/drivers/gpu/drm/nouveau/
H A Dnouveau_bo74c1.c47 PUSH_NVSQ(push, NV74C1, 0x0304, new_reg->size, in nv84_bo_move_exec()
48 0x0308, upper_32_bits(mem->vma[0].addr), in nv84_bo_move_exec()
49 0x030c, lower_32_bits(mem->vma[0].addr), in nv84_bo_move_exec()
50 0x0310, upper_32_bits(mem->vma[1].addr), in nv84_bo_move_exec()
51 0x0314, lower_32_bits(mem->vma[1].addr), in nv84_bo_move_exec()
52 0x0318, 0x00000000 /* MODE_COPY, QUERY_NONE */); in nv84_bo_move_exec()
53 return 0; in nv84_bo_move_exec()
H A Dnouveau_bo90b5.c38 u64 src_offset = mem->vma[0].addr; in nvc0_bo_move_copy()
51 PUSH_NVSQ(push, NV90B5, 0x030c, upper_32_bits(src_offset), in nvc0_bo_move_copy()
52 0x0310, lower_32_bits(src_offset), in nvc0_bo_move_copy()
53 0x0314, upper_32_bits(dst_offset), in nvc0_bo_move_copy()
54 0x0318, lower_32_bits(dst_offset), in nvc0_bo_move_copy()
55 0x031c, PAGE_SIZE, in nvc0_bo_move_copy()
56 0x0320, PAGE_SIZE, in nvc0_bo_move_copy()
57 0x0324, PAGE_SIZE, in nvc0_bo_move_copy()
58 0x0328, line_count); in nvc0_bo_move_copy()
59 PUSH_NVIM(push, NV90B5, 0x0300, 0x0110); in nvc0_bo_move_copy()
[all …]
H A Dnouveau_bo85b5.c45 u64 src_offset = mem->vma[0].addr; in nva3_bo_move_copy()
58 PUSH_NVSQ(push, NV85B5, 0x030c, upper_32_bits(src_offset), in nva3_bo_move_copy()
59 0x0310, lower_32_bits(src_offset), in nva3_bo_move_copy()
60 0x0314, upper_32_bits(dst_offset), in nva3_bo_move_copy()
61 0x0318, lower_32_bits(dst_offset), in nva3_bo_move_copy()
62 0x031c, PAGE_SIZE, in nva3_bo_move_copy()
63 0x0320, PAGE_SIZE, in nva3_bo_move_copy()
64 0x0324, PAGE_SIZE, in nva3_bo_move_copy()
65 0x0328, line_count); in nva3_bo_move_copy()
66 PUSH_NVSQ(push, NV85B5, 0x0300, 0x00000110); in nva3_bo_move_copy()
[all …]
/linux/arch/powerpc/platforms/44x/
H A Dpci.h18 #define PCIX0_VENDID 0x000
19 #define PCIX0_DEVID 0x002
20 #define PCIX0_COMMAND 0x004
21 #define PCIX0_STATUS 0x006
22 #define PCIX0_REVID 0x008
23 #define PCIX0_CLS 0x009
24 #define PCIX0_CACHELS 0x00c
25 #define PCIX0_LATTIM 0x00d
26 #define PCIX0_HDTYPE 0x00e
27 #define PCIX0_BIST 0x00f
[all …]
/linux/drivers/net/wireless/intel/iwlwifi/pcie/
H A Ddrv.c20 #define TRANS_CFG_MARKER BIT(0)
27 __builtin_choose_expr(_IS_A(cfg, iwl_cfg), 0, _invalid_type)))
38 {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */
39 {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */
40 {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */
41 {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */
42 {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */
43 {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */
44 {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */
45 {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */
[all …]
/linux/drivers/pinctrl/
H A Dpinctrl-rockchip.c53 #define IOMUX_GPIO_ONLY BIT(0)
102 .pull_type[0] = pull0, \
140 .pull_type[0] = pull0, \
165 .pull_type[0] = pull0, \
230 .pull_type[0] = pull0, \
270 for (i = 0; i < info->ngroups; i++) { in pinctrl_name_to_group()
300 for (i = 0; i < info->ctrl->nr_banks; i++, b++) { in bank_num_to_bank()
339 return 0; in rockchip_get_group_pins()
379 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; in rockchip_dt_node_to_map()
380 new_map[0].data.mux.function = parent->name; in rockchip_dt_node_to_map()
[all …]
/linux/drivers/net/ethernet/mellanox/mlxbf_gige/
H A Dmlxbf_gige_regs.h13 #define MLXBF_GIGE_VERSION 0x0000
14 #define MLXBF_GIGE_VERSION_BF2 0x0
15 #define MLXBF_GIGE_VERSION_BF3 0x1
16 #define MLXBF_GIGE_STATUS 0x0010
17 #define MLXBF_GIGE_STATUS_READY BIT(0)
18 #define MLXBF_GIGE_INT_STATUS 0x0028
19 #define MLXBF_GIGE_INT_STATUS_RX_RECEIVE_PACKET BIT(0)
28 #define MLXBF_GIGE_INT_EN 0x0030
29 #define MLXBF_GIGE_INT_EN_RX_RECEIVE_PACKET BIT(0)
38 #define MLXBF_GIGE_INT_MASK 0x0038
[all …]
/linux/drivers/net/ethernet/renesas/
H A Drtsn.h14 #define AXIBMI 0x0000
15 #define TSNMHD 0x1000
16 #define RMSO 0x2000
17 #define RMRO 0x3800
20 AXIWC = AXIBMI + 0x0000,
21 AXIRC = AXIBMI + 0x0004,
22 TDPC0 = AXIBMI + 0x0010,
23 TFT = AXIBMI + 0x0090,
24 TATLS0 = AXIBMI + 0x00a0,
25 TATLS1 = AXIBMI + 0x00a4,
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/smu/
H A Dsmu_6_0_d.h26 #define ixLCAC_MC0_CNTL 0x011C
27 #define ixLCAC_MC0_OVR_SEL 0x011D
28 #define ixLCAC_MC0_OVR_VAL 0x011E
29 #define ixLCAC_MC1_CNTL 0x011F
30 #define ixLCAC_MC1_OVR_SEL 0x0120
31 #define ixLCAC_MC1_OVR_VAL 0x0121
32 #define ixLCAC_MC2_CNTL 0x0122
33 #define ixLCAC_MC2_OVR_SEL 0x0123
34 #define ixLCAC_MC2_OVR_VAL 0x0124
35 #define ixLCAC_MC3_CNTL 0x0125
[all …]
/linux/include/linux/soc/ti/
H A Domap1-soc.h51 #define GET_OMAP_REVISION() ((omap_rev() >> 8) & 0xff)
59 #define GET_OMAP_CLASS (omap_rev() & 0xff)
64 return (GET_OMAP_CLASS == (id)) ? 1 : 0; \
67 #define GET_OMAP_SUBCLASS ((omap_rev() >> 20) & 0x0fff)
72 return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0; \
75 IS_OMAP_CLASS(15xx, 0x15)
76 IS_OMAP_CLASS(16xx, 0x16)
78 #define cpu_is_omap15xx() 0
79 #define cpu_is_omap16xx() 0
112 #define GET_OMAP_TYPE ((omap_rev() >> 16) & 0xffff)
[all …]
/linux/drivers/media/platform/samsung/s5p-g2d/
H A Dg2d-regs.h10 #define SOFT_RESET_REG 0x0000 /* Software reset reg */
11 #define INTEN_REG 0x0004 /* Interrupt Enable reg */
12 #define INTC_PEND_REG 0x000C /* Interrupt Control Pending reg */
13 #define FIFO_STAT_REG 0x0010 /* Command FIFO Status reg */
14 #define AXI_ID_MODE_REG 0x0014 /* AXI Read ID Mode reg */
15 #define CACHECTL_REG 0x0018 /* Cache & Buffer clear reg */
16 #define AXI_MODE_REG 0x001C /* AXI Mode reg */
19 #define BITBLT_START_REG 0x0100 /* BitBLT Start reg */
20 #define BITBLT_COMMAND_REG 0x0104 /* Command reg for BitBLT */
23 #define ROTATE_REG 0x0200 /* Rotation reg */
[all …]
/linux/drivers/gpu/drm/nouveau/dispnv04/
H A Ddisp.h25 uint8_t CRTC[0xa0];
26 uint8_t CR58[0x10];
136 const int impl = to_pci_dev(dev->dev)->device & 0x0ff0; in nv_two_heads()
138 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS && impl != 0x0100 && in nv_two_heads()
139 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200) in nv_two_heads()
148 return nv_two_heads(dev) && (to_pci_dev(dev->dev)->device & 0x0ff0) != 0x0110; in nv_gf4_disp_arch()
155 const int impl = to_pci_dev(dev->dev)->device & 0x0ff0; in nv_two_reg_pll()
157 if (impl == 0x0310 || impl == 0x0340 || drm->client.device.info.family >= NV_DEVICE_INFO_V0_CURIE) in nv_two_reg_pll()

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