Lines Matching +full:0 +full:x0310
53 #define IOMUX_GPIO_ONLY BIT(0)
102 .pull_type[0] = pull0, \
140 .pull_type[0] = pull0, \
165 .pull_type[0] = pull0, \
230 .pull_type[0] = pull0, \
270 for (i = 0; i < info->ngroups; i++) { in pinctrl_name_to_group()
300 for (i = 0; i < info->ctrl->nr_banks; i++, b++) { in bank_num_to_bank()
339 return 0; in rockchip_get_group_pins()
379 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; in rockchip_dt_node_to_map()
380 new_map[0].data.mux.function = parent->name; in rockchip_dt_node_to_map()
381 new_map[0].data.mux.group = np->name; in rockchip_dt_node_to_map()
386 for (i = 0; i < grp->npins; i++) { in rockchip_dt_node_to_map()
397 return 0; in rockchip_dt_node_to_map()
421 .pin = 0,
422 .reg = 0x418,
423 .bit = 0,
424 .mask = 0x3
428 .reg = 0x418,
430 .mask = 0x3
434 .reg = 0x418,
436 .mask = 0x3
440 .reg = 0x418,
442 .mask = 0x3
446 .reg = 0x418,
448 .mask = 0x3
452 .reg = 0x418,
454 .mask = 0x3
458 .reg = 0x418,
460 .mask = 0x3
464 .reg = 0x418,
466 .mask = 0x3
470 .reg = 0x41c,
471 .bit = 0,
472 .mask = 0x3
476 .reg = 0x41c,
478 .mask = 0x3
484 .num = 0,
486 .reg = 0x10000,
487 .bit = 0,
488 .mask = 0xf
491 .num = 0,
493 .reg = 0x10000,
495 .mask = 0xf
498 .num = 0,
500 .reg = 0x10000,
502 .mask = 0xf
505 .num = 0,
507 .reg = 0x10000,
509 .mask = 0xf
517 .reg = 0xe8,
518 .bit = 0,
519 .mask = 0x7
523 .reg = 0xe8,
525 .mask = 0x7
529 .reg = 0xe8,
531 .mask = 0x7
535 .reg = 0xe8,
537 .mask = 0x7
541 .reg = 0xd4,
543 .mask = 0x7
552 .reg = 0x28,
554 .mask = 0xf
559 .reg = 0x2c,
560 .bit = 0,
561 .mask = 0x3
566 .reg = 0x30,
568 .mask = 0xf
573 .reg = 0x30,
575 .mask = 0xf
580 .reg = 0x30,
582 .mask = 0xf
587 .reg = 0x34,
588 .bit = 0,
589 .mask = 0xf
594 .reg = 0x34,
596 .mask = 0xf
601 .reg = 0x34,
603 .mask = 0xf
608 .reg = 0x40,
610 .mask = 0x3
615 .reg = 0x40,
617 .mask = 0x3
622 .reg = 0x50,
623 .bit = 0,
624 .mask = 0x3
629 .reg = 0x68,
631 .mask = 0x3
636 .reg = 0x68,
638 .mask = 0x3
643 .reg = 0x68,
645 .mask = 0xf
650 .reg = 0x68,
652 .mask = 0xf
661 .reg = 0x28,
662 .bit = 0,
663 .mask = 0x7
668 .reg = 0x30,
670 .mask = 0x3
675 .reg = 0x44,
677 .mask = 0x3
682 .reg = 0x44,
684 .mask = 0x3
689 .reg = 0x44,
691 .mask = 0x3
696 .reg = 0x44,
698 .mask = 0x3
703 .reg = 0x44,
705 .mask = 0x3
710 .reg = 0x44,
712 .mask = 0x3
717 .reg = 0x44,
719 .mask = 0x3
731 for (i = 0; i < ctrl->niomux_recalced; i++) { in rockchip_get_recalced_mux()
747 RK_MUXROUTE_SAME(2, RK_PB4, 1, 0x184, BIT(16 + 7)), /* cif-d0m0 */
748 RK_MUXROUTE_SAME(3, RK_PA1, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d0m1 */
749 RK_MUXROUTE_SAME(2, RK_PB6, 1, 0x184, BIT(16 + 7)), /* cif-d1m0 */
750 RK_MUXROUTE_SAME(3, RK_PA2, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d1m1 */
751 RK_MUXROUTE_SAME(2, RK_PA0, 1, 0x184, BIT(16 + 7)), /* cif-d2m0 */
752 RK_MUXROUTE_SAME(3, RK_PA3, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d2m1 */
753 RK_MUXROUTE_SAME(2, RK_PA1, 1, 0x184, BIT(16 + 7)), /* cif-d3m0 */
754 RK_MUXROUTE_SAME(3, RK_PA5, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d3m1 */
755 RK_MUXROUTE_SAME(2, RK_PA2, 1, 0x184, BIT(16 + 7)), /* cif-d4m0 */
756 RK_MUXROUTE_SAME(3, RK_PA7, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d4m1 */
757 RK_MUXROUTE_SAME(2, RK_PA3, 1, 0x184, BIT(16 + 7)), /* cif-d5m0 */
758 RK_MUXROUTE_SAME(3, RK_PB0, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d5m1 */
759 RK_MUXROUTE_SAME(2, RK_PA4, 1, 0x184, BIT(16 + 7)), /* cif-d6m0 */
760 RK_MUXROUTE_SAME(3, RK_PB1, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d6m1 */
761 RK_MUXROUTE_SAME(2, RK_PA5, 1, 0x184, BIT(16 + 7)), /* cif-d7m0 */
762 RK_MUXROUTE_SAME(3, RK_PB4, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d7m1 */
763 RK_MUXROUTE_SAME(2, RK_PA6, 1, 0x184, BIT(16 + 7)), /* cif-d8m0 */
764 RK_MUXROUTE_SAME(3, RK_PB6, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d8m1 */
765 RK_MUXROUTE_SAME(2, RK_PA7, 1, 0x184, BIT(16 + 7)), /* cif-d9m0 */
766 RK_MUXROUTE_SAME(3, RK_PB7, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d9m1 */
767 RK_MUXROUTE_SAME(2, RK_PB7, 1, 0x184, BIT(16 + 7)), /* cif-d10m0 */
768 RK_MUXROUTE_SAME(3, RK_PC6, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d10m1 */
769 RK_MUXROUTE_SAME(2, RK_PC0, 1, 0x184, BIT(16 + 7)), /* cif-d11m0 */
770 RK_MUXROUTE_SAME(3, RK_PC7, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d11m1 */
771 RK_MUXROUTE_SAME(2, RK_PB0, 1, 0x184, BIT(16 + 7)), /* cif-vsyncm0 */
772 RK_MUXROUTE_SAME(3, RK_PD1, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-vsyncm1 */
773 RK_MUXROUTE_SAME(2, RK_PB1, 1, 0x184, BIT(16 + 7)), /* cif-hrefm0 */
774 RK_MUXROUTE_SAME(3, RK_PD2, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-hrefm1 */
775 RK_MUXROUTE_SAME(2, RK_PB2, 1, 0x184, BIT(16 + 7)), /* cif-clkinm0 */
776 RK_MUXROUTE_SAME(3, RK_PD3, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-clkinm1 */
777 RK_MUXROUTE_SAME(2, RK_PB3, 1, 0x184, BIT(16 + 7)), /* cif-clkoutm0 */
778 RK_MUXROUTE_SAME(3, RK_PD0, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-clkoutm1 */
779 RK_MUXROUTE_SAME(3, RK_PC6, 2, 0x184, BIT(16 + 8)), /* pdm-m0 */
780 RK_MUXROUTE_SAME(2, RK_PC6, 1, 0x184, BIT(16 + 8) | BIT(8)), /* pdm-m1 */
781 RK_MUXROUTE_SAME(3, RK_PD3, 2, 0x184, BIT(16 + 8)), /* pdm-sdi0m0 */
782 RK_MUXROUTE_SAME(2, RK_PC5, 2, 0x184, BIT(16 + 8) | BIT(8)), /* pdm-sdi0m1 */
783 RK_MUXROUTE_SAME(1, RK_PD3, 2, 0x184, BIT(16 + 10)), /* uart2-rxm0 */
784 RK_MUXROUTE_SAME(2, RK_PB6, 2, 0x184, BIT(16 + 10) | BIT(10)), /* uart2-rxm1 */
785 RK_MUXROUTE_SAME(1, RK_PD2, 2, 0x184, BIT(16 + 10)), /* uart2-txm0 */
786 RK_MUXROUTE_SAME(2, RK_PB4, 2, 0x184, BIT(16 + 10) | BIT(10)), /* uart2-txm1 */
787 RK_MUXROUTE_SAME(0, RK_PC1, 2, 0x184, BIT(16 + 9)), /* uart3-rxm0 */
788 RK_MUXROUTE_SAME(1, RK_PB7, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-rxm1 */
789 RK_MUXROUTE_SAME(0, RK_PC0, 2, 0x184, BIT(16 + 9)), /* uart3-txm0 */
790 RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-txm1 */
791 RK_MUXROUTE_SAME(0, RK_PC2, 2, 0x184, BIT(16 + 9)), /* uart3-ctsm0 */
792 RK_MUXROUTE_SAME(1, RK_PB4, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-ctsm1 */
793 RK_MUXROUTE_SAME(0, RK_PC3, 2, 0x184, BIT(16 + 9)), /* uart3-rtsm0 */
794 RK_MUXROUTE_SAME(1, RK_PB5, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-rtsm1 */
798 RK_MUXROUTE_GRF(3, RK_PD2, 1, 0x10260, WRITE_MASK_VAL(0, 0, 0)), /* I2S0_MCLK_M0 */
799 RK_MUXROUTE_GRF(3, RK_PB0, 3, 0x10260, WRITE_MASK_VAL(0, 0, 1)), /* I2S0_MCLK_M1 */
801 RK_MUXROUTE_GRF(0, RK_PD4, 4, 0x10260, WRITE_MASK_VAL(3, 2, 0)), /* I2S1_MCLK_M0 */
802 RK_MUXROUTE_GRF(1, RK_PD5, 2, 0x10260, WRITE_MASK_VAL(3, 2, 1)), /* I2S1_MCLK_M1 */
803 RK_MUXROUTE_GRF(2, RK_PC7, 6, 0x10260, WRITE_MASK_VAL(3, 2, 2)), /* I2S1_MCLK_M2 */
805 RK_MUXROUTE_GRF(1, RK_PD0, 1, 0x10260, WRITE_MASK_VAL(4, 4, 0)), /* I2S2_MCLK_M0 */
806 RK_MUXROUTE_GRF(2, RK_PB3, 2, 0x10260, WRITE_MASK_VAL(4, 4, 1)), /* I2S2_MCLK_M1 */
808 RK_MUXROUTE_GRF(3, RK_PD4, 2, 0x10260, WRITE_MASK_VAL(12, 12, 0)), /* PDM_CLK0_M0 */
809 RK_MUXROUTE_GRF(3, RK_PC0, 3, 0x10260, WRITE_MASK_VAL(12, 12, 1)), /* PDM_CLK0_M1 */
811 RK_MUXROUTE_GRF(3, RK_PC6, 1, 0x10264, WRITE_MASK_VAL(0, 0, 0)), /* CIF_CLKOUT_M0 */
812 RK_MUXROUTE_GRF(2, RK_PD1, 3, 0x10264, WRITE_MASK_VAL(0, 0, 1)), /* CIF_CLKOUT_M1 */
814 RK_MUXROUTE_GRF(3, RK_PA4, 5, 0x10264, WRITE_MASK_VAL(5, 4, 0)), /* I2C3_SCL_M0 */
815 RK_MUXROUTE_GRF(2, RK_PD4, 7, 0x10264, WRITE_MASK_VAL(5, 4, 1)), /* I2C3_SCL_M1 */
816 RK_MUXROUTE_GRF(1, RK_PD6, 3, 0x10264, WRITE_MASK_VAL(5, 4, 2)), /* I2C3_SCL_M2 */
818 RK_MUXROUTE_GRF(3, RK_PA0, 7, 0x10264, WRITE_MASK_VAL(6, 6, 0)), /* I2C4_SCL_M0 */
819 RK_MUXROUTE_GRF(4, RK_PA0, 4, 0x10264, WRITE_MASK_VAL(6, 6, 1)), /* I2C4_SCL_M1 */
821 RK_MUXROUTE_GRF(2, RK_PA5, 7, 0x10264, WRITE_MASK_VAL(9, 8, 0)), /* I2C5_SCL_M0 */
822 RK_MUXROUTE_GRF(3, RK_PB0, 5, 0x10264, WRITE_MASK_VAL(9, 8, 1)), /* I2C5_SCL_M1 */
823 RK_MUXROUTE_GRF(1, RK_PD0, 4, 0x10264, WRITE_MASK_VAL(9, 8, 2)), /* I2C5_SCL_M2 */
825 RK_MUXROUTE_GRF(3, RK_PC0, 5, 0x10264, WRITE_MASK_VAL(11, 10, 0)), /* SPI1_CLK_M0 */
826 RK_MUXROUTE_GRF(1, RK_PC6, 3, 0x10264, WRITE_MASK_VAL(11, 10, 1)), /* SPI1_CLK_M1 */
827 RK_MUXROUTE_GRF(2, RK_PD5, 6, 0x10264, WRITE_MASK_VAL(11, 10, 2)), /* SPI1_CLK_M2 */
829 RK_MUXROUTE_GRF(3, RK_PC0, 2, 0x10264, WRITE_MASK_VAL(12, 12, 0)), /* RGMII_CLK_M0 */
830 RK_MUXROUTE_GRF(2, RK_PB7, 2, 0x10264, WRITE_MASK_VAL(12, 12, 1)), /* RGMII_CLK_M1 */
832 RK_MUXROUTE_GRF(3, RK_PA1, 3, 0x10264, WRITE_MASK_VAL(13, 13, 0)), /* CAN_TXD_M0 */
833 RK_MUXROUTE_GRF(3, RK_PA7, 5, 0x10264, WRITE_MASK_VAL(13, 13, 1)), /* CAN_TXD_M1 */
835 RK_MUXROUTE_GRF(3, RK_PA4, 6, 0x10268, WRITE_MASK_VAL(0, 0, 0)), /* PWM8_M0 */
836 RK_MUXROUTE_GRF(2, RK_PD7, 5, 0x10268, WRITE_MASK_VAL(0, 0, 1)), /* PWM8_M1 */
838 RK_MUXROUTE_GRF(3, RK_PA5, 6, 0x10268, WRITE_MASK_VAL(2, 2, 0)), /* PWM9_M0 */
839 RK_MUXROUTE_GRF(2, RK_PD6, 5, 0x10268, WRITE_MASK_VAL(2, 2, 1)), /* PWM9_M1 */
841 RK_MUXROUTE_GRF(3, RK_PA6, 6, 0x10268, WRITE_MASK_VAL(4, 4, 0)), /* PWM10_M0 */
842 RK_MUXROUTE_GRF(2, RK_PD5, 5, 0x10268, WRITE_MASK_VAL(4, 4, 1)), /* PWM10_M1 */
844 RK_MUXROUTE_GRF(3, RK_PA7, 6, 0x10268, WRITE_MASK_VAL(6, 6, 0)), /* PWM11_IR_M0 */
845 RK_MUXROUTE_GRF(3, RK_PA1, 5, 0x10268, WRITE_MASK_VAL(6, 6, 1)), /* PWM11_IR_M1 */
847 RK_MUXROUTE_GRF(1, RK_PA5, 3, 0x10268, WRITE_MASK_VAL(8, 8, 0)), /* UART2_TX_M0 */
848 RK_MUXROUTE_GRF(3, RK_PA2, 1, 0x10268, WRITE_MASK_VAL(8, 8, 1)), /* UART2_TX_M1 */
850 RK_MUXROUTE_GRF(3, RK_PC6, 3, 0x10268, WRITE_MASK_VAL(11, 10, 0)), /* UART3_TX_M0 */
851 RK_MUXROUTE_GRF(1, RK_PA7, 2, 0x10268, WRITE_MASK_VAL(11, 10, 1)), /* UART3_TX_M1 */
852 RK_MUXROUTE_GRF(3, RK_PA0, 4, 0x10268, WRITE_MASK_VAL(11, 10, 2)), /* UART3_TX_M2 */
854 RK_MUXROUTE_GRF(3, RK_PA4, 4, 0x10268, WRITE_MASK_VAL(13, 12, 0)), /* UART4_TX_M0 */
855 RK_MUXROUTE_GRF(2, RK_PA6, 4, 0x10268, WRITE_MASK_VAL(13, 12, 1)), /* UART4_TX_M1 */
856 RK_MUXROUTE_GRF(1, RK_PD5, 3, 0x10268, WRITE_MASK_VAL(13, 12, 2)), /* UART4_TX_M2 */
858 RK_MUXROUTE_GRF(3, RK_PA6, 4, 0x10268, WRITE_MASK_VAL(15, 14, 0)), /* UART5_TX_M0 */
859 RK_MUXROUTE_GRF(2, RK_PB0, 4, 0x10268, WRITE_MASK_VAL(15, 14, 1)), /* UART5_TX_M1 */
860 RK_MUXROUTE_GRF(2, RK_PA0, 3, 0x10268, WRITE_MASK_VAL(15, 14, 2)), /* UART5_TX_M2 */
862 RK_MUXROUTE_PMU(0, RK_PB6, 3, 0x0114, WRITE_MASK_VAL(0, 0, 0)), /* PWM0_M0 */
863 RK_MUXROUTE_PMU(2, RK_PB3, 5, 0x0114, WRITE_MASK_VAL(0, 0, 1)), /* PWM0_M1 */
865 RK_MUXROUTE_PMU(0, RK_PB7, 3, 0x0114, WRITE_MASK_VAL(2, 2, 0)), /* PWM1_M0 */
866 RK_MUXROUTE_PMU(2, RK_PB2, 5, 0x0114, WRITE_MASK_VAL(2, 2, 1)), /* PWM1_M1 */
868 RK_MUXROUTE_PMU(0, RK_PC0, 3, 0x0114, WRITE_MASK_VAL(4, 4, 0)), /* PWM2_M0 */
869 RK_MUXROUTE_PMU(2, RK_PB1, 5, 0x0114, WRITE_MASK_VAL(4, 4, 1)), /* PWM2_M1 */
871 RK_MUXROUTE_PMU(0, RK_PC1, 3, 0x0114, WRITE_MASK_VAL(6, 6, 0)), /* PWM3_IR_M0 */
872 RK_MUXROUTE_PMU(2, RK_PB0, 5, 0x0114, WRITE_MASK_VAL(6, 6, 1)), /* PWM3_IR_M1 */
874 RK_MUXROUTE_PMU(0, RK_PC2, 3, 0x0114, WRITE_MASK_VAL(8, 8, 0)), /* PWM4_M0 */
875 RK_MUXROUTE_PMU(2, RK_PA7, 5, 0x0114, WRITE_MASK_VAL(8, 8, 1)), /* PWM4_M1 */
877 RK_MUXROUTE_PMU(0, RK_PC3, 3, 0x0114, WRITE_MASK_VAL(10, 10, 0)), /* PWM5_M0 */
878 RK_MUXROUTE_PMU(2, RK_PA6, 5, 0x0114, WRITE_MASK_VAL(10, 10, 1)), /* PWM5_M1 */
880 RK_MUXROUTE_PMU(0, RK_PB2, 3, 0x0114, WRITE_MASK_VAL(12, 12, 0)), /* PWM6_M0 */
881 RK_MUXROUTE_PMU(2, RK_PD4, 5, 0x0114, WRITE_MASK_VAL(12, 12, 1)), /* PWM6_M1 */
883 RK_MUXROUTE_PMU(0, RK_PB1, 3, 0x0114, WRITE_MASK_VAL(14, 14, 0)), /* PWM7_IR_M0 */
884 RK_MUXROUTE_PMU(3, RK_PA0, 5, 0x0114, WRITE_MASK_VAL(14, 14, 1)), /* PWM7_IR_M1 */
886 RK_MUXROUTE_PMU(0, RK_PB0, 1, 0x0118, WRITE_MASK_VAL(1, 0, 0)), /* SPI0_CLK_M0 */
887 RK_MUXROUTE_PMU(2, RK_PA1, 1, 0x0118, WRITE_MASK_VAL(1, 0, 1)), /* SPI0_CLK_M1 */
888 RK_MUXROUTE_PMU(2, RK_PB2, 6, 0x0118, WRITE_MASK_VAL(1, 0, 2)), /* SPI0_CLK_M2 */
890 RK_MUXROUTE_PMU(0, RK_PB6, 2, 0x0118, WRITE_MASK_VAL(2, 2, 0)), /* UART1_TX_M0 */
891 RK_MUXROUTE_PMU(1, RK_PD0, 5, 0x0118, WRITE_MASK_VAL(2, 2, 1)), /* UART1_TX_M1 */
895 RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x144, BIT(16 + 3) | BIT(16 + 4)), /* spi-0 */
896 RK_MUXROUTE_SAME(1, RK_PD3, 3, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(3)), /* spi-1 */
897 RK_MUXROUTE_SAME(0, RK_PB5, 2, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(4)), /* spi-2 */
898 RK_MUXROUTE_SAME(1, RK_PA5, 1, 0x144, BIT(16 + 5)), /* i2s-0 */
899 RK_MUXROUTE_SAME(0, RK_PB6, 1, 0x144, BIT(16 + 5) | BIT(5)), /* i2s-1 */
900 RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x144, BIT(16 + 6)), /* emmc-0 */
901 RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x144, BIT(16 + 6) | BIT(6)), /* emmc-1 */
905 RK_MUXROUTE_SAME(0, RK_PD0, 1, 0xa0, BIT(16 + 11)), /* non-iomuxed emmc/flash pins on flash-dqs */
906 …RK_MUXROUTE_SAME(0, RK_PD0, 2, 0xa0, BIT(16 + 11) | BIT(11)), /* non-iomuxed emmc/flash pins on em…
910 RK_MUXROUTE_SAME(0, RK_PD2, 1, 0x50, BIT(16)), /* pwm0-0 */
911 RK_MUXROUTE_SAME(3, RK_PC5, 1, 0x50, BIT(16) | BIT(0)), /* pwm0-1 */
912 RK_MUXROUTE_SAME(0, RK_PD3, 1, 0x50, BIT(16 + 1)), /* pwm1-0 */
913 RK_MUXROUTE_SAME(0, RK_PD6, 2, 0x50, BIT(16 + 1) | BIT(1)), /* pwm1-1 */
914 RK_MUXROUTE_SAME(0, RK_PD4, 1, 0x50, BIT(16 + 2)), /* pwm2-0 */
915 RK_MUXROUTE_SAME(1, RK_PB4, 2, 0x50, BIT(16 + 2) | BIT(2)), /* pwm2-1 */
916 RK_MUXROUTE_SAME(3, RK_PD2, 1, 0x50, BIT(16 + 3)), /* pwm3-0 */
917 RK_MUXROUTE_SAME(1, RK_PB3, 2, 0x50, BIT(16 + 3) | BIT(3)), /* pwm3-1 */
918 RK_MUXROUTE_SAME(1, RK_PA1, 1, 0x50, BIT(16 + 4)), /* sdio-0_d0 */
919 RK_MUXROUTE_SAME(3, RK_PA2, 1, 0x50, BIT(16 + 4) | BIT(4)), /* sdio-1_d0 */
920 RK_MUXROUTE_SAME(0, RK_PB5, 2, 0x50, BIT(16 + 5)), /* spi-0_rx */
921 RK_MUXROUTE_SAME(2, RK_PA0, 2, 0x50, BIT(16 + 5) | BIT(5)), /* spi-1_rx */
922 RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x50, BIT(16 + 7)), /* emmc-0_cmd */
923 RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x50, BIT(16 + 7) | BIT(7)), /* emmc-1_cmd */
924 RK_MUXROUTE_SAME(1, RK_PC3, 2, 0x50, BIT(16 + 8)), /* uart2-0_rx */
925 RK_MUXROUTE_SAME(1, RK_PB2, 2, 0x50, BIT(16 + 8) | BIT(8)), /* uart2-1_rx */
926 RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x50, BIT(16 + 11)), /* uart1-0_rx */
927 RK_MUXROUTE_SAME(3, RK_PB5, 1, 0x50, BIT(16 + 11) | BIT(11)), /* uart1-1_rx */
931 RK_MUXROUTE_SAME(7, RK_PC0, 2, 0x264, BIT(16 + 12) | BIT(12)), /* edphdmi_cecinoutt1 */
932 RK_MUXROUTE_SAME(7, RK_PC7, 4, 0x264, BIT(16 + 12)), /* edphdmi_cecinout */
936 RK_MUXROUTE_SAME(0, RK_PC3, 1, 0x314, BIT(16 + 0) | BIT(0)), /* rtc_clk */
937 RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x314, BIT(16 + 2) | BIT(16 + 3)), /* uart2_rxm0 */
938 RK_MUXROUTE_SAME(4, RK_PD2, 2, 0x314, BIT(16 + 2) | BIT(16 + 3) | BIT(2)), /* uart2_rxm1 */
939 RK_MUXROUTE_SAME(0, RK_PB7, 2, 0x314, BIT(16 + 4)), /* i2c3_sdam0 */
940 RK_MUXROUTE_SAME(3, RK_PB4, 2, 0x314, BIT(16 + 4) | BIT(4)), /* i2c3_sdam1 */
941 RK_MUXROUTE_SAME(1, RK_PA3, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclktxm0 */
942 RK_MUXROUTE_SAME(1, RK_PA4, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclkrxm0 */
943 RK_MUXROUTE_SAME(1, RK_PB5, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclktxm1 */
944 RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclkrxm1 */
945 RK_MUXROUTE_SAME(1, RK_PA4, 3, 0x308, BIT(16 + 12) | BIT(16 + 13)), /* pdm-clkm0 */
946 RK_MUXROUTE_SAME(1, RK_PB6, 4, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(12)), /* pdm-clkm1 */
947 RK_MUXROUTE_SAME(2, RK_PA6, 2, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(13)), /* pdm-clkm2 */
948 RK_MUXROUTE_SAME(2, RK_PA4, 3, 0x600, BIT(16 + 2) | BIT(2)), /* pdm-clkm-m2 */
952 RK_MUXROUTE_SAME(1, RK_PA1, 2, 0x50, BIT(16) | BIT(16 + 1)), /* uart2dbg_rxm0 */
953 RK_MUXROUTE_SAME(2, RK_PA1, 1, 0x50, BIT(16) | BIT(16 + 1) | BIT(0)), /* uart2dbg_rxm1 */
954 RK_MUXROUTE_SAME(1, RK_PB3, 2, 0x50, BIT(16 + 2) | BIT(2)), /* gmac-m1_rxd0 */
955 RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x50, BIT(16 + 10) | BIT(10)), /* gmac-m1-optimized_rxd3 */
956 RK_MUXROUTE_SAME(2, RK_PC3, 2, 0x50, BIT(16 + 3)), /* pdm_sdi0m0 */
957 RK_MUXROUTE_SAME(1, RK_PC7, 3, 0x50, BIT(16 + 3) | BIT(3)), /* pdm_sdi0m1 */
958 RK_MUXROUTE_SAME(3, RK_PA2, 4, 0x50, BIT(16 + 4) | BIT(16 + 5) | BIT(5)), /* spi_rxdm2 */
959 RK_MUXROUTE_SAME(1, RK_PD0, 1, 0x50, BIT(16 + 6)), /* i2s2_sdim0 */
960 RK_MUXROUTE_SAME(3, RK_PA2, 6, 0x50, BIT(16 + 6) | BIT(6)), /* i2s2_sdim1 */
961 RK_MUXROUTE_SAME(2, RK_PC6, 3, 0x50, BIT(16 + 7) | BIT(7)), /* card_iom1 */
962 RK_MUXROUTE_SAME(2, RK_PC0, 3, 0x50, BIT(16 + 8) | BIT(8)), /* tsp_d5m1 */
963 RK_MUXROUTE_SAME(2, RK_PC0, 4, 0x50, BIT(16 + 9) | BIT(9)), /* cif_data5m1 */
967 RK_MUXROUTE_SAME(4, RK_PB0, 2, 0xe21c, BIT(16 + 10) | BIT(16 + 11)), /* uart2dbga_rx */
968 RK_MUXROUTE_SAME(4, RK_PC0, 2, 0xe21c, BIT(16 + 10) | BIT(16 + 11) | BIT(10)), /* uart2dbgb_rx */
969 RK_MUXROUTE_SAME(4, RK_PC3, 1, 0xe21c, BIT(16 + 10) | BIT(16 + 11) | BIT(11)), /* uart2dbgc_rx */
970 RK_MUXROUTE_SAME(2, RK_PD2, 2, 0xe21c, BIT(16 + 14)), /* pcie_clkreqn */
971 RK_MUXROUTE_SAME(4, RK_PD0, 1, 0xe21c, BIT(16 + 14) | BIT(14)), /* pcie_clkreqnb */
975 RK_MUXROUTE_PMU(0, RK_PB7, 1, 0x0110, WRITE_MASK_VAL(1, 0, 0)), /* PWM0 IO mux M0 */
976 RK_MUXROUTE_PMU(0, RK_PC7, 2, 0x0110, WRITE_MASK_VAL(1, 0, 1)), /* PWM0 IO mux M1 */
977 RK_MUXROUTE_PMU(0, RK_PC0, 1, 0x0110, WRITE_MASK_VAL(3, 2, 0)), /* PWM1 IO mux M0 */
978 RK_MUXROUTE_PMU(0, RK_PB5, 4, 0x0110, WRITE_MASK_VAL(3, 2, 1)), /* PWM1 IO mux M1 */
979 RK_MUXROUTE_PMU(0, RK_PC1, 1, 0x0110, WRITE_MASK_VAL(5, 4, 0)), /* PWM2 IO mux M0 */
980 RK_MUXROUTE_PMU(0, RK_PB6, 4, 0x0110, WRITE_MASK_VAL(5, 4, 1)), /* PWM2 IO mux M1 */
981 RK_MUXROUTE_GRF(0, RK_PB3, 2, 0x0300, WRITE_MASK_VAL(0, 0, 0)), /* CAN0 IO mux M0 */
982 RK_MUXROUTE_GRF(2, RK_PA1, 4, 0x0300, WRITE_MASK_VAL(0, 0, 1)), /* CAN0 IO mux M1 */
983 RK_MUXROUTE_GRF(1, RK_PA1, 3, 0x0300, WRITE_MASK_VAL(2, 2, 0)), /* CAN1 IO mux M0 */
984 RK_MUXROUTE_GRF(4, RK_PC3, 3, 0x0300, WRITE_MASK_VAL(2, 2, 1)), /* CAN1 IO mux M1 */
985 RK_MUXROUTE_GRF(4, RK_PB5, 3, 0x0300, WRITE_MASK_VAL(4, 4, 0)), /* CAN2 IO mux M0 */
986 RK_MUXROUTE_GRF(2, RK_PB2, 4, 0x0300, WRITE_MASK_VAL(4, 4, 1)), /* CAN2 IO mux M1 */
987 RK_MUXROUTE_GRF(4, RK_PC4, 1, 0x0300, WRITE_MASK_VAL(6, 6, 0)), /* HPDIN IO mux M0 */
988 RK_MUXROUTE_GRF(0, RK_PC2, 2, 0x0300, WRITE_MASK_VAL(6, 6, 1)), /* HPDIN IO mux M1 */
989 RK_MUXROUTE_GRF(3, RK_PB1, 3, 0x0300, WRITE_MASK_VAL(8, 8, 0)), /* GMAC1 IO mux M0 */
990 RK_MUXROUTE_GRF(4, RK_PA7, 3, 0x0300, WRITE_MASK_VAL(8, 8, 1)), /* GMAC1 IO mux M1 */
991 RK_MUXROUTE_GRF(4, RK_PD1, 1, 0x0300, WRITE_MASK_VAL(10, 10, 0)), /* HDMITX IO mux M0 */
992 RK_MUXROUTE_GRF(0, RK_PC7, 1, 0x0300, WRITE_MASK_VAL(10, 10, 1)), /* HDMITX IO mux M1 */
993 RK_MUXROUTE_GRF(0, RK_PB6, 1, 0x0300, WRITE_MASK_VAL(14, 14, 0)), /* I2C2 IO mux M0 */
994 RK_MUXROUTE_GRF(4, RK_PB4, 1, 0x0300, WRITE_MASK_VAL(14, 14, 1)), /* I2C2 IO mux M1 */
995 RK_MUXROUTE_GRF(1, RK_PA0, 1, 0x0304, WRITE_MASK_VAL(0, 0, 0)), /* I2C3 IO mux M0 */
996 RK_MUXROUTE_GRF(3, RK_PB6, 4, 0x0304, WRITE_MASK_VAL(0, 0, 1)), /* I2C3 IO mux M1 */
997 RK_MUXROUTE_GRF(4, RK_PB2, 1, 0x0304, WRITE_MASK_VAL(2, 2, 0)), /* I2C4 IO mux M0 */
998 RK_MUXROUTE_GRF(2, RK_PB1, 2, 0x0304, WRITE_MASK_VAL(2, 2, 1)), /* I2C4 IO mux M1 */
999 RK_MUXROUTE_GRF(3, RK_PB4, 4, 0x0304, WRITE_MASK_VAL(4, 4, 0)), /* I2C5 IO mux M0 */
1000 RK_MUXROUTE_GRF(4, RK_PD0, 2, 0x0304, WRITE_MASK_VAL(4, 4, 1)), /* I2C5 IO mux M1 */
1001 RK_MUXROUTE_GRF(3, RK_PB1, 5, 0x0304, WRITE_MASK_VAL(14, 14, 0)), /* PWM8 IO mux M0 */
1002 RK_MUXROUTE_GRF(1, RK_PD5, 4, 0x0304, WRITE_MASK_VAL(14, 14, 1)), /* PWM8 IO mux M1 */
1003 RK_MUXROUTE_GRF(3, RK_PB2, 5, 0x0308, WRITE_MASK_VAL(0, 0, 0)), /* PWM9 IO mux M0 */
1004 RK_MUXROUTE_GRF(1, RK_PD6, 4, 0x0308, WRITE_MASK_VAL(0, 0, 1)), /* PWM9 IO mux M1 */
1005 RK_MUXROUTE_GRF(3, RK_PB5, 5, 0x0308, WRITE_MASK_VAL(2, 2, 0)), /* PWM10 IO mux M0 */
1006 RK_MUXROUTE_GRF(2, RK_PA1, 2, 0x0308, WRITE_MASK_VAL(2, 2, 1)), /* PWM10 IO mux M1 */
1007 RK_MUXROUTE_GRF(3, RK_PB6, 5, 0x0308, WRITE_MASK_VAL(4, 4, 0)), /* PWM11 IO mux M0 */
1008 RK_MUXROUTE_GRF(4, RK_PC0, 3, 0x0308, WRITE_MASK_VAL(4, 4, 1)), /* PWM11 IO mux M1 */
1009 RK_MUXROUTE_GRF(3, RK_PB7, 2, 0x0308, WRITE_MASK_VAL(6, 6, 0)), /* PWM12 IO mux M0 */
1010 RK_MUXROUTE_GRF(4, RK_PC5, 1, 0x0308, WRITE_MASK_VAL(6, 6, 1)), /* PWM12 IO mux M1 */
1011 RK_MUXROUTE_GRF(3, RK_PC0, 2, 0x0308, WRITE_MASK_VAL(8, 8, 0)), /* PWM13 IO mux M0 */
1012 RK_MUXROUTE_GRF(4, RK_PC6, 1, 0x0308, WRITE_MASK_VAL(8, 8, 1)), /* PWM13 IO mux M1 */
1013 RK_MUXROUTE_GRF(3, RK_PC4, 1, 0x0308, WRITE_MASK_VAL(10, 10, 0)), /* PWM14 IO mux M0 */
1014 RK_MUXROUTE_GRF(4, RK_PC2, 1, 0x0308, WRITE_MASK_VAL(10, 10, 1)), /* PWM14 IO mux M1 */
1015 RK_MUXROUTE_GRF(3, RK_PC5, 1, 0x0308, WRITE_MASK_VAL(12, 12, 0)), /* PWM15 IO mux M0 */
1016 RK_MUXROUTE_GRF(4, RK_PC3, 1, 0x0308, WRITE_MASK_VAL(12, 12, 1)), /* PWM15 IO mux M1 */
1017 RK_MUXROUTE_GRF(3, RK_PD2, 3, 0x0308, WRITE_MASK_VAL(14, 14, 0)), /* SDMMC2 IO mux M0 */
1018 RK_MUXROUTE_GRF(3, RK_PA5, 5, 0x0308, WRITE_MASK_VAL(14, 14, 1)), /* SDMMC2 IO mux M1 */
1019 RK_MUXROUTE_GRF(0, RK_PB5, 2, 0x030c, WRITE_MASK_VAL(0, 0, 0)), /* SPI0 IO mux M0 */
1020 RK_MUXROUTE_GRF(2, RK_PD3, 3, 0x030c, WRITE_MASK_VAL(0, 0, 1)), /* SPI0 IO mux M1 */
1021 RK_MUXROUTE_GRF(2, RK_PB5, 3, 0x030c, WRITE_MASK_VAL(2, 2, 0)), /* SPI1 IO mux M0 */
1022 RK_MUXROUTE_GRF(3, RK_PC3, 3, 0x030c, WRITE_MASK_VAL(2, 2, 1)), /* SPI1 IO mux M1 */
1023 RK_MUXROUTE_GRF(2, RK_PC1, 4, 0x030c, WRITE_MASK_VAL(4, 4, 0)), /* SPI2 IO mux M0 */
1024 RK_MUXROUTE_GRF(3, RK_PA0, 3, 0x030c, WRITE_MASK_VAL(4, 4, 1)), /* SPI2 IO mux M1 */
1025 RK_MUXROUTE_GRF(4, RK_PB3, 4, 0x030c, WRITE_MASK_VAL(6, 6, 0)), /* SPI3 IO mux M0 */
1026 RK_MUXROUTE_GRF(4, RK_PC2, 2, 0x030c, WRITE_MASK_VAL(6, 6, 1)), /* SPI3 IO mux M1 */
1027 RK_MUXROUTE_GRF(2, RK_PB4, 2, 0x030c, WRITE_MASK_VAL(8, 8, 0)), /* UART1 IO mux M0 */
1028 RK_MUXROUTE_GRF(3, RK_PD6, 4, 0x030c, WRITE_MASK_VAL(8, 8, 1)), /* UART1 IO mux M1 */
1029 RK_MUXROUTE_GRF(0, RK_PD1, 1, 0x030c, WRITE_MASK_VAL(10, 10, 0)), /* UART2 IO mux M0 */
1030 RK_MUXROUTE_GRF(1, RK_PD5, 2, 0x030c, WRITE_MASK_VAL(10, 10, 1)), /* UART2 IO mux M1 */
1031 RK_MUXROUTE_GRF(1, RK_PA1, 2, 0x030c, WRITE_MASK_VAL(12, 12, 0)), /* UART3 IO mux M0 */
1032 RK_MUXROUTE_GRF(3, RK_PB7, 4, 0x030c, WRITE_MASK_VAL(12, 12, 1)), /* UART3 IO mux M1 */
1033 RK_MUXROUTE_GRF(1, RK_PA6, 2, 0x030c, WRITE_MASK_VAL(14, 14, 0)), /* UART4 IO mux M0 */
1034 RK_MUXROUTE_GRF(3, RK_PB2, 4, 0x030c, WRITE_MASK_VAL(14, 14, 1)), /* UART4 IO mux M1 */
1035 RK_MUXROUTE_GRF(2, RK_PA2, 3, 0x0310, WRITE_MASK_VAL(0, 0, 0)), /* UART5 IO mux M0 */
1036 RK_MUXROUTE_GRF(3, RK_PC2, 4, 0x0310, WRITE_MASK_VAL(0, 0, 1)), /* UART5 IO mux M1 */
1037 RK_MUXROUTE_GRF(2, RK_PA4, 3, 0x0310, WRITE_MASK_VAL(2, 2, 0)), /* UART6 IO mux M0 */
1038 RK_MUXROUTE_GRF(1, RK_PD5, 3, 0x0310, WRITE_MASK_VAL(2, 2, 1)), /* UART6 IO mux M1 */
1039 RK_MUXROUTE_GRF(2, RK_PA6, 3, 0x0310, WRITE_MASK_VAL(5, 4, 0)), /* UART7 IO mux M0 */
1040 RK_MUXROUTE_GRF(3, RK_PC4, 4, 0x0310, WRITE_MASK_VAL(5, 4, 1)), /* UART7 IO mux M1 */
1041 RK_MUXROUTE_GRF(4, RK_PA2, 4, 0x0310, WRITE_MASK_VAL(5, 4, 2)), /* UART7 IO mux M2 */
1042 RK_MUXROUTE_GRF(2, RK_PC5, 3, 0x0310, WRITE_MASK_VAL(6, 6, 0)), /* UART8 IO mux M0 */
1043 RK_MUXROUTE_GRF(2, RK_PD7, 4, 0x0310, WRITE_MASK_VAL(6, 6, 1)), /* UART8 IO mux M1 */
1044 RK_MUXROUTE_GRF(2, RK_PB0, 3, 0x0310, WRITE_MASK_VAL(9, 8, 0)), /* UART9 IO mux M0 */
1045 RK_MUXROUTE_GRF(4, RK_PC5, 4, 0x0310, WRITE_MASK_VAL(9, 8, 1)), /* UART9 IO mux M1 */
1046 RK_MUXROUTE_GRF(4, RK_PA4, 4, 0x0310, WRITE_MASK_VAL(9, 8, 2)), /* UART9 IO mux M2 */
1047 RK_MUXROUTE_GRF(1, RK_PA2, 1, 0x0310, WRITE_MASK_VAL(11, 10, 0)), /* I2S1 IO mux M0 */
1048 RK_MUXROUTE_GRF(3, RK_PC6, 4, 0x0310, WRITE_MASK_VAL(11, 10, 1)), /* I2S1 IO mux M1 */
1049 RK_MUXROUTE_GRF(2, RK_PD0, 5, 0x0310, WRITE_MASK_VAL(11, 10, 2)), /* I2S1 IO mux M2 */
1050 RK_MUXROUTE_GRF(2, RK_PC1, 1, 0x0310, WRITE_MASK_VAL(12, 12, 0)), /* I2S2 IO mux M0 */
1051 RK_MUXROUTE_GRF(4, RK_PB6, 5, 0x0310, WRITE_MASK_VAL(12, 12, 1)), /* I2S2 IO mux M1 */
1052 RK_MUXROUTE_GRF(3, RK_PA2, 4, 0x0310, WRITE_MASK_VAL(14, 14, 0)), /* I2S3 IO mux M0 */
1053 RK_MUXROUTE_GRF(4, RK_PC2, 5, 0x0310, WRITE_MASK_VAL(14, 14, 1)), /* I2S3 IO mux M1 */
1054 RK_MUXROUTE_GRF(1, RK_PA4, 3, 0x0314, WRITE_MASK_VAL(1, 0, 0)), /* PDM IO mux M0 */
1055 RK_MUXROUTE_GRF(1, RK_PA6, 3, 0x0314, WRITE_MASK_VAL(1, 0, 0)), /* PDM IO mux M0 */
1056 RK_MUXROUTE_GRF(3, RK_PD6, 5, 0x0314, WRITE_MASK_VAL(1, 0, 1)), /* PDM IO mux M1 */
1057 RK_MUXROUTE_GRF(4, RK_PA0, 4, 0x0314, WRITE_MASK_VAL(1, 0, 1)), /* PDM IO mux M1 */
1058 RK_MUXROUTE_GRF(3, RK_PC4, 5, 0x0314, WRITE_MASK_VAL(1, 0, 2)), /* PDM IO mux M2 */
1059 RK_MUXROUTE_GRF(0, RK_PA5, 3, 0x0314, WRITE_MASK_VAL(3, 2, 0)), /* PCIE20 IO mux M0 */
1060 RK_MUXROUTE_GRF(2, RK_PD0, 4, 0x0314, WRITE_MASK_VAL(3, 2, 1)), /* PCIE20 IO mux M1 */
1061 RK_MUXROUTE_GRF(1, RK_PB0, 4, 0x0314, WRITE_MASK_VAL(3, 2, 2)), /* PCIE20 IO mux M2 */
1062 RK_MUXROUTE_GRF(0, RK_PA4, 3, 0x0314, WRITE_MASK_VAL(5, 4, 0)), /* PCIE30X1 IO mux M0 */
1063 RK_MUXROUTE_GRF(2, RK_PD2, 4, 0x0314, WRITE_MASK_VAL(5, 4, 1)), /* PCIE30X1 IO mux M1 */
1064 RK_MUXROUTE_GRF(1, RK_PA5, 4, 0x0314, WRITE_MASK_VAL(5, 4, 2)), /* PCIE30X1 IO mux M2 */
1065 RK_MUXROUTE_GRF(0, RK_PA6, 2, 0x0314, WRITE_MASK_VAL(7, 6, 0)), /* PCIE30X2 IO mux M0 */
1066 RK_MUXROUTE_GRF(2, RK_PD4, 4, 0x0314, WRITE_MASK_VAL(7, 6, 1)), /* PCIE30X2 IO mux M1 */
1067 RK_MUXROUTE_GRF(4, RK_PC2, 4, 0x0314, WRITE_MASK_VAL(7, 6, 2)), /* PCIE30X2 IO mux M2 */
1078 for (i = 0; i < ctrl->niomux_routes; i++) { in rockchip_get_mux_route()
1128 reg += 0x4; in rockchip_get_mux()
1130 mask = 0xf; in rockchip_get_mux()
1133 reg += 0x4; in rockchip_get_mux()
1135 mask = 0x7; in rockchip_get_mux()
1138 mask = 0x3; in rockchip_get_mux()
1145 if ((bank->bank_num == 0) && (pin >= RK_PB4) && (pin <= RK_PB7)) in rockchip_get_mux()
1146 reg += 0x1ff4; /* GPIO0_IOC_GPIO0B_IOMUX_SEL_H */ in rockchip_get_mux()
1150 if (bank->bank_num == 0) { in rockchip_get_mux()
1152 u32 reg0 = 0; in rockchip_get_mux()
1154 reg0 = reg + 0x4000 - 0xC; /* PMU2_IOC_BASE */ in rockchip_get_mux()
1162 reg = reg + 0x8000; /* BUS_IOC_BASE */ in rockchip_get_mux()
1165 } else if (bank->bank_num > 0) { in rockchip_get_mux()
1166 reg += 0x8000; /* BUS_IOC_BASE */ in rockchip_get_mux()
1199 return 0; in rockchip_verify_mux()
1227 if (ret < 0) in rockchip_set_mux()
1231 return 0; in rockchip_set_mux()
1247 reg += 0x4; in rockchip_set_mux()
1249 mask = 0xf; in rockchip_set_mux()
1252 reg += 0x4; in rockchip_set_mux()
1254 mask = 0x7; in rockchip_set_mux()
1257 mask = 0x3; in rockchip_set_mux()
1264 if ((bank->bank_num == 0) && (pin >= RK_PB4) && (pin <= RK_PB7)) in rockchip_set_mux()
1265 reg += 0x1ff4; /* GPIO0_IOC_GPIO0B_IOMUX_SEL_H */ in rockchip_set_mux()
1269 if (bank->bank_num == 0) { in rockchip_set_mux()
1272 reg += 0x4000 - 0xC; /* PMU2_IOC_BASE */ in rockchip_set_mux()
1278 u32 reg0 = 0; in rockchip_set_mux()
1280 reg0 = reg + 0x4000 - 0xC; /* PMU2_IOC_BASE */ in rockchip_set_mux()
1286 reg0 = reg + 0x8000; /* BUS_IOC_BASE */ in rockchip_set_mux()
1300 } else if (bank->bank_num > 0) { in rockchip_set_mux()
1301 reg += 0x8000; /* BUS_IOC_BASE */ in rockchip_set_mux()
1337 #define PX30_PULL_PMU_OFFSET 0x10
1338 #define PX30_PULL_GRF_OFFSET 0x60
1350 if (bank->bank_num == 0) { in px30_calc_pull_reg_and_bit()
1358 *reg -= 0x10; in px30_calc_pull_reg_and_bit()
1366 return 0; in px30_calc_pull_reg_and_bit()
1369 #define PX30_DRV_PMU_OFFSET 0x20
1370 #define PX30_DRV_GRF_OFFSET 0xf0
1382 if (bank->bank_num == 0) { in px30_calc_drv_reg_and_bit()
1390 *reg -= 0x10; in px30_calc_drv_reg_and_bit()
1398 return 0; in px30_calc_drv_reg_and_bit()
1401 #define PX30_SCHMITT_PMU_OFFSET 0x38
1402 #define PX30_SCHMITT_GRF_OFFSET 0xc0
1415 if (bank->bank_num == 0) { in px30_calc_schmitt_reg_and_bit()
1429 return 0; in px30_calc_schmitt_reg_and_bit()
1432 #define RV1108_PULL_PMU_OFFSET 0x10
1433 #define RV1108_PULL_OFFSET 0x110
1445 if (bank->bank_num == 0) { in rv1108_calc_pull_reg_and_bit()
1452 *reg -= 0x10; in rv1108_calc_pull_reg_and_bit()
1460 return 0; in rv1108_calc_pull_reg_and_bit()
1463 #define RV1108_DRV_PMU_OFFSET 0x20
1464 #define RV1108_DRV_GRF_OFFSET 0x210
1476 if (bank->bank_num == 0) { in rv1108_calc_drv_reg_and_bit()
1484 *reg -= 0x10; in rv1108_calc_drv_reg_and_bit()
1492 return 0; in rv1108_calc_drv_reg_and_bit()
1495 #define RV1108_SCHMITT_PMU_OFFSET 0x30
1496 #define RV1108_SCHMITT_GRF_OFFSET 0x388
1509 if (bank->bank_num == 0) { in rv1108_calc_schmitt_reg_and_bit()
1522 return 0; in rv1108_calc_schmitt_reg_and_bit()
1525 #define RV1126_PULL_PMU_OFFSET 0x40
1526 #define RV1126_PULL_GRF_GPIO1A0_OFFSET 0x10108
1539 if (bank->bank_num == 0) { in rv1126_calc_pull_reg_and_bit()
1546 return 0; in rv1126_calc_pull_reg_and_bit()
1560 return 0; in rv1126_calc_pull_reg_and_bit()
1563 #define RV1126_DRV_PMU_OFFSET 0x20
1564 #define RV1126_DRV_GRF_GPIO1A0_OFFSET 0x10090
1576 if (bank->bank_num == 0) { in rv1126_calc_drv_reg_and_bit()
1581 *reg -= 0x4; in rv1126_calc_drv_reg_and_bit()
1584 return 0; in rv1126_calc_drv_reg_and_bit()
1598 return 0; in rv1126_calc_drv_reg_and_bit()
1601 #define RV1126_SCHMITT_PMU_OFFSET 0x60
1602 #define RV1126_SCHMITT_GRF_GPIO1A0_OFFSET 0x10188
1615 if (bank->bank_num == 0) { in rv1126_calc_schmitt_reg_and_bit()
1621 return 0; in rv1126_calc_schmitt_reg_and_bit()
1635 return 0; in rv1126_calc_schmitt_reg_and_bit()
1640 #define RK3308_SCHMITT_GRF_OFFSET 0x1a0
1655 return 0; in rk3308_calc_schmitt_reg_and_bit()
1658 #define RK2928_PULL_OFFSET 0x118
1675 return 0; in rk2928_calc_pull_reg_and_bit()
1678 #define RK3128_PULL_OFFSET 0x118
1693 return 0; in rk3128_calc_pull_reg_and_bit()
1696 #define RK3188_PULL_OFFSET 0x164
1700 #define RK3188_PULL_PMU_OFFSET 0x64
1709 if (bank->bank_num == 0 && pin_num < 12) { in rk3188_calc_pull_reg_and_bit()
1712 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0; in rk3188_calc_pull_reg_and_bit()
1719 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET; in rk3188_calc_pull_reg_and_bit()
1729 * pin in bits 1:0 in rk3188_calc_pull_reg_and_bit()
1735 return 0; in rk3188_calc_pull_reg_and_bit()
1738 #define RK3288_PULL_OFFSET 0x140
1746 if (bank->bank_num == 0) { in rk3288_calc_pull_reg_and_bit()
1758 *reg -= 0x10; in rk3288_calc_pull_reg_and_bit()
1766 return 0; in rk3288_calc_pull_reg_and_bit()
1769 #define RK3288_DRV_PMU_OFFSET 0x70
1770 #define RK3288_DRV_GRF_OFFSET 0x1c0
1782 if (bank->bank_num == 0) { in rk3288_calc_drv_reg_and_bit()
1794 *reg -= 0x10; in rk3288_calc_drv_reg_and_bit()
1802 return 0; in rk3288_calc_drv_reg_and_bit()
1805 #define RK3228_PULL_OFFSET 0x100
1821 return 0; in rk3228_calc_pull_reg_and_bit()
1824 #define RK3228_DRV_GRF_OFFSET 0x200
1840 return 0; in rk3228_calc_drv_reg_and_bit()
1843 #define RK3308_PULL_OFFSET 0xa0
1859 return 0; in rk3308_calc_pull_reg_and_bit()
1862 #define RK3308_DRV_GRF_OFFSET 0x100
1878 return 0; in rk3308_calc_drv_reg_and_bit()
1881 #define RK3368_PULL_GRF_OFFSET 0x100
1882 #define RK3368_PULL_PMU_OFFSET 0x10
1891 if (bank->bank_num == 0) { in rk3368_calc_pull_reg_and_bit()
1903 *reg -= 0x10; in rk3368_calc_pull_reg_and_bit()
1911 return 0; in rk3368_calc_pull_reg_and_bit()
1914 #define RK3368_DRV_PMU_OFFSET 0x20
1915 #define RK3368_DRV_GRF_OFFSET 0x200
1924 if (bank->bank_num == 0) { in rk3368_calc_drv_reg_and_bit()
1936 *reg -= 0x10; in rk3368_calc_drv_reg_and_bit()
1944 return 0; in rk3368_calc_drv_reg_and_bit()
1947 #define RK3399_PULL_GRF_OFFSET 0xe040
1948 #define RK3399_PULL_PMU_OFFSET 0x40
1958 if ((bank->bank_num == 0) || (bank->bank_num == 1)) { in rk3399_calc_pull_reg_and_bit()
1972 *reg -= 0x20; in rk3399_calc_pull_reg_and_bit()
1980 return 0; in rk3399_calc_pull_reg_and_bit()
1991 if ((bank->bank_num == 0) || (bank->bank_num == 1)) in rk3399_calc_drv_reg_and_bit()
2003 return 0; in rk3399_calc_drv_reg_and_bit()
2006 #define RK3568_PULL_PMU_OFFSET 0x20
2007 #define RK3568_PULL_GRF_OFFSET 0x80
2010 #define RK3568_PULL_BANK_STRIDE 0x10
2018 if (bank->bank_num == 0) { in rk3568_calc_pull_reg_and_bit()
2036 return 0; in rk3568_calc_pull_reg_and_bit()
2039 #define RK3568_DRV_PMU_OFFSET 0x70
2040 #define RK3568_DRV_GRF_OFFSET 0x200
2043 #define RK3568_DRV_BANK_STRIDE 0x40
2052 if (bank->bank_num == 0) { in rk3568_calc_drv_reg_and_bit()
2069 return 0; in rk3568_calc_drv_reg_and_bit()
2074 #define RK3576_DRV_GPIO0_AL_OFFSET 0x10
2075 #define RK3576_DRV_GPIO0_BH_OFFSET 0x2014
2076 #define RK3576_DRV_GPIO1_OFFSET 0x6020
2077 #define RK3576_DRV_GPIO2_OFFSET 0x6040
2078 #define RK3576_DRV_GPIO3_OFFSET 0x6060
2079 #define RK3576_DRV_GPIO4_AL_OFFSET 0x6080
2080 #define RK3576_DRV_GPIO4_CL_OFFSET 0xA090
2081 #define RK3576_DRV_GPIO4_DL_OFFSET 0xB098
2091 if (bank->bank_num == 0 && pin_num < 12) in rk3576_calc_drv_reg_and_bit()
2093 else if (bank->bank_num == 0) in rk3576_calc_drv_reg_and_bit()
2094 *reg = RK3576_DRV_GPIO0_BH_OFFSET - 0xc; in rk3576_calc_drv_reg_and_bit()
2104 *reg = RK3576_DRV_GPIO4_CL_OFFSET - 0x10; in rk3576_calc_drv_reg_and_bit()
2106 *reg = RK3576_DRV_GPIO4_DL_OFFSET - 0x18; in rk3576_calc_drv_reg_and_bit()
2114 return 0; in rk3576_calc_drv_reg_and_bit()
2119 #define RK3576_PULL_GPIO0_AL_OFFSET 0x20
2120 #define RK3576_PULL_GPIO0_BH_OFFSET 0x2028
2121 #define RK3576_PULL_GPIO1_OFFSET 0x6110
2122 #define RK3576_PULL_GPIO2_OFFSET 0x6120
2123 #define RK3576_PULL_GPIO3_OFFSET 0x6130
2124 #define RK3576_PULL_GPIO4_AL_OFFSET 0x6140
2125 #define RK3576_PULL_GPIO4_CL_OFFSET 0xA148
2126 #define RK3576_PULL_GPIO4_DL_OFFSET 0xB14C
2136 if (bank->bank_num == 0 && pin_num < 12) in rk3576_calc_pull_reg_and_bit()
2138 else if (bank->bank_num == 0) in rk3576_calc_pull_reg_and_bit()
2139 *reg = RK3576_PULL_GPIO0_BH_OFFSET - 0x4; in rk3576_calc_pull_reg_and_bit()
2149 *reg = RK3576_PULL_GPIO4_CL_OFFSET - 0x8; in rk3576_calc_pull_reg_and_bit()
2151 *reg = RK3576_PULL_GPIO4_DL_OFFSET - 0xc; in rk3576_calc_pull_reg_and_bit()
2159 return 0; in rk3576_calc_pull_reg_and_bit()
2164 #define RK3576_SMT_GPIO0_AL_OFFSET 0x30
2165 #define RK3576_SMT_GPIO0_BH_OFFSET 0x2040
2166 #define RK3576_SMT_GPIO1_OFFSET 0x6210
2167 #define RK3576_SMT_GPIO2_OFFSET 0x6220
2168 #define RK3576_SMT_GPIO3_OFFSET 0x6230
2169 #define RK3576_SMT_GPIO4_AL_OFFSET 0x6240
2170 #define RK3576_SMT_GPIO4_CL_OFFSET 0xA248
2171 #define RK3576_SMT_GPIO4_DL_OFFSET 0xB24C
2182 if (bank->bank_num == 0 && pin_num < 12) in rk3576_calc_schmitt_reg_and_bit()
2184 else if (bank->bank_num == 0) in rk3576_calc_schmitt_reg_and_bit()
2185 *reg = RK3576_SMT_GPIO0_BH_OFFSET - 0x4; in rk3576_calc_schmitt_reg_and_bit()
2195 *reg = RK3576_SMT_GPIO4_CL_OFFSET - 0x8; in rk3576_calc_schmitt_reg_and_bit()
2197 *reg = RK3576_SMT_GPIO4_DL_OFFSET - 0xc; in rk3576_calc_schmitt_reg_and_bit()
2205 return 0; in rk3576_calc_schmitt_reg_and_bit()
2208 #define RK3588_PMU1_IOC_REG (0x0000)
2209 #define RK3588_PMU2_IOC_REG (0x4000)
2210 #define RK3588_BUS_IOC_REG (0x8000)
2211 #define RK3588_VCCIO1_4_IOC_REG (0x9000)
2212 #define RK3588_VCCIO3_5_IOC_REG (0xA000)
2213 #define RK3588_VCCIO2_IOC_REG (0xB000)
2214 #define RK3588_VCCIO6_IOC_REG (0xC000)
2215 #define RK3588_EMMC_IOC_REG (0xD000)
2218 {RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0010},
2219 {RK_GPIO0_A4, RK3588_PMU1_IOC_REG + 0x0014},
2220 {RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0018},
2221 {RK_GPIO0_B4, RK3588_PMU2_IOC_REG + 0x0014},
2222 {RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x0018},
2223 {RK_GPIO0_C4, RK3588_PMU2_IOC_REG + 0x001C},
2224 {RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0020},
2225 {RK_GPIO0_D4, RK3588_PMU2_IOC_REG + 0x0024},
2226 {RK_GPIO1_A0, RK3588_VCCIO1_4_IOC_REG + 0x0020},
2227 {RK_GPIO1_A4, RK3588_VCCIO1_4_IOC_REG + 0x0024},
2228 {RK_GPIO1_B0, RK3588_VCCIO1_4_IOC_REG + 0x0028},
2229 {RK_GPIO1_B4, RK3588_VCCIO1_4_IOC_REG + 0x002C},
2230 {RK_GPIO1_C0, RK3588_VCCIO1_4_IOC_REG + 0x0030},
2231 {RK_GPIO1_C4, RK3588_VCCIO1_4_IOC_REG + 0x0034},
2232 {RK_GPIO1_D0, RK3588_VCCIO1_4_IOC_REG + 0x0038},
2233 {RK_GPIO1_D4, RK3588_VCCIO1_4_IOC_REG + 0x003C},
2234 {RK_GPIO2_A0, RK3588_EMMC_IOC_REG + 0x0040},
2235 {RK_GPIO2_A4, RK3588_VCCIO3_5_IOC_REG + 0x0044},
2236 {RK_GPIO2_B0, RK3588_VCCIO3_5_IOC_REG + 0x0048},
2237 {RK_GPIO2_B4, RK3588_VCCIO3_5_IOC_REG + 0x004C},
2238 {RK_GPIO2_C0, RK3588_VCCIO3_5_IOC_REG + 0x0050},
2239 {RK_GPIO2_C4, RK3588_VCCIO3_5_IOC_REG + 0x0054},
2240 {RK_GPIO2_D0, RK3588_EMMC_IOC_REG + 0x0058},
2241 {RK_GPIO2_D4, RK3588_EMMC_IOC_REG + 0x005C},
2242 {RK_GPIO3_A0, RK3588_VCCIO3_5_IOC_REG + 0x0060},
2243 {RK_GPIO3_A4, RK3588_VCCIO3_5_IOC_REG + 0x0064},
2244 {RK_GPIO3_B0, RK3588_VCCIO3_5_IOC_REG + 0x0068},
2245 {RK_GPIO3_B4, RK3588_VCCIO3_5_IOC_REG + 0x006C},
2246 {RK_GPIO3_C0, RK3588_VCCIO3_5_IOC_REG + 0x0070},
2247 {RK_GPIO3_C4, RK3588_VCCIO3_5_IOC_REG + 0x0074},
2248 {RK_GPIO3_D0, RK3588_VCCIO3_5_IOC_REG + 0x0078},
2249 {RK_GPIO3_D4, RK3588_VCCIO3_5_IOC_REG + 0x007C},
2250 {RK_GPIO4_A0, RK3588_VCCIO6_IOC_REG + 0x0080},
2251 {RK_GPIO4_A4, RK3588_VCCIO6_IOC_REG + 0x0084},
2252 {RK_GPIO4_B0, RK3588_VCCIO6_IOC_REG + 0x0088},
2253 {RK_GPIO4_B4, RK3588_VCCIO6_IOC_REG + 0x008C},
2254 {RK_GPIO4_C0, RK3588_VCCIO6_IOC_REG + 0x0090},
2255 {RK_GPIO4_C2, RK3588_VCCIO3_5_IOC_REG + 0x0090},
2256 {RK_GPIO4_C4, RK3588_VCCIO3_5_IOC_REG + 0x0094},
2257 {RK_GPIO4_D0, RK3588_VCCIO2_IOC_REG + 0x0098},
2258 {RK_GPIO4_D4, RK3588_VCCIO2_IOC_REG + 0x009C},
2262 {RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0020},
2263 {RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0024},
2264 {RK_GPIO0_B5, RK3588_PMU2_IOC_REG + 0x0028},
2265 {RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x002C},
2266 {RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0030},
2267 {RK_GPIO1_A0, RK3588_VCCIO1_4_IOC_REG + 0x0110},
2268 {RK_GPIO1_B0, RK3588_VCCIO1_4_IOC_REG + 0x0114},
2269 {RK_GPIO1_C0, RK3588_VCCIO1_4_IOC_REG + 0x0118},
2270 {RK_GPIO1_D0, RK3588_VCCIO1_4_IOC_REG + 0x011C},
2271 {RK_GPIO2_A0, RK3588_EMMC_IOC_REG + 0x0120},
2272 {RK_GPIO2_A6, RK3588_VCCIO3_5_IOC_REG + 0x0120},
2273 {RK_GPIO2_B0, RK3588_VCCIO3_5_IOC_REG + 0x0124},
2274 {RK_GPIO2_C0, RK3588_VCCIO3_5_IOC_REG + 0x0128},
2275 {RK_GPIO2_D0, RK3588_EMMC_IOC_REG + 0x012C},
2276 {RK_GPIO3_A0, RK3588_VCCIO3_5_IOC_REG + 0x0130},
2277 {RK_GPIO3_B0, RK3588_VCCIO3_5_IOC_REG + 0x0134},
2278 {RK_GPIO3_C0, RK3588_VCCIO3_5_IOC_REG + 0x0138},
2279 {RK_GPIO3_D0, RK3588_VCCIO3_5_IOC_REG + 0x013C},
2280 {RK_GPIO4_A0, RK3588_VCCIO6_IOC_REG + 0x0140},
2281 {RK_GPIO4_B0, RK3588_VCCIO6_IOC_REG + 0x0144},
2282 {RK_GPIO4_C0, RK3588_VCCIO6_IOC_REG + 0x0148},
2283 {RK_GPIO4_C2, RK3588_VCCIO3_5_IOC_REG + 0x0148},
2284 {RK_GPIO4_D0, RK3588_VCCIO2_IOC_REG + 0x014C},
2288 {RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0030},
2289 {RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0034},
2290 {RK_GPIO0_B5, RK3588_PMU2_IOC_REG + 0x0040},
2291 {RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x0044},
2292 {RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0048},
2293 {RK_GPIO1_A0, RK3588_VCCIO1_4_IOC_REG + 0x0210},
2294 {RK_GPIO1_B0, RK3588_VCCIO1_4_IOC_REG + 0x0214},
2295 {RK_GPIO1_C0, RK3588_VCCIO1_4_IOC_REG + 0x0218},
2296 {RK_GPIO1_D0, RK3588_VCCIO1_4_IOC_REG + 0x021C},
2297 {RK_GPIO2_A0, RK3588_EMMC_IOC_REG + 0x0220},
2298 {RK_GPIO2_A6, RK3588_VCCIO3_5_IOC_REG + 0x0220},
2299 {RK_GPIO2_B0, RK3588_VCCIO3_5_IOC_REG + 0x0224},
2300 {RK_GPIO2_C0, RK3588_VCCIO3_5_IOC_REG + 0x0228},
2301 {RK_GPIO2_D0, RK3588_EMMC_IOC_REG + 0x022C},
2302 {RK_GPIO3_A0, RK3588_VCCIO3_5_IOC_REG + 0x0230},
2303 {RK_GPIO3_B0, RK3588_VCCIO3_5_IOC_REG + 0x0234},
2304 {RK_GPIO3_C0, RK3588_VCCIO3_5_IOC_REG + 0x0238},
2305 {RK_GPIO3_D0, RK3588_VCCIO3_5_IOC_REG + 0x023C},
2306 {RK_GPIO4_A0, RK3588_VCCIO6_IOC_REG + 0x0240},
2307 {RK_GPIO4_B0, RK3588_VCCIO6_IOC_REG + 0x0244},
2308 {RK_GPIO4_C0, RK3588_VCCIO6_IOC_REG + 0x0248},
2309 {RK_GPIO4_C2, RK3588_VCCIO3_5_IOC_REG + 0x0248},
2310 {RK_GPIO4_D0, RK3588_VCCIO2_IOC_REG + 0x024C},
2325 for (i = ARRAY_SIZE(rk3588_p_regs) - 1; i >= 0; i--) { in rk3588_calc_pull_reg_and_bit()
2326 if (pin >= rk3588_p_regs[i][0]) { in rk3588_calc_pull_reg_and_bit()
2331 return 0; in rk3588_calc_pull_reg_and_bit()
2350 for (i = ARRAY_SIZE(rk3588_ds_regs) - 1; i >= 0; i--) { in rk3588_calc_drv_reg_and_bit()
2351 if (pin >= rk3588_ds_regs[i][0]) { in rk3588_calc_drv_reg_and_bit()
2356 return 0; in rk3588_calc_drv_reg_and_bit()
2376 for (i = ARRAY_SIZE(rk3588_smt_regs) - 1; i >= 0; i--) { in rk3588_calc_schmitt_reg_and_bit()
2377 if (pin >= rk3588_smt_regs[i][0]) { in rk3588_calc_schmitt_reg_and_bit()
2382 return 0; in rk3588_calc_schmitt_reg_and_bit()
2418 case 0 ... 12: in rockchip_get_drive_perpin()
2430 ret = regmap_read(regmap, reg + 0x4, &temp); in rockchip_get_drive_perpin()
2435 * the bit data[15] contains bit 0 of the value in rockchip_get_drive_perpin()
2436 * while temp[1:0] contains bits 2 and 1 in rockchip_get_drive_perpin()
2439 temp &= 0x3; in rockchip_get_drive_perpin()
2504 ret = ((strength & BIT(2)) >> 2) | ((strength & BIT(0)) << 2) | (strength & BIT(1)); in rockchip_set_drive_perpin()
2515 for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) { in rockchip_set_drive_perpin()
2519 } else if (rockchip_perpin_drv_list[drv_type][i] < 0) { in rockchip_set_drive_perpin()
2525 if (ret < 0) { in rockchip_set_drive_perpin()
2535 case 0 ... 12: in rockchip_set_drive_perpin()
2541 * over 2 registers, the bit data[15] contains bit 0 in rockchip_set_drive_perpin()
2542 * of the value while temp[1:0] contains bits 2 and 1 in rockchip_set_drive_perpin()
2544 data = (ret & 0x1) << 15; in rockchip_set_drive_perpin()
2545 temp = (ret >> 0x1) & 0x3; in rockchip_set_drive_perpin()
2553 rmask = 0x3 | (0x3 << 16); in rockchip_set_drive_perpin()
2554 temp |= (0x3 << 16); in rockchip_set_drive_perpin()
2555 reg += 0x4; in rockchip_set_drive_perpin()
2652 if (ctrl->type == RK3568 && bank->bank_num == 0 && pin_num >= 27 && pin_num <= 30) { in rockchip_get_pull()
2679 return pull ? -EINVAL : 0; in rockchip_set_pull()
2707 for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]); in rockchip_set_pull()
2718 if (ctrl->type == RK3568 && bank->bank_num == 0 && pin_num >= 27 && pin_num <= 30) { in rockchip_set_pull()
2723 if (ret < 0) { in rockchip_set_pull()
2746 #define RK3328_SCHMITT_GRF_OFFSET 0x380
2762 return 0; in rk3328_calc_schmitt_reg_and_bit()
2767 #define RK3568_SCHMITT_BANK_STRIDE 0x10
2768 #define RK3568_SCHMITT_GRF_OFFSET 0xc0
2769 #define RK3568_SCHMITT_PMUGRF_OFFSET 0x30
2778 if (bank->bank_num == 0) { in rk3568_calc_schmitt_reg_and_bit()
2791 return 0; in rk3568_calc_schmitt_reg_and_bit()
2819 return data & 0x1; in rockchip_get_schmitt()
2845 data |= ((enable ? 0x2 : 0x1) << bit); in rockchip_set_schmitt()
2884 return 0; in rockchip_pmx_get_groups()
2895 int cnt, ret = 0; in rockchip_pmx_set()
2904 for (cnt = 0; cnt < info->groups[group].npins; cnt++) { in rockchip_pmx_set()
2914 for (cnt--; cnt >= 0; cnt--) { in rockchip_pmx_set()
2916 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0); in rockchip_pmx_set()
2922 return 0; in rockchip_pmx_set()
2992 return 0; in rockchip_pinconf_defer_pin()
3007 for (i = 0; i < num_configs; i++) { in rockchip_pinconf_set()
3080 if (rc < 0) in rockchip_pinconf_set()
3089 if (rc < 0) in rockchip_pinconf_set()
3098 return 0; in rockchip_pinconf_set()
3117 arg = 0; in rockchip_pinconf_get()
3137 arg = 0; in rockchip_pinconf_get()
3142 if (rc < 0) in rockchip_pinconf_get()
3145 arg = rc ? 1 : 0; in rockchip_pinconf_get()
3153 if (rc < 0) in rockchip_pinconf_get()
3163 if (rc < 0) in rockchip_pinconf_get()
3175 return 0; in rockchip_pinconf_get()
3241 for (i = 0, j = 0; i < size; i += 4, j++) { in rockchip_pinctrl_parse_groups()
3265 return 0; in rockchip_pinctrl_parse_groups()
3277 u32 i = 0; in rockchip_pinctrl_parse_functions()
3286 if (func->ngroups <= 0) in rockchip_pinctrl_parse_functions()
3287 return 0; in rockchip_pinctrl_parse_functions()
3301 return 0; in rockchip_pinctrl_parse_functions()
3325 i = 0; in rockchip_pinctrl_parse_dt()
3338 return 0; in rockchip_pinctrl_parse_dt()
3366 for (bank = 0, k = 0; bank < info->ctrl->nr_banks; bank++) { in rockchip_pinctrl_register()
3373 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) { in rockchip_pinctrl_register()
3391 return 0; in rockchip_pinctrl_register()
3416 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { in rockchip_pinctrl_get_soc_data()
3417 int bank_pins = 0; in rockchip_pinctrl_get_soc_data()
3425 for (j = 0; j < 4; j++) { in rockchip_pinctrl_get_soc_data()
3434 if (iom->offset >= 0) { in rockchip_pinctrl_get_soc_data()
3447 if (drv->offset >= 0) { in rockchip_pinctrl_get_soc_data()
3457 dev_dbg(dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n", in rockchip_pinctrl_get_soc_data()
3491 for (j = 0; j < ctrl->niomux_recalced; j++) { in rockchip_pinctrl_get_soc_data()
3492 int pin = 0; in rockchip_pinctrl_get_soc_data()
3501 for (j = 0; j < ctrl->niomux_routes; j++) { in rockchip_pinctrl_get_soc_data()
3502 int pin = 0; in rockchip_pinctrl_get_soc_data()
3514 #define RK3288_GRF_GPIO6C_IOMUX 0x64
3540 return 0; in rockchip_pinctrl_suspend()
3586 node = of_parse_phandle(np, "rockchip,grf", 0); in rockchip_pinctrl_probe()
3593 base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in rockchip_pinctrl_probe()
3606 if (ctrl->type == RK3188 && info->reg_size < 0x200) { in rockchip_pinctrl_probe()
3619 node = of_parse_phandle(np, "rockchip,pmu", 0); in rockchip_pinctrl_probe()
3637 return 0; in rockchip_pinctrl_probe()
3649 for (i = 0; i < info->ctrl->nr_banks; i++) { in rockchip_pinctrl_remove()
3664 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
3691 .grf_mux_offset = 0x0,
3692 .pmu_mux_offset = 0x0,
3701 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
3705 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
3706 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0),
3707 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0),
3715 .grf_mux_offset = 0x10,
3716 .pmu_mux_offset = 0x0,
3725 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0",
3735 0x10010, 0x10018, 0x10020, 0x10028),
3747 IOMUX_WIDTH_4BIT, 0, 0, 0),
3755 .grf_mux_offset = 0x10004, /* mux offset from GPIO0_D0 */
3756 .pmu_mux_offset = 0x0,
3767 PIN_BANK(0, 32, "gpio0"),
3778 .grf_mux_offset = 0xa8,
3783 PIN_BANK(0, 32, "gpio0"),
3793 .grf_mux_offset = 0xa8,
3798 PIN_BANK(0, 32, "gpio0"),
3811 .grf_mux_offset = 0xa8,
3816 PIN_BANK(0, 32, "gpio0"),
3827 .grf_mux_offset = 0x60,
3831 PIN_BANK(0, 32, "gpio0"),
3842 .grf_mux_offset = 0xa8,
3851 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
3862 .grf_mux_offset = 0x60,
3869 PIN_BANK(0, 32, "gpio0"),
3880 .grf_mux_offset = 0x0,
3888 PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
3896 0
3898 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
3899 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT),
3902 0,
3903 0
3906 0,
3907 0,
3910 PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED),
3911 PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0,
3912 0,
3924 .grf_mux_offset = 0x0,
3925 .pmu_mux_offset = 0x84,
3933 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_WIDTH_2BIT,
3960 .grf_mux_offset = 0x0,
3971 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0),
3972 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
3973 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0,
3976 0),
3980 0,
3981 0),
3989 .grf_mux_offset = 0x0,
4000 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
4015 .grf_mux_offset = 0x0,
4016 .pmu_mux_offset = 0x0,
4022 PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0",
4031 0x80,
4032 0x88,
4048 0xa0,
4049 0xa8,
4050 0xb0,
4051 0xb8
4079 .grf_mux_offset = 0xe000,
4080 .pmu_mux_offset = 0x0,
4081 .grf_drv_offset = 0xe100,
4082 .pmu_drv_offset = 0x80,
4090 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
4117 .grf_mux_offset = 0x0,
4118 .pmu_mux_offset = 0x0,
4119 .grf_drv_offset = 0x0200,
4120 .pmu_drv_offset = 0x0070,
4142 RK3576_PIN_BANK(0, "gpio0", 0, 0x8, 0x2004, 0x200C),
4143 RK3576_PIN_BANK(1, "gpio1", 0x4020, 0x4028, 0x4030, 0x4038),
4144 RK3576_PIN_BANK(2, "gpio2", 0x4040, 0x4048, 0x4050, 0x4058),
4145 RK3576_PIN_BANK(3, "gpio3", 0x4060, 0x4068, 0x4070, 0x4078),
4146 RK3576_PIN_BANK(4, "gpio4", 0x4080, 0x4088, 0xA390, 0xB398),
4160 RK3588_PIN_BANK_FLAGS(0, 32, "gpio0",