Searched +full:0 +full:x03002000 (Results 1 – 7 of 7) sorted by relevance
/freebsd/sys/contrib/device-tree/Bindings/clock/ |
H A D | sophgo,cv1800-clk.yaml | 42 reg = <0x03002000 0x1000>;
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/freebsd/sys/contrib/device-tree/src/riscv/sophgo/ |
H A D | cv18xx.dtsi | 17 #size-cells = <0>; 20 cpu0: cpu@0 { 23 reg = <0>; 47 #clock-cells = <0>; 59 reg = <0x03002000 0x1000>; 66 reg = <0x3020000 0x1000>; 68 #size-cells = <0>; 70 porta: gpio-controller@0 { 75 reg = <0>; 84 reg = <0x3021000 0x1000>; [all …]
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/freebsd/sys/contrib/device-tree/src/arm64/allwinner/ |
H A D | sun50i-a100.dtsi | 19 #size-cells = <0>; 21 cpu0: cpu@0 { 24 reg = <0x0>; 31 reg = <0x1>; 38 reg = <0x2>; 45 reg = <0x3>; 59 #clock-cells = <0>; 67 #clock-cells = <0>; 74 #clock-cells = <0>; 93 ranges = <0 [all...] |
H A D | sun50i-h616.dtsi | 21 #size-cells = <0>; 23 cpu0: cpu@0 { 26 reg = <0>; 30 i-cache-size = <0x8000>; 33 d-cache-size = <0x8000>; 46 i-cache-size = <0x8000>; 49 d-cache-size = <0x8000>; 62 i-cache-size = <0x8000>; 65 d-cache-size = <0x8000>; 78 i-cache-size = <0x8000>; [all …]
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H A D | sun50i-h6.dtsi | 22 #size-cells = <0>; 24 cpu0: cpu@0 { 27 reg = <0>; 32 i-cache-size = <0x8000>; 35 d-cache-size = <0x8000>; 49 i-cache-size = <0x8000>; 52 d-cache-size = <0x8000>; 66 i-cache-size = <0x8000>; 69 d-cache-size = <0x8000>; 83 i-cache-size = <0x8000>; [all …]
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/freebsd/sys/contrib/xen/ |
H A D | arch-arm.h | 170 #define XEN_HYPERCALL_TAG 0XEA1 199 _sxghr_tmp->q = 0; \ 201 } while ( 0 ) 294 #define _VGCF_online 0 310 #define XEN_DOMCTL_CONFIG_GIC_NATIVE 0 314 #define XEN_DOMCTL_CONFIG_TEE_NONE 0 333 * = 0 => property not present 334 * > 0 => Value of the property 362 #define PSR_IT_MASK (0x0600fc00) /* Thumb If-Then Mask */ 366 #define PSR_MODE_USR 0x10 [all …]
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/freebsd/sys/dev/qlnx/qlnxe/ |
H A D | ecore_init_values.h | 35 0x00030003, 0xffff0000, /* if phase != 'engine', skip 3 ops (no DMAE) */ 36 0x00020002, 0x00020000, /* if mode != '!asic', skip 2 ops */ 37 0x0280c201, 0x00000000, /* write 0x0 to address 0x50184 */ 38 0x02810201, 0x00000000, /* write 0x0 to address 0x50204 */ 40 0x00110003, 0xffff0000, /* if phase != 'engine', skip 17 ops (no DMAE) */ 41 0x00030002, 0x00020000, /* if mode != '!asic', skip 3 ops */ 42 0x0048c201, 0x00000000, /* write 0x0 to address 0x9184 */ 43 0x0048d201, 0x00000000, /* write 0x0 to address 0x91a4 */ 44 0x004ba601, 0x00000001, /* write 0x1 to address 0x974c */ 45 0x00020002, 0x00be0000, /* if mode != '(!asic)&bb', skip 2 ops */ [all …]
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