/linux/arch/arm/mach-rpc/include/mach/ |
H A D | hardware.h | 25 #define RPC_RAM_SIZE 0x10000000 26 #define RPC_RAM_START 0x10000000 28 #define EASI_SIZE 0x08000000 /* EASI I/O */ 29 #define EASI_START 0x08000000 30 #define EASI_BASE IOMEM(0xe5000000) 32 #define IO_START 0x03000000 /* I/O */ 33 #define IO_SIZE 0x01000000 34 #define IO_BASE IOMEM(0xe0000000) 36 #define SCREEN_START 0x02000000 /* VRAM */ 37 #define SCREEN_END 0xdfc00000 [all …]
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/linux/drivers/gpu/drm/nouveau/nvkm/engine/disp/ |
H A D | g94.c | 39 nvkm_mask(device, 0x61c128 + loff, 0x0000003f, watermark); in g94_sor_dp_watermark() 49 nvkm_mask(device, 0x61c10c + loff, 0x000001fc, TU << 2); in g94_sor_dp_activesym() 50 nvkm_mask(device, 0x61c128 + loff, 0x010f7f00, VTUa << 24 | VTUf << 16 | VTUi << 8); in g94_sor_dp_activesym() 59 nvkm_mask(device, 0x61c1e8 + soff, 0x0000ffff, h); in g94_sor_dp_audio_sym() 60 nvkm_mask(device, 0x61c1ec + soff, 0x00ffffff, v); in g94_sor_dp_audio_sym() 71 data[0] = nvkm_rd32(device, 0x61c118 + loff) & ~(0x000000ff << shift); in g94_sor_dp_drive() 72 data[1] = nvkm_rd32(device, 0x61c120 + loff) & ~(0x000000ff << shift); in g94_sor_dp_drive() 73 data[2] = nvkm_rd32(device, 0x61c130 + loff); in g94_sor_dp_drive() 74 if ((data[2] & 0x0000ff00) < (pu << 8) || ln == 0) in g94_sor_dp_drive() 75 data[2] = (data[2] & ~0x0000ff00) | (pu << 8); in g94_sor_dp_drive() [all …]
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/linux/Documentation/devicetree/bindings/net/ |
H A D | cavium-mdio.txt | 15 - #size-cells: Must be <0>. MDIO addresses have no size component. 23 #size-cells = <0>; 24 reg = <0x11800 0x00001800 0x0 0x40>; 26 ethernet-phy@0 { 28 reg = <0>; 58 reg = <0x0b00 0 0 0 0>; /* DEVFN = 0x0b (1:3) */ 59 assigned-addresses = <0x03000000 0x87e0 0x05000000 0x0 0x800000>; 60 ranges = <0x87e0 0x05000000 0x03000000 0x87e0 0x05000000 0x0 0x800000>; 65 #size-cells = <0>; 66 reg = <0x87e0 0x05003800 0x0 0x30>; [all …]
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/linux/drivers/video/fbdev/ |
H A D | i740_reg.h | 37 #define XRX 0x3D6 38 #define MRX 0x3D2 41 #define DACMASK 0x3C6 42 #define DACSTATE 0x3C7 43 #define DACRX 0x3C7 44 #define DACWX 0x3C8 45 #define DACDATA 0x3C9 48 #define START_ADDR_HI 0x0C 49 #define START_ADDR_LO 0x0D 50 #define VERT_SYNC_END 0x11 [all …]
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/linux/include/uapi/linux/media/raspberrypi/ |
H A D | pisp_common.h | 32 PISP_BAYER_ORDER_RGGB = 0, 45 PISP_IMAGE_FORMAT_BPS_8 = 0x00000000, 46 PISP_IMAGE_FORMAT_BPS_10 = 0x00000001, 47 PISP_IMAGE_FORMAT_BPS_12 = 0x00000002, 48 PISP_IMAGE_FORMAT_BPS_16 = 0x00000003, 49 PISP_IMAGE_FORMAT_BPS_MASK = 0x00000003, 51 PISP_IMAGE_FORMAT_PLANARITY_INTERLEAVED = 0x00000000, 52 PISP_IMAGE_FORMAT_PLANARITY_SEMI_PLANAR = 0x00000010, 53 PISP_IMAGE_FORMAT_PLANARITY_PLANAR = 0x00000020, 54 PISP_IMAGE_FORMAT_PLANARITY_MASK = 0x00000030, [all …]
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/linux/arch/powerpc/boot/dts/fsl/ |
H A D | mpc8536ds.dtsi | 36 nor@0,0 { 40 reg = <0x0 0x0 0x8000000>; 44 partition@0 { 45 reg = <0x0 0x03000000>; 50 reg = <0x03000000 0x00e00000>; 56 reg = <0x03e00000 0x00200000>; 62 reg = <0x04000000 0x00400000>; 67 reg = <0x04400000 0x03b00000>; 72 reg = <0x07f00000 0x00080000>; 77 reg = <0x07f80000 0x00080000>; [all …]
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H A D | p1022ds.dtsi | 36 nor@0,0 { 40 reg = <0x0 0x0 0x8000000>; 44 partition@0 { 45 reg = <0x0 0x03000000>; 51 reg = <0x03000000 0x00e00000>; 57 reg = <0x03e00000 0x00200000>; 63 reg = <0x04000000 0x00400000>; 69 reg = <0x04400000 0x03b00000>; 74 reg = <0x07f00000 0x00080000>; 80 reg = <0x07f80000 0x00080000>; [all …]
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H A D | p1023rdb.dts | 56 size = <0 0x1000000>; 57 alignment = <0 0x1000000>; 60 size = <0 0x400000>; 61 alignment = <0 0x400000>; 64 size = <0 0x2000000>; 65 alignment = <0 0x2000000>; 70 ranges = <0x0 0xf 0xff000000 0x200000>; 74 ranges = <0x0 0xf 0xff200000 0x200000>; 78 ranges = <0x0 0x0 0xff600000 0x200000>; 83 reg = <0x53>; [all …]
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H A D | p2020ds.dtsi | 36 nor@0,0 { 40 reg = <0x0 0x0 0x8000000>; 44 ramdisk@0 { 45 reg = <0x0 0x03000000>; 50 reg = <0x03000000 0x00e00000>; 55 reg = <0x03e00000 0x00200000>; 60 reg = <0x04000000 0x00400000>; 65 reg = <0x04400000 0x03b00000>; 69 reg = <0x07f00000 0x00080000>; 74 reg = <0x07f80000 0x00080000>; [all …]
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/linux/drivers/media/pci/cx18/ |
H A D | cx18-av-firmware.c | 13 #define CX18_AUDIO_ENABLE 0xc72014 14 #define CX18_AI1_MUX_MASK 0x30 15 #define CX18_AI1_MUX_I2S1 0x00 16 #define CX18_AI1_MUX_I2S2 0x10 17 #define CX18_AI1_MUX_843_I2S 0x20 18 #define CX18_AI1_MUX_INVALID 0x30 25 int ret = 0; in cx18_av_verifyfw() 34 dl_control &= 0x00ffffff; in cx18_av_verifyfw() 35 dl_control |= 0x0f000000; in cx18_av_verifyfw() 38 } while ((dl_control & 0xff000000) != 0x0f000000); in cx18_av_verifyfw() [all …]
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/linux/drivers/gpu/drm/nouveau/nvkm/subdev/clk/ |
H A D | mcp77.c | 45 return nvkm_rd32(device, 0x004600); in read_div() 52 u32 ctrl = nvkm_rd32(device, base + 0); in read_pll() 55 u32 post_div = 0; in read_pll() 56 u32 clock = 0; in read_pll() 60 case 0x4020: in read_pll() 61 post_div = 1 << ((nvkm_rd32(device, 0x4070) & 0x000f0000) >> 16); in read_pll() 63 case 0x4028: in read_pll() 64 post_div = (nvkm_rd32(device, 0x4040) & 0x000f0000) >> 16; in read_pll() 70 N1 = (coef & 0x0000ff00) >> 8; in read_pll() 71 M1 = (coef & 0x000000ff); in read_pll() [all …]
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/linux/Documentation/devicetree/bindings/clock/ |
H A D | allwinner,sun9i-a80-de-clks.yaml | 59 reg = <0x03000000 0x30>;
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H A D | qcom,sc7280-lpasscc.yaml | 65 reg = <0x03000000 0x40>, <0x03c04000 0x4>;
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/linux/drivers/dma/ |
H A D | fsl_raid.h | 47 #define FSL_RE_GFM_POLY 0x1d000000 50 #define FSL_RE_CFG1_CBSI 0x08000000 51 #define FSL_RE_CFG1_CBS0 0x00080000 56 #define FSL_RE_PQ_OPCODE 0x1B 57 #define FSL_RE_XOR_OPCODE 0x1A 58 #define FSL_RE_MOVE_OPCODE 0x8 60 #define FSL_RE_BLOCK_SIZE 0x3 /* 4096 bytes */ 61 #define FSL_RE_CACHEABLE_IO 0x0 62 #define FSL_RE_BUFFER_OUTPUT 0x0 63 #define FSL_RE_INTR_ON_ERROR 0x1 [all …]
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/linux/include/linux/mtd/ |
H A D | ndfc.h | 12 #define NDFC_CMD 0x00 13 #define NDFC_ALE 0x04 14 #define NDFC_DATA 0x08 15 #define NDFC_ECC 0x10 16 #define NDFC_BCFG0 0x30 17 #define NDFC_BCFG1 0x34 18 #define NDFC_BCFG2 0x38 19 #define NDFC_BCFG3 0x3c 20 #define NDFC_CCR 0x40 21 #define NDFC_STAT 0x44 [all …]
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/linux/drivers/message/fusion/lsi/ |
H A D | mpi_init.h | 88 U8 LUN[8]; /* 0Ch */ 100 #define MPI_SCSIIO_MSGFLGS_SENSE_WIDTH (0x01) 101 #define MPI_SCSIIO_MSGFLGS_SENSE_WIDTH_32 (0x00) 102 #define MPI_SCSIIO_MSGFLGS_SENSE_WIDTH_64 (0x01) 104 #define MPI_SCSIIO_MSGFLGS_SENSE_LOCATION (0x02) 105 #define MPI_SCSIIO_MSGFLGS_SENSE_LOC_HOST (0x00) 106 #define MPI_SCSIIO_MSGFLGS_SENSE_LOC_IOC (0x02) 108 #define MPI_SCSIIO_MSGFLGS_CMD_DETERMINES_DATA_DIR (0x04) 112 #define MPI_SCSIIO_LUN_FIRST_LEVEL_ADDRESSING (0x0000FFFF) 113 #define MPI_SCSIIO_LUN_SECOND_LEVEL_ADDRESSING (0xFFFF0000) [all …]
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/linux/drivers/net/ethernet/ibm/emac/ |
H A D | tah.h | 52 #define TAH_MR_CVR 0x80000000 53 #define TAH_MR_SR 0x40000000 54 #define TAH_MR_ST_256 0x01000000 55 #define TAH_MR_ST_512 0x02000000 56 #define TAH_MR_ST_768 0x03000000 57 #define TAH_MR_ST_1024 0x04000000 58 #define TAH_MR_ST_1280 0x05000000 59 #define TAH_MR_ST_1536 0x06000000 60 #define TAH_MR_TFS_16KB 0x00000000 61 #define TAH_MR_TFS_2KB 0x00200000 [all …]
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/linux/drivers/soc/fsl/qbman/ |
H A D | qman_priv.h | 44 u16 channel_wq; /* ignores wq (3 lsbits): _res[0-2] */ 101 #define CGR_BIT(x) (BIT(31) >> ((x) & 0x1f)) 110 memset(c, 0, sizeof(*c)); in qman_cgrs_init() 115 memset(c, 0xff, sizeof(*c)); in qman_cgrs_fill() 137 for (ret = 0; ret < 8; ret++) in qman_cgrs_and() 149 for (ret = 0; ret < 8; ret++) in qman_cgrs_xor() 181 #define QMAN_REV11 0x0101 182 #define QMAN_REV12 0x0102 183 #define QMAN_REV20 0x0200 184 #define QMAN_REV30 0x0300 [all …]
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/linux/arch/powerpc/include/asm/ |
H A D | reg_8xx.h | 29 #define SPRN_EID 81 /* External interrupt disable (EE=0, RI=1) */ 30 #define SPRN_NRI 82 /* Non recoverable interrupt (EE=0, RI=0) */ 38 #define LCTRL1_CTE_GT 0xc0000000 39 #define LCTRL1_CTF_LT 0x14000000 40 #define LCTRL1_CRWE_RW 0x00000000 41 #define LCTRL1_CRWE_RO 0x00040000 42 #define LCTRL1_CRWE_WO 0x000c0000 43 #define LCTRL1_CRWF_RW 0x00000000 44 #define LCTRL1_CRWF_RO 0x00010000 45 #define LCTRL1_CRWF_WO 0x00030000 [all …]
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/linux/Documentation/devicetree/bindings/bus/ |
H A D | arm,integrator-ap-lm.yaml | 15 determine if a logic module is connected at index 0, 1, 2 or 3. The logic 35 "^bus(@[0-9a-f]*)?$": 37 and are named with bus. The first module is at 0xc0000000, the second 38 at 0xd0000000 and so on until the top of the memory of the system at 39 0xffffffff. All information about the memory used by the module is 55 ranges = <0xc0000000 0xc0000000 0x40000000>; 60 ranges = <0x00000000 0xc0000000 0x10000000>; 61 /* The Logic Modules sees the Core Module 0 RAM @80000000 */ 62 dma-ranges = <0x00000000 0x80000000 0x10000000>; 68 reg = <0x00100000 0x1000>; [all …]
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/linux/Documentation/i2c/ |
H A D | i2c-stub.rst | 26 explicitly by setting the respective bits (0x03000000) in the functionality 52 value 0x1f0000 would only enable the quick, byte and byte data
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/linux/arch/arm64/boot/dts/rockchip/ |
H A D | rk3568.dtsi | 13 reg = <0 0xfc000000 0 0x1000>; 20 ports-implemented = <0x1>; 27 reg = <0x0 0xfdc70000 0x0 0x1000>; 32 reg = <0x0 0xfe190080 0x0 0x20>; 37 reg = <0x0 0xfe190100 0x0 0x20>; 42 reg = <0x0 0xfe190200 0x0 0x20>; 47 reg = <0x0 0xfdcb8000 0x0 0x10000>; 52 reg = <0x0 0xfe8c0000 0x0 0x20000>; 53 #phy-cells = <0>; 67 bus-range = <0x0 0xf>; [all …]
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H A D | rk3588-extra.dtsi | 12 reg = <0x0 0xfc400000 0x0 0x400000>; 13 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH 0>; 32 reg = <0x0 0xfd5b8000 0x0 0x10000>; 37 reg = <0x0 0xfd5c0000 0x0 0x100>; 42 reg = <0x0 0xfd5cc000 0x0 0x4000>; 47 reg = <0x0 0xfd5d4000 0x0 0x4000>; 53 reg = <0x4000 0x10>; 54 #clock-cells = <0>; 58 interrupts = <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH 0>; 64 #phy-cells = <0>; [all …]
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/linux/Documentation/devicetree/bindings/pci/ |
H A D | microchip,pcie-host.yaml | 41 0-3 45 pattern: '^fic[0-3]$' 64 reg = <0x0 0x70000000 0x0 0x08000000>, 65 <0x0 0x43000000 0x0 0x00010000>; 72 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 73 interrupt-map = <0 0 0 1 &pcie_intc0 0>, 74 <0 0 0 2 &pcie_intc0 1>, 75 <0 0 0 3 &pcie_intc0 2>, 76 <0 0 0 4 &pcie_intc0 3>; 80 bus-range = <0x00 0x7f>; [all …]
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/linux/drivers/staging/rtl8712/ |
H A D | rtl8712_xmit.h | 19 #define VO_QUEUE_INX 0 47 /*OFFSET 0*/ 48 #define OFFSET_SZ (0) 54 #define TYPE_MSK (0x03000000) 57 #define PKT_OFFSET_SZ (0) 75 #define RSVD6_MSK (0x00E00000) 79 /*DWORD 0*/
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