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/freebsd/sys/dev/syscons/
H A Dscvgarndr.c54 #define SC_RENDER_DEBUG 0
108 RENDERER(mda, 0, txtrndrsw, vga_set);
109 RENDERER(cga, 0, txtrndrsw, vga_set);
110 RENDERER(ega, 0, txtrndrsw, vga_set);
111 RENDERER(vga, 0, txtrndrsw, vga_set);
161 0xC000, 0xA000, 0x9000, 0x8800, 0x8400, 0x8200, 0x8100, 0x8200,
162 0x8400, 0x8400, 0x8400, 0x9200, 0xB200, 0xA900, 0xC900, 0x8600, }, {
163 0x0000, 0x4000, 0x6000, 0x7000, 0x7800, 0x7C00, 0x7E00, 0x7C00,
164 0x7800, 0x7800, 0x7800, 0x6C00, 0x4C00, 0x4600, 0x0600, 0x0000, },
169 0xC000, 0xA000, 0x9000, 0x8800, 0x8400, 0x8200, 0x8100, 0x8700,
[all …]
/freebsd/lib/msun/i387/
H A De_exp.S44 andl $0x7fffffff,%eax
45 cmpl $0x7ff00000,%eax
58 andl $0x0300,%eax
59 cmpl $0x0300,%eax /* RC == 0 && PC == 3? */
61 movl $0x137f,8(%esp)
82 * Return 0 if x is -Inf. Otherwise just return x; when x is Inf
86 cmpl $0xfff00000,8(%esp)
88 cmpl $0,4(%esp)
/freebsd/contrib/tcpdump/
H A Dprint-realtek.c36 #define RTL_PROTOCOL_OFFSET 0 /* Protocol and possibly other data - 1 byte */
38 #define RTL_PROTOCOL_RRCP 0x01 /* RRCP */
39 #define RTL_PROTOCOL_REP 0x02 /* REP */
40 #define RTL_PROTOCOL_RLDP 0x03 /* RLDP */
41 #define RTL_PROTOCOL_RLDP2 0x23 /* also RLDP */
42 #define RTL_PROTOCOL_XXX_DSA 0x04 /* DSA protocol for some chip(s) */
54 #define RTL_PROTOCOL_8306_DSA 0x90 /* RTL8306 DSA protocol */
55 #define RTL_PROTOCOL_8366RB_DSA 0xA0 /* RTL8366RB DSA protocol */
59 #define RRCP_OPCODE_MASK 0x7F /* 0x00 = hello, 0x01 = get, 0x02 = set */
60 #define RRCP_ISREPLY 0x80 /* 0 = request to switch, 0x80 = reply from switch */
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx6ul-pinfunc.h13 #define MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x0014 0x02a0 0x0000 5 0
14 #define MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x0018 0x02a4 0x0000 5 0
16 #define MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x001c 0x02a8 0x0000 5 0
17 #define MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x0020 0x02ac 0x0000 5 0
18 #define MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0024 0x02b0 0x0000 5 0
19 #define MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0028 0x02b4 0x0000 5 0
20 #define MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x002c 0x02b8 0x0000 5 0
21 #define MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0030 0x02bc 0x0000 5 0
22 #define MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0034 0x02c0 0x0000 5 0
23 #define MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0038 0x02c4 0x0000 5 0
[all …]
/freebsd/sys/dev/mii/
H A De1000phyreg.h72 #define E1000_MAX_REG_ADDRESS 0x1F
74 #define E1000_CR 0x00 /* control register */
75 #define E1000_CR_SPEED_SELECT_MSB 0x0040
76 #define E1000_CR_COLL_TEST_ENABLE 0x0080
77 #define E1000_CR_FULL_DUPLEX 0x0100
78 #define E1000_CR_RESTART_AUTO_NEG 0x0200
79 #define E1000_CR_ISOLATE 0x0400
80 #define E1000_CR_POWER_DOWN 0x0800
81 #define E1000_CR_AUTO_NEG_ENABLE 0x1000
82 #define E1000_CR_SPEED_SELECT_LSB 0x2000
[all …]
H A Dtruephyreg.h42 #define TRUEPHY_INDEX 0x10 /* XXX reserved in DS */
43 #define TRUEPHY_INDEX_MAGIC 0x402
44 #define TRUEPHY_DATA 0x11 /* XXX reserved in DS */
46 #define TRUEPHY_CTRL 0x12
47 #define TRUEPHY_CTRL_DIAG 0x0004
48 #define TRUEPHY_CTRL_RSV1 0x0002 /* XXX reserved */
49 #define TRUEPHY_CTRL_RSV0 0x0001 /* XXX reserved */
51 #define TRUEPHY_CONF 0x16
52 #define TRUEPHY_CONF_TXFIFO_MASK 0x3000
53 #define TRUEPHY_CONF_TXFIFO_8 0x0000
[all …]
H A Dbrgphyreg.h42 #define BRGPHY_MII_BMCR 0x00
43 #define BRGPHY_BMCR_RESET 0x8000
44 #define BRGPHY_BMCR_LOOP 0x4000
45 #define BRGPHY_BMCR_SPD0 0x2000 /* Speed select, lower bit */
46 #define BRGPHY_BMCR_AUTOEN 0x1000 /* Autoneg enabled */
47 #define BRGPHY_BMCR_PDOWN 0x0800 /* Power down */
48 #define BRGPHY_BMCR_ISO 0x0400 /* Isolate */
49 #define BRGPHY_BMCR_STARTNEG 0x0200 /* Restart autoneg */
50 #define BRGPHY_BMCR_FDX 0x0100 /* Duplex mode */
51 #define BRGPHY_BMCR_CTEST 0x0080 /* Collision test enable */
[all …]
/freebsd/tools/test/iconv/ref/
H A DCP12581 0x0000 = 0x0000
2 0x0001 = 0x0001
3 0x0002 = 0x0002
4 0x0003 = 0x0003
5 0x0004 = 0x0004
6 0x0005 = 0x0005
7 0x0006 = 0x0006
8 0x0007 = 0x0007
9 0x0008 = 0x0008
10 0x0009 = 0x0009
[all …]
H A DTCVN5712-11 0x0000 = 0x0000
2 0x0001 = 0x0000
3 0x0002 = 0x1EE4
4 0x0003 = 0x0003
5 0x0004 = 0x1EEA
6 0x0005 = 0x1EEC
7 0x0006 = 0x1EEE
8 0x0007 = 0x0007
9 0x0008 = 0x0008
10 0x0009 = 0x0009
[all …]
/freebsd/crypto/openssl/include/openssl/
H A Dprov_ssl.h22 # define SSL3_VERSION 0x0300
23 # define TLS1_VERSION 0x0301
24 # define TLS1_1_VERSION 0x0302
25 # define TLS1_2_VERSION 0x0303
26 # define TLS1_3_VERSION 0x0304
27 # define DTLS1_VERSION 0xFEFF
28 # define DTLS1_2_VERSION 0xFEFD
29 # define DTLS1_BAD_VER 0x0100
/freebsd/share/i18n/csmapper/TCVN/
H A DTCVN5712-1%UCS.src5 SRC_ZONE 0x0000-0xF3FF
7 DST_ILSEQ 0xFFFE
46 0x0000 = 0x0000
47 0x0001 = 0x0000
48 0x0001 = 0x00DA
49 0x0002 = 0x1EE4
50 0x0003 = 0x0003
51 0x0004 = 0x1EEA
52 0x0005 = 0x1EEC
53 0x0006 = 0x1EEE
[all …]
/freebsd/sys/x86/include/
H A Dapm_bios.h25 #define APM_BIOS 0x53
26 #define APM_INT 0x15
29 #define APM_16BIT_SUPPORT 0x01
30 #define APM_32BIT_SUPPORT 0x02
31 #define APM_CPUIDLE_SLOW 0x04
32 #define APM_DISABLED 0x08
33 #define APM_DISENGAGED 0x10
36 #define APM_OURADDR 0x00080000
39 #define APM_INSTCHECK 0x00
40 #define APM_REALCONNECT 0x01
[all …]
/freebsd/contrib/llvm-project/compiler-rt/lib/builtins/loongarch/
H A Dfp_mode.c3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
10 #define LOONGARCH_TONEAREST 0x0000
11 #define LOONGARCH_TOWARDZERO 0x0100
12 #define LOONGARCH_UPWARD 0x0200
13 #define LOONGARCH_DOWNWARD 0x0300
18 #define LOONGARCH_INEXACT 0x10000
21 #if __loongarch_frlen != 0 in __fe_getround()
24 __asm__ __volatile__("movfcsr2gr %0, $fcsr0" : "=r" (fcsr)); in __fe_getround()
26 __asm__ __volatile__("movfcsr2gr %0, $r0" : "=r" (fcsr)); in __fe_getround()
46 #if __loongarch_frlen != 0 in __fe_raise_inexact()
[all …]
/freebsd/sys/compat/linuxkpi/common/include/linux/
H A Dpci_ids.h33 #define PCI_CLASS_NETWORK_OTHER 0x0280
35 #define PCI_BASE_CLASS_DISPLAY 0x03
36 #define PCI_CLASS_DISPLAY_VGA 0x0300
37 #define PCI_CLASS_DISPLAY_OTHER 0x0380
39 #define PCI_BASE_CLASS_BRIDGE 0x06
40 #define PCI_CLASS_BRIDGE_ISA 0x0601
42 #define PCI_CLASS_ACCELERATOR_PROCESSING 0x1200
47 #define PCI_VENDOR_ID_APPLE 0x106b
48 #define PCI_VENDOR_ID_ASUSTEK 0x1043
49 #define PCI_VENDOR_ID_ATHEROS 0x168c
[all …]
/freebsd/sys/dev/ntb/ntb_hw/
H A Dntb_hw_intel.h42 * Params: [in] P = Bit position of start of the bit field (lsb is 0).
51 #define NTB_LINK_STATUS_ACTIVE 0x2000
52 #define NTB_LINK_SPEED_MASK 0x000f
53 #define NTB_LINK_WIDTH_MASK 0x03f0
67 #define XEON_SPCICMD_OFFSET 0x0504
68 #define XEON_DEVCTRL_OFFSET 0x0598
69 #define XEON_DEVSTS_OFFSET 0x059a
70 #define XEON_LINK_STATUS_OFFSET 0x01a2
71 #define XEON_SLINK_STATUS_OFFSET 0x05a2
73 #define XEON_PBAR2LMT_OFFSET 0x0000
[all …]
/freebsd/sys/dev/usb/net/
H A Dif_axereg.h46 * the data length (0 to 15) and D represents the direction (0 for vendor read,
50 #define AXE_CMD_IS_WRITE(x) (((x) & 0x0F00) >> 8)
51 #define AXE_CMD_LEN(x) (((x) & 0xF000) >> 12)
52 #define AXE_CMD_CMD(x) ((x) & 0x00FF)
54 #define AXE_172_CMD_READ_RXTX_SRAM 0x2002
55 #define AXE_182_CMD_READ_RXTX_SRAM 0x8002
56 #define AXE_172_CMD_WRITE_RX_SRAM 0x0103
57 #define AXE_182_CMD_WRITE_RXTX_SRAM 0x8103
58 #define AXE_172_CMD_WRITE_TX_SRAM 0x0104
59 #define AXE_CMD_MII_OPMODE_SW 0x0106
[all …]
/freebsd/sys/dev/qcom_qup/
H A Dqcom_spi_reg.h31 #define SPI_CONFIG 0x0300
36 #define SPI_IO_CONTROL 0x0304
42 #define SPI_IO_C_CS_SELECT_MASK 0x000c
44 #define SPI_IO_C_NO_TRI_STATE (1U << 0)
46 #define SPI_ERROR_FLAGS 0x0308
47 #define SPI_ERROR_FLAGS_EN 0x030c
49 #define SPI_ERROR_CLK_UNDER_RUN (1U << 0)
/freebsd/share/i18n/csmapper/CP/
H A DCP1163%UCS.src30 SRC_ZONE 0x00-0xFF
32 DST_ILSEQ 0xFFFE
43 0x00 - 0xA3 = 0x0000 -
44 0xA4 = 0x20AC
45 0xA5 - 0xA7 = 0x00A5 -
46 0xA8 = 0x0153
47 0xA9 - 0xB3 = 0x00A9 -
48 0xB4 = 0x0178
49 0xB5 - 0xB7 = 0x00B5 -
50 0xB8 = 0x0152
[all …]
/freebsd/share/i18n/csmapper/JIS/
H A DJISX0213-1%UCS@BMP.src5 SRC_ZONE 0x21-0x7E / 0x21-0x7E / 8
7 DST_INVALID 0xFFFE
34 0x222F = 0xFF07 # 0x0027
35 0x2230 = 0xFF02 # 0x0022
36 0x2231 = 0xFF0D # 0x002D
37 0x2232 = 0xFF5E # 0x007E
38 0x2233 = 0x3033
39 0x2234 = 0x3034
40 0x2235 = 0x3035
41 0x2236 = 0x303B
[all …]
H A DUCS@BMP%JISX0213-1.src5 SRC_ZONE 0x007E - 0xFF60
7 DST_INVALID 0xFFFF
30 0x00A0 = 0x2922
31 0x00A1 = 0x2923
32 0x00A4 = 0x2924
33 0x00A6 = 0x2925
34 0x00A9 = 0x2926
35 0x00AA = 0x2927
36 0x00AB = 0x2928
37 0x00AD = 0x2929
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx95-pinfunc.h13 #define IMX95_PAD_DAP_TDI__JTAG_MUX_TDI 0x0000 0x0204 0x0610 0x00 0x00
14 #define IMX95_PAD_DAP_TDI__NETCMIX_TOP_MQS2_LEFT 0x0000 0x0204 0x0000 0x01 0x00
15 #define IMX95_PAD_DAP_TDI__NETCMIX_TOP_NETC_TMR_1588_ALARM1 0x0000 0x0204 0x0000 0x02 0x00
16 #define IMX95_PAD_DAP_TDI__CAN2_TX 0x0000 0x0204 0x0000 0x03 0x00
17 #define IMX95_PAD_DAP_TDI__FLEXIO2_FLEXIO_BIT30 0x0000 0x0204 0x0000 0x04 0x00
18 #define IMX95_PAD_DAP_TDI__GPIO3_IO_BIT28 0x0000 0x0204 0x0000 0x05 0x00
19 #define IMX95_PAD_DAP_TDI__LPUART5_RX 0x0000 0x0204 0x0570 0x06 0x00
21 #define IMX95_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x0004 0x0208 0x0614 0x00 0x00
22 #define IMX95_PAD_DAP_TMS_SWDIO__CAN4_TX 0x0004 0x0208 0x0000 0x02 0x00
23 #define IMX95_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO_BIT31 0x0004 0x0208 0x0000 0x04 0x00
[all …]
H A Dimx93-pinfunc.h13 #define MX93_PAD_DAP_TDI__JTAG_MUX_TDI 0x0000 0x01B0 0x03D8 0x0 0x0
14 #define MX93_PAD_DAP_TDI__MQS2_LEFT 0x0000 0x01B0 0x0000 0x1 0x0
15 #define MX93_PAD_DAP_TDI__CAN2_TX 0x0000 0x01B0 0x0000 0x3 0x0
16 #define MX93_PAD_DAP_TDI__FLEXIO2_FLEXIO30 0x0000 0x01B0 0x0000 0x4 0x0
17 #define MX93_PAD_DAP_TDI__GPIO3_IO28 0x0000 0x01B0 0x0000 0x5 0x0
18 #define MX93_PAD_DAP_TDI__LPUART5_RX 0x0000 0x01B0 0x0430 0x6 0x0
19 #define MX93_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x0004 0x01B4 0x03DC 0x0 0x0
20 #define MX93_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO31 0x0004 0x01B4 0x0000 0x4 0x0
21 #define MX93_PAD_DAP_TMS_SWDIO__GPIO3_IO29 0x0004 0x01B4 0x0000 0x5 0x0
22 #define MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x0004 0x01B4 0x0000 0x6 0x0
[all …]
/freebsd/sys/dev/bnxt/bnxt_en/
H A Dbnxt_dcb.h33 #define BNXT_IEEE_8021QAZ_TSA_STRICT 0
37 #define BNXT_DCB_CAP_DCBX_HOST 0x01
38 #define BNXT_DCB_CAP_DCBX_LLD_MANAGED 0x02
39 #define BNXT_DCB_CAP_DCBX_VER_CEE 0x04
40 #define BNXT_DCB_CAP_DCBX_VER_IEEE 0x08
41 #define BNXT_DCB_CAP_DCBX_STATIC 0x10
57 #define BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
116 #define ETH_P_ROCE 0x8915
125 #define HWRM_STRUCT_DATA_SUBTYPE_HOST_OPERATIONAL 0x0300
/freebsd/libexec/rbootd/
H A Drmp.h54 * Define RMP/Ethernet Multicast address (9:0:9:0:0:4) and its length.
56 #define RMP_ADDR { 0x9, 0x0, 0x9, 0x0, 0x0, 0x4 }
62 #define IEEE_DSAP_HP 0xF8 /* Destination Service Access Point */
63 #define IEEE_SSAP_HP 0xF8 /* Source Service Access Point */
64 #define IEEE_CNTL_HP 0x0300 /* Type 1 / I format control information */
66 #define HPEXT_DXSAP 0x608 /* HP Destination Service Access Point */
67 #define HPEXT_SXSAP 0x609 /* HP Source Service Access Point */
/freebsd/sys/dev/e1000/
H A De1000_phy.h132 #define IGP01E1000_PHY_PORT_CONFIG 0x10 /* Port Config */
133 #define IGP01E1000_PHY_PORT_STATUS 0x11 /* Status */
134 #define IGP01E1000_PHY_PORT_CTRL 0x12 /* Control */
135 #define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health */
136 #define IGP01E1000_GMII_FIFO 0x14 /* GMII FIFO */
137 #define IGP02E1000_PHY_POWER_MGMT 0x19 /* Power Management */
138 #define IGP01E1000_PHY_PAGE_SELECT 0x1F /* Page Select */
141 #define PHY_REG_MASK 0x1F
144 #define GS40G_PAGE_SELECT 0x16
146 #define GS40G_OFFSET_MASK 0xFFFF
[all …]

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