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Searched +full:0 +full:x02200000 (Results 1 – 6 of 6) sorted by relevance

/linux/Documentation/devicetree/bindings/ata/
H A Dimx-sata.yaml124 reg = <0x02200000 0x4000>;
125 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
/linux/drivers/net/wireless/mediatek/mt76/mt7915/
H A Dcoredump.c16 .start = 0xe003b400,
17 .len = 0x00003bff,
24 .start = 0x00800000,
25 .len = 0x0005ffff,
29 .start = 0x00900000,
30 .len = 0x00013fff,
34 .start = 0x02200000,
35 .len = 0x0004ffff,
39 .start = 0x02300000,
40 .len = 0x0004ffff,
[all …]
/linux/drivers/net/wireless/mediatek/mt76/mt7996/
H A Dcoredump.c16 .start = 0x00800000,
17 .len = 0x0004ffff,
21 .start = 0x00900000,
22 .len = 0x00037fff,
26 .start = 0x02200000,
27 .len = 0x0003ffff,
31 .start = 0x00400000,
32 .len = 0x00067fff,
36 .start = 0xe0000000,
37 .len = 0x0015ffff,
[all …]
/linux/arch/arm/net/
H A Dbpf_jit_32.h12 #define ARM_R0 0
29 #define ARM_COND_EQ 0x0 /* == */
30 #define ARM_COND_NE 0x1 /* != */
31 #define ARM_COND_CS 0x2 /* unsigned >= */
33 #define ARM_COND_CC 0x3 /* unsigned < */
35 #define ARM_COND_MI 0x4 /* < 0 */
36 #define ARM_COND_PL 0x5 /* >= 0 */
37 #define ARM_COND_VS 0x6 /* Signed Overflow */
38 #define ARM_COND_VC 0x7 /* No Signed Overflow */
39 #define ARM_COND_HI 0x8 /* unsigned > */
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6q.dtsi17 #size-cells = <0>;
19 cpu0: cpu@0 {
22 reg = <0>;
165 reg = <0x00900000 0x40000>;
166 ranges = <0 0x00900000 0x40000>;
176 #size-cells = <0>;
178 reg = <0x02018000 0x4000>;
179 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
192 reg = <0x02200000 0x4000>;
193 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
[all …]
/linux/include/soc/fsl/qe/
H A Dqe.h34 QE_CLK_NONE = 0,
150 return 0; in cpm_muram_dma()
245 return 0; in qe_alive_during_sleep()
291 u8 split; /* 0 = shared I-RAM, 1 = split I-RAM */
304 __be32 traps[16]; /* Trap addresses, 0 == ignore */
348 #define BD_STATUS_MASK 0xffff0000
349 #define BD_LENGTH_MASK 0x0000ffff
357 #define QE_RISC_ALLOCATION_RISC1 0x1 /* RISC 1 */
358 #define QE_RISC_ALLOCATION_RISC2 0x2 /* RISC 2 */
359 #define QE_RISC_ALLOCATION_RISC3 0x4 /* RISC 3 */
[all …]