Lines Matching +full:0 +full:x02200000
31 bus@0 {
36 ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
40 reg = <0x0 0x00100000 0x0 0xf000>,
41 <0x0 0x0010f000 0x0 0x1000>;
47 reg = <0x0 0x02080000 0x0 0x00121000>;
48 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
70 reg = <0x0 0x02200000 0x0 0x10000>,
71 <0x0 0x02210000 0x0 0x10000>;
124 gpio-ranges = <&pinmux 0 0 164>;
129 reg = <0x0 0x2430000 0x0 0x19100>;
135 reg = <0x0 0x2600000 0x0 0x210000>;
172 dma-channel-mask = <0xfffffffe>;
187 ranges = <0x0 0x02900000 0x0 0x02900000 0x0 0x200000>;
191 reg = <0x0 0x02900800 0x0 0x800>;
201 ranges = <0x0 0x02900800 0x0 0x02900800 0x0 0x11800>;
206 reg = <0x0 0x2901000 0x0 0x100>;
218 #size-cells = <0>;
220 port@0 {
221 reg = <0>;
242 reg = <0x0 0x2901100 0x0 0x100>;
254 #size-cells = <0>;
256 port@0 {
257 reg = <0>;
278 reg = <0x0 0x2901200 0x0 0x100>;
290 #size-cells = <0>;
292 port@0 {
293 reg = <0>;
314 reg = <0x0 0x2901300 0x0 0x100>;
326 #size-cells = <0>;
328 port@0 {
329 reg = <0>;
350 reg = <0x0 0x2901400 0x0 0x100>;
362 #size-cells = <0>;
364 port@0 {
365 reg = <0>;
386 reg = <0x0 0x2901500 0x0 0x100>;
398 #size-cells = <0>;
400 port@0 {
401 reg = <0>;
422 reg = <0x0 0x2902000 0x0 0x200>;
427 #size-cells = <0>;
429 port@0 {
430 reg = <0>;
450 reg = <0x0 0x2902200 0x0 0x200>;
455 #size-cells = <0>;
457 port@0 {
458 reg = <0>;
478 reg = <0x0 0x2902400 0x0 0x200>;
483 #size-cells = <0>;
485 port@0 {
486 reg = <0>;
506 reg = <0x0 0x2902600 0x0 0x200>;
511 #size-cells = <0>;
513 port@0 {
514 reg = <0>;
534 reg = <0x0 0x2903000 0x0 0x100>;
539 #size-cells = <0>;
541 port@0 {
542 reg = <0>;
586 reg = <0x0 0x2903100 0x0 0x100>;
591 #size-cells = <0>;
593 port@0 {
594 reg = <0>;
638 reg = <0x0 0x2903200 0x0 0x100>;
643 #size-cells = <0>;
645 port@0 {
646 reg = <0>;
690 reg = <0x0 0x2903300 0x0 0x100>;
695 #size-cells = <0>;
697 port@0 {
698 reg = <0>;
742 reg = <0x0 0x2903800 0x0 0x100>;
747 #size-cells = <0>;
749 port@0 {
750 reg = <0>;
794 reg = <0x0 0x2903900 0x0 0x100>;
799 #size-cells = <0>;
801 port@0 {
802 reg = <0>;
846 reg = <0x0 0x2903a00 0x0 0x100>;
851 #size-cells = <0>;
853 port@0 {
854 reg = <0>;
898 reg = <0x0 0x2903b00 0x0 0x100>;
903 #size-cells = <0>;
905 port@0 {
906 reg = <0>;
951 reg = <0x0 0x2904000 0x0 0x100>;
962 #size-cells = <0>;
964 port@0 {
965 reg = <0>;
985 reg = <0x0 0x2904100 0x0 0x100>;
996 #size-cells = <0>;
998 port@0 {
999 reg = <0>;
1019 reg = <0x0 0x2904200 0x0 0x100>;
1030 #size-cells = <0>;
1032 port@0 {
1033 reg = <0>;
1053 reg = <0x0 0x2904300 0x0 0x100>;
1064 #size-cells = <0>;
1066 port@0 {
1067 reg = <0>;
1087 reg = <0x0 0x2905000 0x0 0x100>;
1098 #size-cells = <0>;
1100 port@0 {
1101 reg = <0>;
1121 reg = <0x0 0x2905100 0x0 0x100>;
1132 #size-cells = <0>;
1134 port@0 {
1135 reg = <0>;
1155 reg = <0x0 0x2908000 0x0 0x100>;
1165 reg = <0x0 0x2908100 0x0 0x100>;
1171 reg = <0x0 0x2908200 0x0 0x200>;
1176 #size-cells = <0>;
1178 port@0 {
1179 reg = <0x0>;
1188 reg = <0x1>;
1201 reg = <0x0 0x290a000 0x0 0x200>;
1206 #size-cells = <0>;
1208 port@0 {
1209 reg = <0>;
1229 reg = <0x0 0x290a200 0x0 0x200>;
1234 #size-cells = <0>;
1236 port@0 {
1237 reg = <0>;
1257 reg = <0x0 0x290bb00 0x0 0x800>;
1262 #size-cells = <0>;
1264 port@0 {
1265 reg = <0x0>;
1273 reg = <0x1>;
1281 reg = <0x2>;
1289 reg = <0x3>;
1297 reg = <0x4>;
1305 reg = <0x5>;
1313 reg = <0x6>;
1321 reg = <0x7>;
1329 reg = <0x8>;
1337 reg = <0x9>;
1345 reg = <0xa>;
1353 reg = <0xb>;
1361 reg = <0xc>;
1369 reg = <0xd>;
1377 reg = <0xe>;
1389 reg = <0x0 0x0290f000 0x0 0x1000>;
1437 #size-cells = <0>;
1439 admaif0_port: port@0 {
1440 reg = <0x0>;
1448 reg = <0x1>;
1456 reg = <0x2>;
1464 reg = <0x3>;
1472 reg = <0x4>;
1480 reg = <0x5>;
1488 reg = <0x6>;
1496 reg = <0x7>;
1504 reg = <0x8>;
1512 reg = <0x9>;
1520 reg = <0xa>;
1528 reg = <0xb>;
1536 reg = <0xc>;
1544 reg = <0xd>;
1552 reg = <0xe>;
1560 reg = <0xf>;
1568 reg = <0x10>;
1576 reg = <0x11>;
1584 reg = <0x12>;
1592 reg = <0x13>;
1604 reg = <0x0 0x2910000 0x0 0x2000>;
1609 #size-cells = <0>;
1611 port@0 {
1612 reg = <0x0>;
1621 reg = <0x1>;
1630 reg = <0x2>;
1639 reg = <0x3>;
1648 reg = <0x4>;
1657 reg = <0x5>;
1666 reg = <0x6>;
1675 reg = <0x7>;
1684 reg = <0x8>;
1693 reg = <0x9>;
1702 reg = <0xa>;
1711 reg = <0xb>;
1720 reg = <0xc>;
1732 #size-cells = <0>;
1734 port@0 {
1735 reg = <0x0>;
1743 reg = <0x1>;
1751 reg = <0x2>;
1759 reg = <0x3>;
1767 reg = <0x4>;
1775 reg = <0x5>;
1783 reg = <0x6>;
1791 reg = <0x7>;
1799 reg = <0x8>;
1807 reg = <0x9>;
1815 reg = <0xa>;
1823 reg = <0xb>;
1831 reg = <0xc>;
1839 reg = <0xd>;
1847 reg = <0xe>;
1855 reg = <0xf>;
1863 reg = <0x10>;
1871 reg = <0x11>;
1879 reg = <0x12>;
1887 reg = <0x13>;
1895 reg = <0x14>;
1903 reg = <0x15>;
1911 reg = <0x16>;
1919 reg = <0x17>;
1927 reg = <0x18>;
1935 reg = <0x19>;
1943 reg = <0x1a>;
1951 reg = <0x1b>;
1959 reg = <0x1c>;
1967 reg = <0x1d>;
1975 reg = <0x1e>;
1983 reg = <0x1f>;
1991 reg = <0x20>;
1999 reg = <0x21>;
2007 reg = <0x22>;
2015 reg = <0x23>;
2023 reg = <0x24>;
2031 reg = <0x25>;
2039 reg = <0x26>;
2047 reg = <0x27>;
2055 reg = <0x28>;
2063 reg = <0x29>;
2071 reg = <0x2a>;
2079 reg = <0x2b>;
2087 reg = <0x2c>;
2095 reg = <0x2d>;
2103 reg = <0x2e>;
2111 reg = <0x2f>;
2119 reg = <0x30>;
2127 reg = <0x31>;
2135 reg = <0x32>;
2143 reg = <0x33>;
2151 reg = <0x34>;
2159 reg = <0x35>;
2167 reg = <0x36>;
2175 reg = <0x37>;
2183 reg = <0x38>;
2191 reg = <0x39>;
2199 reg = <0x3a>;
2207 reg = <0x3b>;
2215 reg = <0x3c>;
2223 reg = <0x3d>;
2231 reg = <0x3e>;
2239 reg = <0x3f>;
2247 reg = <0x40>;
2255 reg = <0x41>;
2263 reg = <0x42>;
2271 reg = <0x43>;
2279 reg = <0x44>;
2287 reg = <0x45>;
2295 reg = <0x46>;
2303 reg = <0x47>;
2311 reg = <0x48>;
2319 reg = <0x49>;
2327 reg = <0x4a>;
2335 reg = <0x4b>;
2343 reg = <0x4c>;
2351 reg = <0x4d>;
2359 reg = <0x4e>;
2367 reg = <0x4f>;
2375 reg = <0x50>;
2383 reg = <0x51>;
2391 reg = <0x52>;
2399 reg = <0x53>;
2407 reg = <0x54>;
2415 reg = <0x55>;
2423 reg = <0x56>;
2431 reg = <0x57>;
2439 reg = <0x58>;
2447 reg = <0x59>;
2455 reg = <0x5a>;
2463 reg = <0x5b>;
2471 reg = <0x5c>;
2479 reg = <0x5d>;
2487 reg = <0x5e>;
2495 reg = <0x5f>;
2503 reg = <0x60>;
2511 reg = <0x61>;
2519 reg = <0x62>;
2527 reg = <0x63>;
2535 reg = <0x64>;
2543 reg = <0x65>;
2551 reg = <0x66>;
2559 reg = <0x67>;
2567 reg = <0x68>;
2575 reg = <0x69>;
2583 reg = <0x6a>;
2591 reg = <0x6b>;
2599 reg = <0x6c>;
2607 reg = <0x6d>;
2615 reg = <0x6e>;
2623 reg = <0x6f>;
2631 reg = <0x70>;
2639 reg = <0x71>;
2651 reg = <0x0 0x02930000 0x0 0x20000>;
2653 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
2696 reg = <0x0 0x02a41000 0x0 0x1000>,
2697 <0x0 0x02a42000 0x0 0x2000>;
2709 reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */
2710 <0x0 0x02c10000 0x0 0x10000>, /* MC Broadcast*/
2711 <0x0 0x02c20000 0x0 0x10000>, /* MC0 */
2712 <0x0 0x02c30000 0x0 0x10000>, /* MC1 */
2713 <0x0 0x02c40000 0x0 0x10000>, /* MC2 */
2714 <0x0 0x02c50000 0x0 0x10000>, /* MC3 */
2715 <0x0 0x02b80000 0x0 0x10000>, /* MC4 */
2716 <0x0 0x02b90000 0x0 0x10000>, /* MC5 */
2717 <0x0 0x02ba0000 0x0 0x10000>, /* MC6 */
2718 <0x0 0x02bb0000 0x0 0x10000>, /* MC7 */
2719 <0x0 0x01700000 0x0 0x10000>, /* MC8 */
2720 <0x0 0x01710000 0x0 0x10000>, /* MC9 */
2721 <0x0 0x01720000 0x0 0x10000>, /* MC10 */
2722 <0x0 0x01730000 0x0 0x10000>, /* MC11 */
2723 <0x0 0x01740000 0x0 0x10000>, /* MC12 */
2724 <0x0 0x01750000 0x0 0x10000>, /* MC13 */
2725 <0x0 0x01760000 0x0 0x10000>, /* MC14 */
2726 <0x0 0x01770000 0x0 0x10000>; /* MC15 */
2736 ranges = <0x0 0x01700000 0x0 0x01700000 0x0 0x100000>,
2737 <0x0 0x02b80000 0x0 0x02b80000 0x0 0x040000>,
2738 <0x0 0x02c00000 0x0 0x02c00000 0x0 0x100000>;
2753 * Limit the DMA range for memory clients to [38:0].
2755 dma-ranges = <0x0 0x0 0x0 0x0 0x80 0x0>;
2759 reg = <0x0 0x02c60000 0x0 0x90000>,
2760 <0x0 0x01780000 0x0 0x80000>;
2766 #interconnect-cells = <0>;
2774 reg = <0x0 0x03100000 0x0 0x10000>;
2785 reg = <0x0 0x03140000 0x0 0x10000>;
2796 reg = <0x0 0x3160000 0x0 0x100>;
2800 #size-cells = <0>;
2815 reg = <0x0 0x3180000 0x0 0x100>;
2818 #size-cells = <0>;
2834 reg = <0x0 0x3190000 0x0 0x100>;
2837 #size-cells = <0>;
2853 reg = <0x0 0x31b0000 0x0 0x100>;
2856 #size-cells = <0>;
2872 reg = <0x0 0x31c0000 0x0 0x100>;
2875 #size-cells = <0>;
2891 reg = <0x0 0x31d0000 0x0 0x10000>;
2898 reg = <0x0 0x31e0000 0x0 0x100>;
2901 #size-cells = <0>;
2917 reg = <0x0 0x03210000 0x0 0x1000>;
2920 #size-cells = <0>;
2936 reg = <0x0 0x03230000 0x0 0x1000>;
2939 #size-cells = <0>;
2955 reg = <0x0 0x3270000 0x0 0x1000>;
2958 #size-cells = <0>;
2973 reg = <0x0 0x3280000 0x0 0x10000>;
2983 reg = <0x0 0x3290000 0x0 0x10000>;
2993 reg = <0x0 0x32a0000 0x0 0x10000>;
3003 reg = <0x0 0x32c0000 0x0 0x10000>;
3013 reg = <0x0 0x32d0000 0x0 0x10000>;
3023 reg = <0x0 0x32e0000 0x0 0x10000>;
3033 reg = <0x0 0x32f0000 0x0 0x10000>;
3043 reg = <0x0 0x3300000 0x0 0x1000>;
3046 #size-cells = <0>;
3061 reg = <0x0 0x03400000 0x0 0x20000>;
3077 pinctrl-0 = <&sdmmc1_3v3>;
3079 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
3080 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x07>;
3081 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
3082 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
3083 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
3084 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
3086 nvidia,default-trim = <0x8>;
3096 reg = <0x0 0x03460000 0x0 0x20000>;
3110 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>;
3111 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>;
3112 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
3113 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>;
3114 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
3115 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>;
3116 nvidia,default-tap = <0x8>;
3117 nvidia,default-trim = <0x14>;
3125 reg = <0x0 0x3510000 0x0 0x10000>;
3143 reg = <0x0 0x03520000 0x0 0x20000>,
3144 <0x0 0x03540000 0x0 0x10000>;
3159 usb2-0 {
3162 #phy-cells = <0>;
3168 #phy-cells = <0>;
3174 #phy-cells = <0>;
3180 #phy-cells = <0>;
3187 usb3-0 {
3190 #phy-cells = <0>;
3196 #phy-cells = <0>;
3202 #phy-cells = <0>;
3208 #phy-cells = <0>;
3215 usb2-0 {
3231 usb3-0 {
3251 reg = <0x0 0x03550000 0x0 0x8000>,
3252 <0x0 0x03558000 0x0 0x8000>;
3274 reg = <0x0 0x03610000 0x0 0x40000>,
3275 <0x0 0x03600000 0x0 0x10000>,
3276 <0x0 0x03650000 0x0 0x10000>;
3311 reg = <0x0 0x03810000 0x0 0x10000>;
3318 reg = <0x0 0x3aa0000 0x0 0x10000>;
3326 reg = <0x0 0x03c00000 0x0 0xa0000>;
3344 reg = <0x0 0x03e00000 0x0 0x10000>;
3347 #phy-cells = <0>;
3352 reg = <0x0 0x03e10000 0x0 0x10000>;
3355 #phy-cells = <0>;
3360 reg = <0x0 0x03e20000 0x0 0x10000>;
3363 #phy-cells = <0>;
3368 reg = <0x0 0x03e30000 0x0 0x10000>;
3371 #phy-cells = <0>;
3376 reg = <0x0 0x03e40000 0x0 0x10000>;
3379 #phy-cells = <0>;
3384 reg = <0x0 0x03e50000 0x0 0x10000>;
3387 #phy-cells = <0>;
3392 reg = <0x0 0x03e60000 0x0 0x10000>;
3395 #phy-cells = <0>;
3400 reg = <0x0 0x03e70000 0x0 0x10000>;
3403 #phy-cells = <0>;
3408 reg = <0x0 0x03e90000 0x0 0x10000>;
3411 #phy-cells = <0>;
3416 reg = <0x0 0x03ea0000 0x0 0x10000>;
3419 #phy-cells = <0>;
3424 reg = <0x0 0x03eb0000 0x0 0x10000>;
3427 #phy-cells = <0>;
3432 reg = <0x0 0x03ec0000 0x0 0x10000>;
3435 #phy-cells = <0>;
3440 reg = <0x0 0x03ed0000 0x0 0x10000>;
3443 #phy-cells = <0>;
3448 reg = <0x0 0x03ee0000 0x0 0x10000>;
3451 #phy-cells = <0>;
3456 reg = <0x0 0x03ef0000 0x0 0x10000>;
3459 #phy-cells = <0>;
3464 reg = <0x0 0x03f00000 0x0 0x10000>;
3467 #phy-cells = <0>;
3472 reg = <0x0 0x03f20000 0x0 0x10000>;
3475 #phy-cells = <0>;
3480 reg = <0x0 0x03f30000 0x0 0x10000>;
3483 #phy-cells = <0>;
3488 reg = <0x0 0x03f40000 0x0 0x10000>;
3491 #phy-cells = <0>;
3496 reg = <0x0 0x03f50000 0x0 0x10000>;
3499 #phy-cells = <0>;
3504 reg = <0x0 0x03f60000 0x0 0x10000>;
3507 #phy-cells = <0>;
3512 reg = <0x0 0x03f70000 0x0 0x10000>;
3515 #phy-cells = <0>;
3520 reg = <0x0 0x03f80000 0x0 0x10000>;
3523 #phy-cells = <0>;
3528 reg = <0x0 0x03f90000 0x0 0x10000>;
3531 #phy-cells = <0>;
3536 reg = <0x0 0x06800000 0x0 0x10000>,
3537 <0x0 0x06810000 0x0 0x10000>,
3538 <0x0 0x068a0000 0x0 0x10000>;
3578 reg = <0x0 0x06900000 0x0 0x10000>,
3579 <0x0 0x06910000 0x0 0x10000>,
3580 <0x0 0x069a0000 0x0 0x10000>;
3620 reg = <0x0 0x06a00000 0x0 0x10000>,
3621 <0x0 0x06a10000 0x0 0x10000>,
3622 <0x0 0x06aa0000 0x0 0x10000>;
3662 reg = <0x0 0x06b00000 0x0 0x10000>,
3663 <0x0 0x06b10000 0x0 0x10000>,
3664 <0x0 0x06ba0000 0x0 0x10000>;
3696 reg = <0x0 0x8000000 0x0 0x1000000>,
3697 <0x0 0x7000000 0x0 0x1000000>;
3828 stream-match-mask = <0x7f80>;
3838 reg = <0x0 0xb600000 0x0 0x40000>;
3845 reg = <0x0 0xbe00000 0x0 0x40000>;
3852 reg = <0x0 0x0c150000 0x0 0x90000>;
3858 * Shared interrupt 0 is routed only to AON/SPE, so
3867 reg = <0x0 0xc1e0000 0x0 0x10000>;
3876 reg = <0x0 0xc240000 0x0 0x100>;
3879 #size-cells = <0>;
3895 reg = <0x0 0xc250000 0x0 0x100>;
3898 #size-cells = <0>;
3908 dmas = <&gpcdma 0>, <&gpcdma 0>;
3914 reg = <0x0 0x0c260000 0x0 0x1000>;
3917 #size-cells = <0>;
3933 reg = <0x0 0x0c2a0000 0x0 0x10000>;
3944 reg = <0x0 0x0c2f0000 0x0 0x1000>,
3945 <0x0 0x0c2f1000 0x0 0x1000>;
3954 gpio-ranges = <&pinmux_aon 0 0 32>;
3959 reg = <0x0 0xc300000 0x0 0x4000>;
3964 reg = <0x0 0xc340000 0x0 0x10000>;
3974 reg = <0x0 0x0c360000 0x0 0x10000>,
3975 <0x0 0x0c370000 0x0 0x10000>,
3976 <0x0 0x0c380000 0x0 0x10000>,
3977 <0x0 0x0c390000 0x0 0x10000>,
3978 <0x0 0x0c3a0000 0x0 0x10000>;
4007 reg = <0x0 0xc600000 0x0 0x40000>;
4014 reg = <0x0 0xd600000 0x0 0x40000>;
4021 reg = <0x0 0xde00000 0x0 0x40000>;
4028 reg = <0x0 0x0e000000 0x0 0x5ffff>;
4035 reg = <0x0 0x0f400000 0x0 0x010000>, /* GICD */
4036 <0x0 0x0f440000 0x0 0x200000>; /* GICR */
4044 #address-cells = <0>;
4049 reg = <0x0 0x10000000 0x0 0x1000000>;
4179 stream-match-mask = <0x7f80>;
4189 reg = <0x0 0x12000000 0x0 0x1000000>,
4190 <0x0 0x11000000 0x0 0x1000000>;
4321 stream-match-mask = <0x7f80>;
4331 reg = <0x0 0x13a00000 0x0 0x400000>;
4338 reg = <0x0 0x13e00000 0x0 0x10000>,
4339 <0x0 0x13e10000 0x0 0x10000>,
4340 <0x0 0x13e40000 0x0 0x10000>;
4358 ranges = <0x0 0x14800000 0x0 0x14800000 0x0 0x02000000>;
4366 iommu-map = <0 &smmu_niso0 TEGRA234_SID_HOST1X_CTX0 1>,
4385 reg = <0x0 0x15340000 0x0 0x00040000>;
4402 reg = <0x0 0x15480000 0x0 0x00040000>;
4422 nvidia,bl-manifest-offset = <0>;
4423 nvidia,bl-data-offset = <0>;
4424 nvidia,bl-code-offset = <0>;
4425 nvidia,os-manifest-offset = <0>;
4426 nvidia,os-data-offset = <0>;
4427 nvidia,os-code-offset = <0>;
4438 reg = <0x00 0x15820000 0x00 0x10000>;
4446 reg = <0x00 0x15840000 0x00 0x10000>;
4456 reg = <0x00 0x140a0000 0x0 0x00020000>, /* appl registers (128K) */
4457 <0x00 0x2a000000 0x0 0x00040000>, /* configuration space (256K) */
4458 <0x00 0x2a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
4459 <0x00 0x2a080000 0x0 0x00040000>, /* DBI reg space (256K) */
4460 <0x35 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
4482 interrupt-map-mask = <0 0 0 0>;
4483 interrupt-map = <0 0 0 0 &gic GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
4491 bus-range = <0x0 0xff>;
4493 …ranges = <0x43000000 0x32 0x40000000 0x32 0x40000000 0x2 0xe8000000>, /* prefetchable memory (1190…
4494 …<0x02000000 0x0 0x40000000 0x35 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
4495 <0x01000000 0x0 0x2a100000 0x00 0x2a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
4500 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE8 0x1000>;
4501 iommu-map-mask = <0x0>;
4510 reg = <0x00 0x140c0000 0x0 0x00020000>, /* appl registers (128K) */
4511 <0x00 0x2c000000 0x0 0x00040000>, /* configuration space (256K) */
4512 <0x00 0x2c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
4513 <0x00 0x2c080000 0x0 0x00040000>, /* DBI reg space (256K) */
4514 <0x38 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
4536 interrupt-map-mask = <0 0 0 0>;
4537 interrupt-map = <0 0 0 0 &gic GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
4545 bus-range = <0x0 0xff>;
4547 …ranges = <0x43000000 0x35 0x40000000 0x35 0x40000000 0x2 0xc0000000>, /* prefetchable memory (1126…
4548 …<0x02000000 0x0 0x40000000 0x38 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
4549 <0x01000000 0x0 0x2c100000 0x00 0x2c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
4554 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE9 0x1000>;
4555 iommu-map-mask = <0x0>;
4564 reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */
4565 <0x00 0x2e000000 0x0 0x00040000>, /* configuration space (256K) */
4566 <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
4567 <0x00 0x2e080000 0x0 0x00040000>, /* DBI reg space (256K) */
4568 <0x3b 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
4590 interrupt-map-mask = <0 0 0 0>;
4591 interrupt-map = <0 0 0 0 &gic GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
4599 bus-range = <0x0 0xff>;
4601 …ranges = <0x43000000 0x38 0x40000000 0x38 0x40000000 0x2 0xe8000000>, /* prefetchable memory (1190…
4602 …<0x02000000 0x0 0x40000000 0x3b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
4603 <0x01000000 0x0 0x2e100000 0x00 0x2e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
4608 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>;
4609 iommu-map-mask = <0x0>;
4618 reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */
4619 <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
4620 <0x00 0x2e080000 0x0 0x00040000>, /* DBI space (256K) */
4621 <0x38 0x40000000 0x3 0x00000000>; /* Address Space (12G) */
4646 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>;
4647 iommu-map-mask = <0x0>;
4656 reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */
4657 <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */
4658 <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
4659 <0x00 0x30080000 0x0 0x00040000>, /* DBI reg space (256K) */
4660 <0x20 0xb0000000 0x0 0x10000000>; /* ECAM (256MB) */
4682 interrupt-map-mask = <0 0 0 0>;
4683 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
4691 bus-range = <0x0 0xff>;
4693 …ranges = <0x43000000 0x20 0x80000000 0x20 0x80000000 0x0 0x28000000>, /* prefetchable memory (640 …
4694 …<0x02000000 0x0 0x40000000 0x20 0xa8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
4695 <0x01000000 0x0 0x30100000 0x00 0x30100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
4700 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE1 0x1000>;
4701 iommu-map-mask = <0x0>;
4710 reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */
4711 <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */
4712 <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
4713 <0x00 0x32080000 0x0 0x00040000>, /* DBI reg space (256K) */
4714 <0x20 0xf0000000 0x0 0x10000000>; /* ECAM (256MB) */
4736 interrupt-map-mask = <0 0 0 0>;
4737 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
4745 bus-range = <0x0 0xff>;
4747 …ranges = <0x43000000 0x20 0xc0000000 0x20 0xc0000000 0x0 0x28000000>, /* prefetchable memory (640 …
4748 …<0x02000000 0x0 0x40000000 0x20 0xe8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
4749 <0x01000000 0x0 0x32100000 0x00 0x32100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
4754 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE2 0x1000>;
4755 iommu-map-mask = <0x0>;
4764 reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */
4765 <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */
4766 <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
4767 <0x00 0x34080000 0x0 0x00040000>, /* DBI reg space (256K) */
4768 <0x21 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
4790 interrupt-map-mask = <0 0 0 0>;
4791 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
4799 bus-range = <0x0 0xff>;
4801 …ranges = <0x43000000 0x21 0x00000000 0x21 0x00000000 0x0 0x28000000>, /* prefetchable memory (640 …
4802 …<0x02000000 0x0 0x40000000 0x21 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
4803 <0x01000000 0x0 0x34100000 0x00 0x34100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
4808 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE3 0x1000>;
4809 iommu-map-mask = <0x0>;
4818 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */
4819 <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */
4820 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
4821 <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */
4822 <0x24 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
4844 interrupt-map-mask = <0 0 0 0>;
4845 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
4853 bus-range = <0x0 0xff>;
4855 …ranges = <0x43000000 0x21 0x40000000 0x21 0x40000000 0x2 0xe8000000>, /* prefetchable memory (1190…
4856 …<0x02000000 0x0 0x40000000 0x24 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
4857 <0x01000000 0x0 0x36100000 0x00 0x36100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
4862 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE4 0x1000>;
4863 iommu-map-mask = <0x0>;
4872 reg = <0x00 0x14160000 0x0 0x00020000 /* appl registers (128K) */
4873 0x00 0x36040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
4874 0x00 0x36080000 0x0 0x00040000 /* DBI space (256K) */
4875 0x21 0x40000000 0x3 0x00000000>; /* Address Space (12G) */
4903 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */
4904 <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */
4905 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
4906 <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */
4907 <0x27 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
4915 linux,pci-domain = <0>;
4929 interrupt-map-mask = <0 0 0 0>;
4930 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
4932 nvidia,bpmp = <&bpmp 0>;
4938 bus-range = <0x0 0xff>;
4940 …ranges = <0x43000000 0x24 0x40000000 0x24 0x40000000 0x2 0xe8000000>, /* prefetchable memory (1190…
4941 …<0x02000000 0x0 0x40000000 0x27 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
4942 <0x01000000 0x0 0x38100000 0x00 0x38100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
4947 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE0 0x1000>;
4948 iommu-map-mask = <0x0>;
4957 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */
4958 <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */
4959 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
4960 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */
4961 <0x2b 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
4983 interrupt-map-mask = <0 0 0 0>;
4984 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
4992 bus-range = <0x0 0xff>;
4994 …ranges = <0x43000000 0x28 0x00000000 0x28 0x00000000 0x3 0x28000000>, /* prefetchable memory (1292…
4995 …<0x02000000 0x0 0x40000000 0x2b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
4996 <0x01000000 0x0 0x3a100000 0x00 0x3a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
5001 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>;
5002 iommu-map-mask = <0x0>;
5011 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */
5012 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
5013 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */
5014 <0x27 0x40000000 0x4 0x00000000>; /* Address Space (16G) */
5039 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>;
5040 iommu-map-mask = <0x0>;
5049 reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K) */
5050 <0x00 0x3c000000 0x0 0x00040000>, /* configuration space (256K) */
5051 <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
5052 <0x00 0x3c080000 0x0 0x00040000>, /* DBI reg space (256K) */
5053 <0x2e 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
5075 interrupt-map-mask = <0 0 0 0>;
5076 interrupt-map = <0 0 0 0 &gic GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
5084 bus-range = <0x0 0xff>;
5086 …ranges = <0x43000000 0x2b 0x40000000 0x2b 0x40000000 0x2 0xe8000000>, /* prefetchable memory (1190…
5087 …<0x02000000 0x0 0x40000000 0x2e 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
5088 <0x01000000 0x0 0x3c100000 0x00 0x3c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
5093 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>;
5094 iommu-map-mask = <0x0>;
5103 reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K) */
5104 <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
5105 <0x00 0x3c080000 0x0 0x00040000>, /* DBI space (256K) */
5106 <0x2b 0x40000000 0x3 0x00000000>; /* Address Space (12G) */
5131 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>;
5132 iommu-map-mask = <0x0>;
5141 reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K) */
5142 <0x00 0x3e000000 0x0 0x00040000>, /* configuration space (256K) */
5143 <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
5144 <0x00 0x3e080000 0x0 0x00040000>, /* DBI reg space (256K) */
5145 <0x32 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
5167 interrupt-map-mask = <0 0 0 0>;
5168 interrupt-map = <0 0 0 0 &gic GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
5176 bus-range = <0x0 0xff>;
5178 …ranges = <0x43000000 0x30 0x00000000 0x30 0x00000000 0x2 0x28000000>, /* prefetchable memory (8832…
5179 …<0x02000000 0x0 0x40000000 0x32 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
5180 <0x01000000 0x0 0x3e100000 0x00 0x3e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
5185 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>;
5186 iommu-map-mask = <0x0>;
5195 reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K) */
5196 <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
5197 <0x00 0x3e080000 0x0 0x00040000>, /* DBI space (256K) */
5198 <0x2e 0x40000000 0x4 0x00000000>; /* Address Space (16G) */
5223 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>;
5224 iommu-map-mask = <0x0>;
5233 reg = <0x0 0x40000000 0x0 0x80000>;
5237 ranges = <0x0 0x0 0x40000000 0x80000>;
5242 reg = <0x70000 0x1000>;
5248 reg = <0x71000 0x1000>;
5273 #size-cells = <0>;
5284 #size-cells = <0>;
5286 cpu0_0: cpu@0 {
5289 reg = <0x00000>;
5308 reg = <0x00100>;
5327 reg = <0x00200>;
5346 reg = <0x00300>;
5365 reg = <0x10000>;
5384 reg = <0x10100>;
5403 reg = <0x10200>;
5422 reg = <0x10300>;
5441 reg = <0x20000>;
5460 reg = <0x20100>;
5479 reg = <0x20200>;
5498 reg = <0x20300>;
5750 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>,
5765 assigned-clock-parents = <0>,