Home
last modified time | relevance | path

Searched +full:0 +full:x02200000 (Results 1 – 14 of 14) sorted by relevance

/freebsd/sys/contrib/device-tree/Bindings/ata/
H A Dimx-sata.txt31 reg = <0x02200000 0x4000>;
32 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
H A Dimx-sata.yaml124 reg = <0x02200000 0x4000>;
125 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx6ull.dtsi58 reg = <0x02200000 0x100000>;
63 reg = <0x02280000 0x4000>;
73 reg = <0x02284000 0x4000>;
80 reg = <0x02290000 0x4000>;
86 reg = <0x02288000 0x4000>;
H A Dimx6q.dtsi17 #size-cells = <0>;
19 cpu0: cpu@0 {
22 reg = <0>;
165 reg = <0x00900000 0x40000>;
166 ranges = <0 0x00900000 0x40000>;
176 #size-cells = <0>;
178 reg = <0x02018000 0x4000>;
179 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
192 reg = <0x02200000 0x4000>;
193 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
[all …]
H A Dimx6sl.dtsi51 #size-cells = <0>;
53 cpu0: cpu@0 {
56 reg = <0x0>;
86 #clock-cells = <0>;
92 #clock-cells = <0>;
100 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
105 #phy-cells = <0>;
117 reg = <0x00900000 0x20000>;
118 ranges = <0 0x00900000 0x20000>;
128 reg = <0x00a01000 0x1000>,
[all …]
H A Dimx6sx.dtsi61 #size-cells = <0>;
63 cpu0: cpu@0 {
66 reg = <0>;
100 #clock-cells = <0>;
107 #clock-cells = <0>;
114 #clock-cells = <0>;
115 clock-frequency = <0>;
121 #clock-cells = <0>;
122 clock-frequency = <0>;
128 #clock-cells = <0>;
[all …]
/freebsd/sys/contrib/dev/mediatek/mt76/mt7915/
H A Dcoredump.c16 .start = 0xe003b400,
17 .len = 0x00003bff,
24 .start = 0x00800000,
25 .len = 0x0005ffff,
29 .start = 0x00900000,
30 .len = 0x00013fff,
34 .start = 0x02200000,
35 .len = 0x0004ffff,
39 .start = 0x02300000,
40 .len = 0x0004ffff,
[all …]
/freebsd/sys/contrib/dev/mediatek/mt76/mt7996/
H A Dcoredump.c16 .start = 0x00800000,
17 .len = 0x0004ffff,
21 .start = 0x00900000,
22 .len = 0x00037fff,
26 .start = 0x02200000,
27 .len = 0x0003ffff,
31 .start = 0x00400000,
32 .len = 0x00067fff,
36 .start = 0xe0000000,
37 .len = 0x0015ffff,
[all …]
/freebsd/sys/dev/qlnx/qlnxe/
H A Dmcp_public.h51 #define OFFSIZE_OFFSET_OFFSET 0
52 #define OFFSIZE_OFFSET_MASK 0x0000ffff
55 #define OFFSIZE_SIZE_MASK 0xffff0000
70 u32 speed; /* 0 = autoneg, 1000/10000/20000/25000/40000/50000/100000 */
71 #define ETH_SPEED_AUTONEG 0
72 #define ETH_SPEED_SMARTLINQ 0x8 /* deprecated - use link_modes field instead */
75 #define ETH_PAUSE_NONE 0x0
76 #define ETH_PAUSE_AUTONEG 0x1
77 #define ETH_PAUSE_RX 0x2
78 #define ETH_PAUSE_TX 0x4
[all …]
H A Decore_dbg_values.h34 0x02, 0x00, 0x04, 0x00, 0x01, 0x09, 0x01, 0x08, 0x07, 0x02, 0x00, 0x01,
35 0x04, 0x05, 0x00, 0x01, 0x07, 0x09, 0x02, 0x00, 0x01, 0x04, 0x12, 0x00,
36 0x00, 0x06, 0x02, 0x00, 0x01, 0x04, 0x05, 0x00, 0x00, 0x06, 0x02, 0x00,
37 0x01, 0x05, 0x12, 0x00, 0x00, 0x06, 0x02, 0x00, 0x04, 0x00, 0x01, 0x09,
38 0x00, 0x06, 0x02, 0x00, 0x04, 0x02, 0x00, 0x0b, 0x0e, 0x00, 0x01, 0x00,
39 0x06, 0x01, 0x04, 0x05, 0x02, 0x00, 0x12, 0x00, 0x01, 0x07, 0x09, 0x02,
40 0x00, 0x04, 0x00, 0x01, 0x08, 0x07, 0x02, 0x00, 0x04, 0x00, 0x01, 0x07,
41 0x09, 0x02, 0x00, 0x04, 0x02, 0x00, 0x0b, 0x10, 0x02, 0x00, 0x04, 0x02,
42 0x00, 0x0b, 0x0f, 0x02, 0x04, 0x00, 0x01, 0x07, 0x09, 0x02, 0x00, 0x04,
43 0x02, 0x0b, 0x0e, 0x02, 0x00, 0x04, 0x00, 0x00, 0x06, 0x02, 0x04, 0x02,
[all …]
H A Decore_init_values.h35 0x00030003, 0xffff0000, /* if phase != 'engine', skip 3 ops (no DMAE) */
36 0x00020002, 0x00020000, /* if mode != '!asic', skip 2 ops */
37 0x0280c201, 0x00000000, /* write 0x0 to address 0x50184 */
38 0x02810201, 0x00000000, /* write 0x0 to address 0x50204 */
40 0x00110003, 0xffff0000, /* if phase != 'engine', skip 17 ops (no DMAE) */
41 0x00030002, 0x00020000, /* if mode != '!asic', skip 3 ops */
42 0x0048c201, 0x00000000, /* write 0x0 to address 0x9184 */
43 0x0048d201, 0x00000000, /* write 0x0 to address 0x91a4 */
44 0x004ba601, 0x00000001, /* write 0x1 to address 0x974c */
45 0x00020002, 0x00be0000, /* if mode != '(!asic)&bb', skip 2 ops */
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/nvidia/
H A Dtegra234.dtsi19 bus@0 {
24 ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
28 reg = <0x0 0x00100000 0x0 0xf000>,
29 <0x0 0x0010f000 0x0 0x1000>;
35 reg = <0x0 0x02080000 0x0 0x00121000>;
36 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
58 reg = <0x0 0x02200000 0x0 0x10000>,
59 <0x0 0x02210000 0x0 0x10000>;
112 gpio-ranges = <&pinmux 0 0 164>;
117 reg = <0x0 0x2430000 0x0 0x19100>;
[all …]
/freebsd/contrib/llvm-project/lldb/source/Plugins/Instruction/ARM/
H A DEmulateInstructionARM.cpp3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
39 #define AlignPC(pc_val) (pc_val & 0xFFFFFFFC) in LLDB_PLUGIN_DEFINE_ADV()
47 ::memset(&reg_info, 0, sizeof(RegisterInfo)); in LLDB_PLUGIN_DEFINE_ADV()
234 // FPA Registers 0-7 in LLDB_PLUGIN_DEFINE_ADV()
260 // Intel wireless MMX general purpose registers 0 - 7 XScale accumulator in LLDB_PLUGIN_DEFINE_ADV()
261 // register 0 - 7 (they do overlap with wCGR0 - wCGR7) in LLDB_PLUGIN_DEFINE_ADV()
287 // Intel wireless MMX data registers 0 - 15 in LLDB_PLUGIN_DEFINE_ADV()
423 // Intel wireless MMX control register in co-processor 0 - 7 in LLDB_PLUGIN_DEFINE_ADV()
604 // Valid return values are {1, 2, 3, 4}, with 0 signifying an error condition.
609 return 0; in CountITSize()
[all …]
/freebsd/tools/test/iconv/ref/
H A DUTF-32BE-rev1 0x00 = 0x00000000
2 0x01 = 0x01000000
3 0x02 = 0x02000000
4 0x03 = 0x03000000
5 0x04 = 0x04000000
6 0x05 = 0x05000000
7 0x06 = 0x06000000
8 0x07 = 0x07000000
9 0x08 = 0x08000000
10 0x09 = 0x09000000
[all …]