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/linux/arch/arm64/boot/dts/freescale/
H A Dimx93-pinfunc.h13 #define MX93_PAD_DAP_TDI__JTAG_MUX_TDI 0x0000 0x01B0 0x03D8 0x0 0x0
14 #define MX93_PAD_DAP_TDI__MQS2_LEFT 0x0000 0x01B0 0x0000 0x1 0x0
15 #define MX93_PAD_DAP_TDI__CAN2_TX 0x0000 0x01B0 0x0000 0x3 0x0
16 #define MX93_PAD_DAP_TDI__FLEXIO2_FLEXIO30 0x0000 0x01B0 0x0000 0x4 0x0
17 #define MX93_PAD_DAP_TDI__GPIO3_IO28 0x0000 0x01B0 0x0000 0x5 0x0
18 #define MX93_PAD_DAP_TDI__LPUART5_RX 0x0000 0x01B0 0x0430 0x6 0x0
19 #define MX93_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x0004 0x01B4 0x03DC 0x0 0x0
20 #define MX93_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO31 0x0004 0x01B4 0x0000 0x4 0x0
21 #define MX93_PAD_DAP_TMS_SWDIO__GPIO3_IO29 0x0004 0x01B4 0x0000 0x5 0x0
22 #define MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x0004 0x01B4 0x0000 0x6 0x0
[all …]
H A Dimx95-pinfunc.h13 #define IMX95_PAD_DAP_TDI__JTAG_MUX_TDI 0x0000 0x0204 0x0610 0x00 0x00
14 #define IMX95_PAD_DAP_TDI__NETCMIX_TOP_MQS2_LEFT 0x0000 0x0204 0x0000 0x01 0x00
15 #define IMX95_PAD_DAP_TDI__NETCMIX_TOP_NETC_TMR_1588_ALARM1 0x0000 0x0204 0x0000 0x02 0x00
16 #define IMX95_PAD_DAP_TDI__CAN2_TX 0x0000 0x0204 0x0000 0x03 0x00
17 #define IMX95_PAD_DAP_TDI__FLEXIO2_FLEXIO_BIT30 0x0000 0x0204 0x0000 0x04 0x00
18 #define IMX95_PAD_DAP_TDI__GPIO3_IO_BIT28 0x0000 0x0204 0x0000 0x05 0x00
19 #define IMX95_PAD_DAP_TDI__LPUART5_RX 0x0000 0x0204 0x0570 0x06 0x00
21 #define IMX95_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x0004 0x0208 0x0614 0x00 0x00
22 #define IMX95_PAD_DAP_TMS_SWDIO__CAN4_TX 0x0004 0x0208 0x0000 0x02 0x00
23 #define IMX95_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO_BIT31 0x0004 0x0208 0x0000 0x04 0x00
[all …]
/linux/arch/arm64/boot/dts/ti/
H A Dk3-am642-phyboard-electra-x27-gpio1-spi1-uart3.dtso25 AM64X_IOPAD(0x0220, PIN_INPUT, 7) /* (D14) SPI1_CS1.GPIO1_48 */
31 AM64X_IOPAD(0x0224, PIN_INPUT, 0) /* (C14) SPI1_CLK */
32 AM64X_IOPAD(0x021c, PIN_OUTPUT, 0) /* (B14) SPI1_CS0 */
33 AM64X_IOPAD(0x0228, PIN_OUTPUT, 0) /* (B15) SPI1_D0 */
34 AM64X_IOPAD(0x022c, PIN_INPUT, 0) /* (A15) SPI1_D1 */
40 AM64X_IOPAD(0x0048, PIN_INPUT, 2) /* (U20) GPMC0_AD3.UART3_RXD */
41 AM64X_IOPAD(0x004c, PIN_OUTPUT, 2) /* (U18) GPMC0_AD4.UART3_TXD */
48 pinctrl-0 = <&main_gpio1_exp_header_gpio_pins_default>;
54 pinctrl-0 = <&main_spi1_pins_default>;
61 pinctrl-0 = <&main_uart3_pins_default>;
/linux/arch/arm/mach-pxa/
H A Dpxa320.c26 MFP_ADDR_X(GPIO0, GPIO4, 0x0124),
27 MFP_ADDR_X(GPIO5, GPIO9, 0x028C),
28 MFP_ADDR(GPIO10, 0x0458),
29 MFP_ADDR_X(GPIO11, GPIO26, 0x02A0),
30 MFP_ADDR_X(GPIO27, GPIO48, 0x0400),
31 MFP_ADDR_X(GPIO49, GPIO62, 0x045C),
32 MFP_ADDR_X(GPIO63, GPIO73, 0x04B4),
33 MFP_ADDR_X(GPIO74, GPIO98, 0x04F0),
34 MFP_ADDR_X(GPIO99, GPIO127, 0x0600),
35 MFP_ADDR_X(GPIO0_2, GPIO5_2, 0x0674),
[all …]
H A Dpxa300.c26 MFP_ADDR_X(GPIO0, GPIO2, 0x00b4),
27 MFP_ADDR_X(GPIO3, GPIO26, 0x027c),
28 MFP_ADDR_X(GPIO27, GPIO98, 0x0400),
29 MFP_ADDR_X(GPIO99, GPIO127, 0x0600),
30 MFP_ADDR_X(GPIO0_2, GPIO1_2, 0x0674),
31 MFP_ADDR_X(GPIO2_2, GPIO6_2, 0x02dc),
33 MFP_ADDR(nBE0, 0x0204),
34 MFP_ADDR(nBE1, 0x0208),
36 MFP_ADDR(nLUA, 0x0244),
37 MFP_ADDR(nLLA, 0x0254),
[all …]
/linux/drivers/gpu/drm/arm/
H A Dhdlcd_regs.h15 #define HDLCD_REG_VERSION 0x0000 /* ro */
16 #define HDLCD_REG_INT_RAWSTAT 0x0010 /* rw */
17 #define HDLCD_REG_INT_CLEAR 0x0014 /* wo */
18 #define HDLCD_REG_INT_MASK 0x0018 /* rw */
19 #define HDLCD_REG_INT_STATUS 0x001c /* ro */
20 #define HDLCD_REG_FB_BASE 0x0100 /* rw */
21 #define HDLCD_REG_FB_LINE_LENGTH 0x0104 /* rw */
22 #define HDLCD_REG_FB_LINE_COUNT 0x0108 /* rw */
23 #define HDLCD_REG_FB_LINE_PITCH 0x010c /* rw */
24 #define HDLCD_REG_BUS_OPTIONS 0x0110 /* rw */
[all …]
/linux/Documentation/devicetree/bindings/clock/ti/
H A Dti,apll-clock.yaml30 const: 0
71 #size-cells = <0>;
74 #clock-cells = <0>;
77 reg = <0x021c>, <0x0220>;
81 #clock-cells = <0>;
87 reg = <0x0500>, <0x0530>, <0x0520>;
/linux/drivers/media/i2c/
H A Dalvium-csi2.h29 #define REG_BCRM_MINOR_VERSION_R CCI_REG16(0x0000)
30 #define REG_BCRM_MAJOR_VERSION_R CCI_REG16(0x0002)
31 #define REG_BCRM_REG_ADDR_R CCI_REG16(0x0014)
33 #define REG_BCRM_FEATURE_INQUIRY_R REG_BCRM_V4L2_64BIT(0x0008)
34 #define REG_BCRM_DEVICE_FW REG_BCRM_V4L2_64BIT(0x0010)
35 #define REG_BCRM_WRITE_HANDSHAKE_RW REG_BCRM_V4L2_8BIT(0x0018)
38 #define REG_BCRM_SUPPORTED_CSI2_LANE_COUNTS_R REG_BCRM_V4L2_8BIT(0x0040)
39 #define REG_BCRM_CSI2_LANE_COUNT_RW REG_BCRM_V4L2_8BIT(0x0044)
40 #define REG_BCRM_CSI2_CLOCK_MIN_R REG_BCRM_V4L2_32BIT(0x0048)
41 #define REG_BCRM_CSI2_CLOCK_MAX_R REG_BCRM_V4L2_32BIT(0x004c)
[all …]
/linux/drivers/hwtracing/intel_th/
H A Dmsu.h12 REG_MSU_MSUPARAMS = 0x0000,
13 REG_MSU_MSUSTS = 0x0008,
14 REG_MSU_MINTCTL = 0x0004, /* MSU-global interrupt control */
15 REG_MSU_MSC0CTL = 0x0100, /* MSC0 control */
16 REG_MSU_MSC0STS = 0x0104, /* MSC0 status */
17 REG_MSU_MSC0BAR = 0x0108, /* MSC0 output base address */
18 REG_MSU_MSC0SIZE = 0x010c, /* MSC0 output size */
19 REG_MSU_MSC0MWP = 0x0110, /* MSC0 write pointer */
20 REG_MSU_MSC0NWSA = 0x011c, /* MSC0 next window start address */
22 REG_MSU_MSC1CTL = 0x0200, /* MSC1 control */
[all …]
/linux/drivers/gpu/drm/nouveau/include/nvhw/class/
H A Dcl5039.h26 …_SET_OBJECT 0x0000
27 …_SET_OBJECT_POINTER 15:0
29 …_NO_OPERATION 0x0100
30 …_NO_OPERATION_V 31:0
32 …_SET_CONTEXT_DMA_NOTIFY 0x0180
33 …_SET_CONTEXT_DMA_NOTIFY_HANDLE 31:0
35 …_SET_CONTEXT_DMA_BUFFER_IN 0x0184
36 …_SET_CONTEXT_DMA_BUFFER_IN_HANDLE 31:0
38 …_SET_CONTEXT_DMA_BUFFER_OUT 0x0188
39 …_SET_CONTEXT_DMA_BUFFER_OUT_HANDLE 31:0
[all …]
/linux/drivers/clk/mediatek/
H A Dclk-mt7986-apmixed.c42 PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x0, PLL_AO, 32,
43 0x0200, 4, 0, 0x0204, 0),
44 PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0210, 0x021C, 0x0, 0, 32,
45 0x0210, 4, 0, 0x0214, 0),
46 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0220, 0x022C, 0x0, 0, 32,
47 0x0220, 4, 0, 0x0224, 0),
48 PLL(CLK_APMIXED_SGMPLL, "sgmpll", 0x0230, 0x023c, 0x0, 0, 32,
49 0x0230, 4, 0, 0x0234, 0),
50 PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0240, 0x024c, 0x0, 0,
51 32, 0x0240, 4, 0, 0x0244, 0),
[all …]
H A Dclk-mt7981-apmixed.c44 PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x00000001, PLL_AO,
45 32, 0x0200, 4, 0, 0x0204, 0),
46 PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0210, 0x021C, 0x00000001, 0, 32,
47 0x0210, 4, 0, 0x0214, 0),
48 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0220, 0x022C, 0x00000001, 0, 32,
49 0x0220, 4, 0, 0x0224, 0),
50 PLL(CLK_APMIXED_SGMPLL, "sgmpll", 0x0230, 0x023C, 0x00000001, 0, 32,
51 0x0230, 4, 0, 0x0234, 0),
52 PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0240, 0x024C, 0x00000001, 0, 32,
53 0x0240, 4, 0, 0x0244, 0),
[all …]
/linux/drivers/net/wireless/broadcom/b43/
H A Dtables_phy_lcn.c30 0x014d, 0x014d, 0x014d, 0x014d, 0x014d, 0x014d,
31 0x014d, 0x014d, 0x014d, 0x014d, 0x014d, 0x014d,
32 0x014d, 0x014d, 0x014d, 0x014d, 0x014d, 0x014d,
33 0x014d, 0x014d, 0x014d, 0x014d, 0x014d, 0x014d,
34 0x014d, 0x014d, 0x014d, 0x014d, 0x014d, 0x014d,
35 0x014d, 0x014d, 0x014d, 0x014d, 0x014d, 0x014d,
36 0x014d, 0x014d, 0x014d, 0x014d, 0x014d, 0x014d,
37 0x014d, 0x014d, 0x014d, 0x014d, 0x014d, 0x014d,
38 0x014d, 0x014d, 0x014d, 0x014d, 0x014d, 0x014d,
39 0x014d, 0x014d, 0x014d, 0x014d, 0x014d, 0x014d,
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Domap24xx-clocks.dtsi9 #clock-cells = <0>;
13 reg = <0x4>;
17 #clock-cells = <0>;
23 #clock-cells = <0>;
27 reg = <0x4>;
31 #clock-cells = <0>;
39 #clock-cells = <0>;
45 #clock-cells = <0>;
51 #clock-cells = <0>;
57 #clock-cells = <0>;
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6sll-pinfunc.h15 #define MX6SLL_PAD_WDOG_B__WDOG1_B 0x0014 0x02DC 0x0000 0x0 0x0
16 #define MX6SLL_PAD_WDOG_B__WDOG1_RESET_B_DEB 0x0014 0x02DC 0x0000 0x1 0x0
17 #define MX6SLL_PAD_WDOG_B__UART5_RI_B 0x0014 0x02DC 0x0000 0x2 0x0
18 #define MX6SLL_PAD_WDOG_B__GPIO3_IO18 0x0014 0x02DC 0x0000 0x5 0x0
19 #define MX6SLL_PAD_REF_CLK_24M__XTALOSC_REF_CLK_24M 0x0018 0x02E0 0x0000 0x0 0x0
20 #define MX6SLL_PAD_REF_CLK_24M__I2C3_SCL 0x0018 0x02E0 0x068C 0x1 0x0
21 #define MX6SLL_PAD_REF_CLK_24M__PWM3_OUT 0x0018 0x02E0 0x0000 0x2 0x0
22 #define MX6SLL_PAD_REF_CLK_24M__USB_OTG2_ID 0x0018 0x02E0 0x0560 0x3 0x0
23 #define MX6SLL_PAD_REF_CLK_24M__CCM_PMIC_READY 0x0018 0x02E0 0x05AC 0x4 0x0
24 #define MX6SLL_PAD_REF_CLK_24M__GPIO3_IO21 0x0018 0x02E0 0x0000 0x5 0x0
[all …]
H A Dimx7d-pinfunc.h14 #define MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x0000 0x0030 0x0000 0x0 0x0
15 #define MX7D_PAD_LPSR_GPIO1_IO00__PWM4_OUT 0x0000 0x0030 0x0000 0x1 0x0
16 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_ANY 0x0000 0x0030 0x0000 0x2 0x0
17 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x0000 0x0030 0x0000 0x3 0x0
18 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG__RST_B_DEB 0x0000 0x0030 0x0000 0x4 0x0
19 #define MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x0004 0x0034 0x0000 0x0 0x0
20 #define MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x0004 0x0034 0x0000 0x1 0x0
21 #define MX7D_PAD_LPSR_GPIO1_IO01__CCM_ENET_REF_CLK3 0x0004 0x0034 0x0000 0x2 0x0
22 #define MX7D_PAD_LPSR_GPIO1_IO01__SAI1_MCLK 0x0004 0x0034 0x0000 0x3 0x0
23 #define MX7D_PAD_LPSR_GPIO1_IO01__ANATOP_24M_OUT 0x0004 0x0034 0x0000 0x4 0x0
[all …]
/linux/drivers/gpu/drm/amd/display/dc/sspl/
H A Ddc_spl_isharp_filters.c21 0x03010000,
22 0x0F0B0805,
23 0x211E1813,
24 0x2B292624,
25 0x3533302E,
26 0x3E3C3A37,
27 0x46444240,
28 0x4D4B4A48,
29 0x5352504F,
30 0x59575655,
[all …]
/linux/include/linux/bcma/
H A Dbcma_driver_pcie2.h5 #define BCMA_CORE_PCIE2_CLK_CONTROL 0x0000
6 #define PCIE2_CLKC_RST_OE 0x0001 /* When set, drives PCI_RESET out to pin */
7 #define PCIE2_CLKC_RST 0x0002 /* Value driven out to pin */
8 #define PCIE2_CLKC_SPERST 0x0004 /* SurvivePeRst */
9 #define PCIE2_CLKC_DISABLE_L1CLK_GATING 0x0010
10 #define PCIE2_CLKC_DLYPERST 0x0100 /* Delay PeRst to CoE Core */
11 #define PCIE2_CLKC_DISSPROMLD 0x0200 /* DisableSpromLoadOnPerst */
12 #define PCIE2_CLKC_WAKE_MODE_L2 0x1000 /* Wake on L2 */
13 #define BCMA_CORE_PCIE2_RC_PM_CONTROL 0x0004
14 #define BCMA_CORE_PCIE2_RC_PM_STATUS 0x0008
[all …]
/linux/drivers/media/rc/keymaps/
H A Drc-avermedia-m135a.c23 { 0x0200, KEY_POWER2 },
24 { 0x022e, KEY_DOT }, /* '.' */
25 { 0x0201, KEY_MODE }, /* TV/FM or SOURCE */
27 { 0x0205, KEY_NUMERIC_1 },
28 { 0x0206, KEY_NUMERIC_2 },
29 { 0x0207, KEY_NUMERIC_3 },
30 { 0x0209, KEY_NUMERIC_4 },
31 { 0x020a, KEY_NUMERIC_5 },
32 { 0x020b, KEY_NUMERIC_6 },
33 { 0x020d, KEY_NUMERIC_7 },
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/nbio/
H A Dnbio_7_0_offset.h27 // base address: 0x0
28 …NB_NBCFG0_NB_VENDOR_ID 0x0000
29 …NB_NBCFG0_NB_DEVICE_ID 0x0002
30 …NB_NBCFG0_NB_COMMAND 0x0004
31 …NB_NBCFG0_NB_STATUS 0x0006
32 …NB_NBCFG0_NB_REVISION_ID 0x0008
33 …NB_NBCFG0_NB_REGPROG_INF 0x0009
34 …NB_NBCFG0_NB_SUB_CLASS 0x000a
35 …NB_NBCFG0_NB_BASE_CODE 0x000b
36 …NB_NBCFG0_NB_CACHE_LINE 0x000c
[all …]
/linux/drivers/net/can/spi/mcp251xfd/
H A Dmcp251xfd-crc16.c24 0x0000, 0x8005, 0x800f, 0x000a, 0x801b, 0x001e, 0x0014, 0x8011,
25 0x8033, 0x0036, 0x003c, 0x8039, 0x0028, 0x802d, 0x8027, 0x0022,
26 0x8063, 0x0066, 0x006c, 0x8069, 0x0078, 0x807d, 0x8077, 0x0072,
27 0x0050, 0x8055, 0x805f, 0x005a, 0x804b, 0x004e, 0x0044, 0x8041,
28 0x80c3, 0x00c6, 0x00cc, 0x80c9, 0x00d8, 0x80dd, 0x80d7, 0x00d2,
29 0x00f0, 0x80f5, 0x80ff, 0x00fa, 0x80eb, 0x00ee, 0x00e4, 0x80e1,
30 0x00a0, 0x80a5, 0x80af, 0x00aa, 0x80bb, 0x00be, 0x00b4, 0x80b1,
31 0x8093, 0x0096, 0x009c, 0x8099, 0x0088, 0x808d, 0x8087, 0x0082,
32 0x8183, 0x0186, 0x018c, 0x8189, 0x0198, 0x819d, 0x8197, 0x0192,
33 0x01b0, 0x81b5, 0x81bf, 0x01ba, 0x81ab, 0x01ae, 0x01a4, 0x81a1,
[all …]
/linux/sound/soc/sof/mediatek/mt8195/
H A Dmt8195.h15 #define DSP_REG_BASE 0x10803000
16 #define SCP_CFGREG_BASE 0x10724000
17 #define DSP_SYSAO_BASE 0x1080C000
22 #define DSP_JTAGMUX 0x0000
23 #define DSP_ALTRESETVEC 0x0004
24 #define DSP_PDEBUGDATA 0x0008
25 #define DSP_PDEBUGBUS0 0x000c
26 #define PDEBUG_ENABLE BIT(0)
27 #define DSP_PDEBUGBUS1 0x0010
28 #define DSP_PDEBUGINST 0x0014
[all …]
/linux/sound/firewire/tascam/
H A Dtascam.h102 #define TSCM_ADDR_BASE 0xffff00000000ull
104 #define TSCM_OFFSET_FIRMWARE_REGISTER 0x0000
105 #define TSCM_OFFSET_FIRMWARE_FPGA 0x0004
106 #define TSCM_OFFSET_FIRMWARE_ARM 0x0008
107 #define TSCM_OFFSET_FIRMWARE_HW 0x000c
109 #define TSCM_OFFSET_ISOC_TX_CH 0x0200
110 #define TSCM_OFFSET_UNKNOWN 0x0204
111 #define TSCM_OFFSET_START_STREAMING 0x0208
112 #define TSCM_OFFSET_ISOC_RX_CH 0x020c
113 #define TSCM_OFFSET_ISOC_RX_ON 0x0210 /* Little conviction. */
[all …]
/linux/drivers/media/dvb-frontends/
H A Dau8522_dig.c25 } while (0)
34 { 0, 270 },
68 { 15, 0 },
149 { 15, 0 },
221 for (i = 0; i < sz; i++) { in au8522_mse2snr_lookup()
224 ret = 0; in au8522_mse2snr_lookup()
241 r0b5 = 0x00; in au8522_set_if()
242 r0b6 = 0x3d; in au8522_set_if()
243 r0b7 = 0xa0; in au8522_set_if()
247 r0b5 = 0x00; in au8522_set_if()
[all …]
/linux/drivers/bluetooth/
H A Dath3k.c20 #define ATH3K_DNLOAD 0x01
21 #define ATH3K_GETSTATE 0x05
22 #define ATH3K_SET_NORMAL_MODE 0x07
23 #define ATH3K_GETVERSION 0x09
24 #define USB_REG_SWITCH_VID_PID 0x0a
26 #define ATH3K_MODE_MASK 0x3F
27 #define ATH3K_NORMAL_MODE 0x0E
29 #define ATH3K_PATCH_UPDATE 0x80
30 #define ATH3K_SYSCFG_UPDATE 0x40
32 #define ATH3K_XTAL_FREQ_26M 0x00
[all …]

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