Searched +full:0 +full:x021b8000 (Results 1 – 6 of 6) sorted by relevance
25 <cs-number> 0 <physical address of mapping> <size>32 register, e.g. IOMUXC_GPR1 on i.MX6Q. IOMUXC_GPR1[11:0]36 IOMUXC_GPR1[11:0] CS0 CS1 CS2 CS338 05 128M 0M 0M 0M39 033 64M 64M 0M 0M40 0113 64M 32M 32M 0M44 what bootloader sets up in IOMUXC_GPR1[11:0] will be75 reg = <0x021b8000 0x4000>;79 ranges = <0 0 0x08000000 0x08000000>;82 nor@0,0 {[all …]
21 pattern: "^memory-controller@[0-9a-f]+$"63 WEIM CS GPR register, e.g. IOMUXC_GPR1 on i.MX6Q. IOMUXC_GPR1[11:0]67 IOMUXC_GPR1[11:0] CS0 CS1 CS2 CS369 05 128M 0M 0M 0M70 033 64M 64M 0M 0M71 0113 64M 32M 32M 0M75 sets up in IOMUXC_GPR1[11:0] will be used.90 "^.*@[0-7],[0-9a-f]+$":133 "^.*@[0-7],[0-9a-f]+$":149 "^.*@[0-7],[0-9a-f]+$":[all …]
51 #size-cells = <0>;53 cpu0: cpu@0 {56 reg = <0x0>;86 #clock-cells = <0>;92 #clock-cells = <0>;100 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;105 #phy-cells = <0>;117 reg = <0x00900000 0x20000>;118 ranges = <0 0x00900000 0x20000>;128 reg = <0x00a01000 0x1000>,[all …]
58 #size-cells = <0>;60 cpu0: cpu@0 {63 reg = <0>;108 #clock-cells = <0>;115 #clock-cells = <0>;122 #clock-cells = <0>;123 clock-frequency = <0>;129 #clock-cells = <0>;130 clock-frequency = <0>;149 reg = <0x00900000 0x20000>;[all …]
59 #clock-cells = <0>;65 #clock-cells = <0>;66 clock-frequency = <0>;71 #clock-cells = <0>;78 #size-cells = <0>;83 lvds-channel@0 {85 #size-cells = <0>;86 reg = <0>;89 port@0 {90 reg = <0>;[all …]
61 #size-cells = <0>;63 cpu0: cpu@0 {66 reg = <0>;100 #clock-cells = <0>;107 #clock-cells = <0>;114 #clock-cells = <0>;115 clock-frequency = <0>;121 #clock-cells = <0>;122 clock-frequency = <0>;128 #clock-cells = <0>;[all …]