Lines Matching +full:0 +full:x021b8000
25 <cs-number> 0 <physical address of mapping> <size>
32 register, e.g. IOMUXC_GPR1 on i.MX6Q. IOMUXC_GPR1[11:0]
36 IOMUXC_GPR1[11:0] CS0 CS1 CS2 CS3
38 05 128M 0M 0M 0M
39 033 64M 64M 0M 0M
40 0113 64M 32M 32M 0M
44 what bootloader sets up in IOMUXC_GPR1[11:0] will be
75 reg = <0x021b8000 0x4000>;
79 ranges = <0 0 0x08000000 0x08000000>;
82 nor@0,0 {
84 reg = <0 0 0x02000000>;
88 fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000
89 0x0000c000 0x1404a38e 0x00000000>;
95 In this case, both chip select 0 and 1 will be configured with the same timing
100 reg = <0x021b8000 0x4000>;
104 ranges = <0 0 0x08000000 0x02000000
105 1 0 0x0a000000 0x02000000
106 2 0 0x0c000000 0x02000000
107 3 0 0x0e000000 0x02000000>;
110 acme@0 {
112 reg = <0 0 0x100>, <0 0x400000 0x800>,
113 <1 0x400000 0x800>;
114 fsl,weim-cs-timing = <0x024400b1 0x00001010 0x20081100
115 0x00000000 0xa0000240 0x00000000>;