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/freebsd/sys/contrib/device-tree/src/arm/cirrus/
H A Dep93xx-bk3.dts17 memory@0 {
20 reg = <0x00000000 0x02000000>,
21 <0x000530c0 0x01fdd000>;
26 led-0 {
28 gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>;
44 reg = <0x60000000 0x8000000>;
46 #size-cells = <0>;
48 nand@0 {
49 reg = <0>;
55 partition@0 {
[all …]
/freebsd/sys/contrib/device-tree/Bindings/bus/
H A Dmvebu-mbus.txt65 pcie-mem-aperture = <0xe0000000 0x8000000>;
66 pcie-io-aperture = <0xe8000000 0x100000>;
73 reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>;
87 0xSIAA0000 0x00oooooo
91 S = 0x0 for a MBus valid window
92 S = 0xf for a non-valid window (see below)
94 If S = 0x0, then:
99 If S = 0xf, then:
105 (S = 0x0), an address decoding window is allocated. On the other side,
106 entries for translation that do not correspond to valid windows (S = 0xf)
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/rockchip/
H A Drk3568.dtsi13 reg = <0 0xfc000000 0 0x1000>;
20 ports-implemented = <0x1>;
27 reg = <0x0 0xfdc70000 0x0 0x1000>;
32 reg = <0x0 0xfe190080 0x0 0x20>;
37 reg = <0x0 0xfe190100 0x0 0x20>;
42 reg = <0x0 0xfe190200 0x0 0x20>;
47 reg = <0x0 0xfdcb8000 0x0 0x10000>;
52 reg = <0x0 0xfe8c0000 0x0 0x20000>;
53 #phy-cells = <0>;
67 bus-range = <0x0 0xf>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/display/
H A Dallwinner,sun4i-a10-display-frontend.yaml63 port@0:
94 reg = <0x01e00000 0x20000>;
104 #size-cells = <0>;
108 #size-cells = <0>;
111 fe0_out_be0: endpoint@0 {
112 reg = <0>;
/freebsd/sys/contrib/device-tree/src/nios2/
H A D3c120_devboard.dts18 #size-cells = <0>;
20 cpu: cpu@0 {
23 reg = <0x00000000>;
38 altr,reset-addr = <0xc2800000>;
39 altr,fast-tlb-miss-addr = <0xc7fff400>;
40 altr,exception-addr = <0xd0000020>;
46 memory@0 {
48 reg = <0x10000000 0x08000000>,
49 <0x07fff400 0x00000400>;
52 sopc@0 {
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/allwinner/
H A Dsun50i-h5.dtsi11 #size-cells = <0>;
13 cpu0: cpu@0 {
16 reg = <0>;
84 reg = <0x01c00000 0x1000>;
91 reg = <0x00018000 0x1c000>;
94 ranges = <0 0x00018000 0x1c000>;
96 ve_sram: sram-section@0 {
99 reg = <0x000000 0x1c000>;
106 reg = <0x01c0e000 0x1000>;
117 reg = <0x01c15000 0x1000>;
[all …]
H A Dsun50i-a64.dtsi47 #size-cells = <0>;
49 cpu0: cpu@0 {
52 reg = <0>;
57 i-cache-size = <0x8000>;
60 d-cache-size = <0x8000>;
74 i-cache-size = <0x8000>;
77 d-cache-size = <0x8000>;
91 i-cache-size = <0x8000>;
94 d-cache-size = <0x8000>;
108 i-cache-size = <0x8000>;
[all …]
/freebsd/sys/contrib/alpine-hal/eth/
H A Dal_hal_an_lt_wrapper_regs.h60 /* [0x0] AN LT wrapper Version */
62 /* [0x4] AN LT general configuration */
67 /* [0x0] AN LT register file address */
69 /* [0x4] PCS register file data */
71 /* [0x8] AN LT control signals */
73 /* [0xc] AN LT status signals */
79 AL_ETH_AN_LT_UNIT_32_BIT = 0,
86 struct al_an_lt_wrapper_gen gen; /* [0x100] */
87 struct al_an_lt_wrapper_an_lt an_lt[3]; /* [0x140] */
98 #define AN_LT_WRAPPER_GEN_VERSION_RELEASE_NUM_MINOR_MASK 0x000000FF
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/ti/
H A Dk3-am62a-phycore-som.dtsi31 pinctrl-0 = <&leds_pins_default>;
33 led-0 {
44 reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
56 size = <0x00 0x24000000>;
57 alloc-ranges = <0x00 0xc0000000 0x00 0x24000000>;
62 reg = <0x00 0x9e780000 0x00 0x80000>;
63 alignment = <0x1000>;
68 reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
69 alignment = <0x1000>;
75 reg = <0x00 0x9c900000 0x00 0x01e00000>;
[all …]
H A Dk3-am62p5-sk.dts40 reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
41 <0x00000008 0x80000000 0x00000001 0x80000000>;
52 reg = <0x00 0x9e780000 0x00 0x80000>;
57 reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
63 reg = <0x00 0x9c900000 0x00 0x01e00000>;
68 vmain_pd: regulator-0 {
107 pinctrl-0 = <&vddshv_sdio_pins_default>;
112 states = <1800000 0x0>,
113 <3300000 0x1>;
120 pinctrl-0 = <&usr_led_pins_default>;
[all …]
H A Dk3-am62a7-sk.dts34 reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
35 <0x00000008 0x80000000 0x00000000 0x80000000>;
47 size = <0x00 0x24000000>;
48 alloc-ranges = <0x00 0xc0000000 0x00 0x24000000>;
53 reg = <0x00 0x9e780000 0x00 0x80000>;
54 alignment = <0x1000>;
59 reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
60 alignment = <0x1000>;
66 reg = <0x00 0x9c900000 0x00 0x01e00000>;
71 vmain_pd: regulator-0 {
[all …]
/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Dnvidia,tegra194-pcie.txt47 "p2u-N": where N ranges from 0 to one less than the total number of lanes
50 0: C0
65 - cell 0 specifies the bus and device numbers of the root port:
68 - cell 1 denotes the upper 32 address bits and should be 0
81 - 0x81000000: I/O memory region
82 - 0x82000000: non-prefetchable memory region
83 - 0xc2000000: prefetchable memory region
104 - pinctrl-0: phandle for the 'default' state of pin configuration.
147 reg = <0x00 0x14180000 0x0 0x00020000 /* appl registers (128K) */
148 0x00 0x38000000 0x0 0x00040000 /* configuration space (256K) */
[all …]
H A Dnvidia,tegra194-pcie.yaml85 - const: p2u-0
123 0: C0
132 0 : C0
260 bus@0 {
263 ranges = <0x0 0x0 0x0 0x8 0x0>;
268 reg = <0x0 0x14180000 0x0 0x00020000>, /* appl registers (128K) */
269 <0x0 0x38000000 0x0 0x00040000>, /* configuration space (256K) */
270 <0x0 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
271 <0x0 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */
278 linux,pci-domain = <0>;
[all …]
/freebsd/sys/contrib/alpine-hal/
H A Dal_hal_serdes_25g_regs.h57 /* [0x0] SERDES registers Version */
60 /* [0x10] SERDES register file address */
62 /* [0x14] SERDES register file data */
64 /* [0x18] SERDES control */
66 /* [0x1c] SERDES cpu mem address */
68 /* [0x20] SERDES cpu mem data */
70 /* [0x24] SERDES data mem address */
72 /* [0x28] SERDES data mem data */
74 /* [0x2c] SERDES control */
76 /* [0x30] SERDES control */
[all …]
H A Dal_hal_serdes_hssp_regs.h57 /* [0x0] SerDes Registers Version */
60 /* [0x10] SerDes register file address */
62 /* [0x14] SerDes register file data */
65 /* [0x20] SerDes control */
67 /* [0x24] SerDes control */
69 /* [0x28] SerDes control */
72 /* [0x30] SerDes control */
74 /* [0x34] SerDes control */
76 /* [0x38] SerDes control */
78 /* [0x3c] SerDes control */
[all …]
H A Dal_hal_serdes_regs.h58 /* [0x0] SerDes Registers Version */
61 /* [0x10] SerDes register file address */
63 /* [0x14] SerDes register file data */
66 /* [0x20] SerDes control */
68 /* [0x24] SerDes control */
70 /* [0x28] SerDes control */
73 /* [0x30] SerDes control */
75 /* [0x34] SerDes control */
77 /* [0x38] SerDes control */
79 /* [0x3c] SerDes control */
[all …]
/freebsd/sys/contrib/dev/rtw89/
H A Drtw8852a_rfk_table.c8 RTW89_DECL_RFK_WM(0x12a8, 0x00000001, 0x00000001),
9 RTW89_DECL_RFK_WM(0x12a8, 0x0000000e, 0x00000002),
10 RTW89_DECL_RFK_WM(0x32a8, 0x00000001, 0x00000001),
11 RTW89_DECL_RFK_WM(0x32a8, 0x0000000e, 0x00000002),
12 RTW89_DECL_RFK_WM(0x12bc, 0x000000f0, 0x00000005),
13 RTW89_DECL_RFK_WM(0x12bc, 0x00000f00, 0x00000005),
14 RTW89_DECL_RFK_WM(0x12bc, 0x000f0000, 0x00000005),
15 RTW89_DECL_RFK_WM(0x12bc, 0x0000f000, 0x00000005),
16 RTW89_DECL_RFK_WM(0x120c, 0x000000ff, 0x00000033),
17 RTW89_DECL_RFK_WM(0x12c0, 0x0ff00000, 0x00000033),
[all …]
/freebsd/sys/dev/bhnd/cores/pmu/
H A Dbhnd_pmureg.h29 (((_value) & _flag) != 0)
43 #define BHND_CLK_CTL_ST 0x1e0 /**< clock control and status */
55 #define BHND_CCS_FORCEALP 0x00000001 /**< force ALP request */
56 #define BHND_CCS_FORCEHT 0x00000002 /**< force HT request */
57 #define BHND_CCS_FORCEILP 0x00000004 /**< force ILP request */
58 #define BHND_CCS_FORCE_MASK 0x0000000F
60 #define BHND_CCS_ALPAREQ 0x00000008 /**< ALP Avail Request */
61 #define BHND_CCS_HTAREQ 0x00000010 /**< HT Avail Request */
62 #define BHND_CCS_AREQ_MASK 0x00000018
64 #define BHND_CCS_FORCEHWREQOFF 0x00000020 /**< Force HW Clock Request Off */
[all …]
/freebsd/sys/contrib/device-tree/src/arm/allwinner/
H A Dsun5i.dtsi56 #size-cells = <0>;
58 cpu0: cpu@0 {
61 reg = <0x0>;
97 #clock-cells = <0>;
104 #clock-cells = <0>;
119 size = <0x6000000>;
120 alloc-ranges = <0x40000000 0x10000000>;
135 reg = <0x01c00000 0x30>;
140 sram_a: sram@0 {
142 reg = <0x00000000 0xc000>;
[all …]
H A Dsun8i-a23-a33.dtsi91 #size-cells = <0>;
93 cpu0: cpu@0 {
96 reg = <0>;
112 #clock-cells = <0>;
120 #clock-cells = <0>;
136 reg = <0x01c00000 0x30>;
143 reg = <0x01d00000 0x80000>;
146 ranges = <0 0x01d00000 0x80000>;
148 ve_sram: sram-section@0 {
151 reg = <0x000000 0x80000>;
[all …]
H A Dsun4i-a10.dtsi111 #size-cells = <0>;
112 cpu0: cpu@0 {
115 reg = <0x0>;
166 #clock-cells = <0>;
173 #clock-cells = <0>;
199 size = <0x6000000>;
200 alloc-ranges = <0x40000000 0x10000000>;
214 reg = <0x01c00000 0x30>;
219 sram_a: sram@0 {
221 reg = <0x00000000 0xc000>;
[all …]
H A Dsun6i-a31.dtsi101 #size-cells = <0>;
103 cpu0: cpu@0 {
106 reg = <0>;
213 #clock-cells = <0>;
221 #clock-cells = <0>;
238 #clock-cells = <0>;
245 #clock-cells = <0>;
252 #clock-cells = <0>;
254 reg = <0x01c200d0 0x4>;
274 reg = <0x01c02000 0x1000>;
[all …]
/freebsd/sys/arm/arm/
H A Ddisassem.c76 * m - m register (bits 0-3)
81 * h - 3rd fp operand (register/immediate) (bits 0-4)
83 * t - thumb branch address (bits 24, 0-23)
84 * k - breakpoint comment (bits 0-3, 8-19)
87 * c - comment field bits(0-23)
112 { 0x0fffffff, 0x0ff00000, "imb", "c" }, /* Before swi */
113 { 0x0fffffff, 0x0ff00001, "imbrange", "c" }, /* Before swi */
114 { 0x0f000000, 0x0f000000, "swi", "c" },
115 { 0xfe000000, 0xfa000000, "blx", "t" }, /* Before b and bl */
116 { 0x0f000000, 0x0a000000, "b", "b" },
[all …]
/freebsd/sys/dev/usb/controller/
H A Ddwc_otgreg.h32 #define DOTG_GOTGCTL 0x0000
33 #define DOTG_GOTGINT 0x0004
34 #define DOTG_GAHBCFG 0x0008
35 #define DOTG_GUSBCFG 0x000C
36 #define DOTG_GRSTCTL 0x0010
37 #define DOTG_GINTSTS 0x0014
38 #define DOTG_GINTMSK 0x0018
39 #define DOTG_GRXSTSRD 0x001C
40 #define DOTG_GRXSTSRH 0x001C
41 #define DOTG_GRXSTSPD 0x0020
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dsm6125.dtsi24 #clock-cells = <0>;
30 #clock-cells = <0>;
38 #size-cells = <0>;
40 CPU0: cpu@0 {
43 reg = <0x0 0x0>;
57 reg = <0x0 0x1>;
66 reg = <0x0 0x2>;
75 reg = <0x0 0x3>;
84 reg = <0x0 0x100>;
98 reg = <0x0 0x101>;
[all …]

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