Home
last modified time | relevance | path

Searched +full:0 +full:x01d84000 (Results 1 – 18 of 18) sorted by relevance

/linux/Documentation/devicetree/bindings/ufs/
H A Dqcom,sm8650-ufshc.yaml88 reg = <0x0 0x01d84000 0x0 0x3000>;
90 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;
125 iommus = <&apps_smmu 0x60 0>;
145 /bits/ 64 <0>,
146 /bits/ 64 <0>,
148 /bits/ 64 <0>,
149 /bits/ 64 <0>,
150 /bits/ 64 <0>,
151 /bits/ 64 <0>;
157 /bits/ 64 <0>,
[all …]
H A Dqcom,ufs.yaml191 reg = <0x0 0x01d84000 0x0 0x2500>,
192 <0x0 0x01d90000 0x0 0x8000>;
210 iommus = <&apps_smmu 0x300 0>;
231 <0 0>,
232 <0 0>,
234 <0 0>,
235 <0 0>,
236 <0 0>,
237 <0 0>,
238 <0 300000000>;
/linux/arch/arm64/boot/dts/qcom/
H A Dsm6350.dtsi35 #clock-cells = <0>;
43 #clock-cells = <0>;
49 #size-cells = <0>;
51 cpu0: cpu@0 {
54 reg = <0x0 0x0>;
55 clocks = <&cpufreq_hw 0>;
60 qcom,freq-domain = <&cpufreq_hw 0>;
84 reg = <0x0 0x10
[all...]
H A Dsm8750.dtsi32 #size-cells = <0>;
34 cpu0: cpu@0 {
37 reg = <0x0 0x0>;
40 power-domains = <&cpu_pd0>, <&scmi_dvfs 0>;
53 reg = <0x0 0x100>;
56 power-domains = <&cpu_pd1>, <&scmi_dvfs 0>;
63 reg = <0x0 0x20
[all...]
H A Dsc8180x.dtsi32 #clock-cells = <0>;
38 #clock-cells = <0>;
46 #size-cells = <0>;
48 cpu0: cpu@0 {
51 reg = <0x0 0x0>;
55 qcom,freq-domain = <&cpufreq_hw 0>;
62 clocks = <&cpufreq_hw 0>;
80 reg = <0x0 0x100>;
84 qcom,freq-domain = <&cpufreq_hw 0>;
91 clocks = <&cpufreq_hw 0>;
[all …]
H A Dsm8350.dtsi40 #clock-cells = <0>;
48 #clock-cells = <0>;
54 #size-cells = <0>;
56 cpu0: cpu@0 {
59 reg = <0x0 0x0>;
60 clocks = <&cpufreq_hw 0>;
63 qcom,freq-domain = <&cpufreq_hw 0>;
83 reg = <0x0 0x100>;
84 clocks = <&cpufreq_hw 0>;
87 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dtalos.dtsi30 #size-cells = <0>;
32 cpu0: cpu@0 {
35 reg = <0x0 0x0>;
42 clocks = <&cpufreq_hw 0>;
43 qcom,freq-domain = <&cpufreq_hw 0>;
61 reg = <0x0 0x100>;
68 clocks = <&cpufreq_hw 0>;
69 qcom,freq-domain = <&cpufreq_hw 0>;
[all...]
H A Dsc7180.dtsi67 #clock-cells = <0>;
73 #clock-cells = <0>;
79 #size-cells = <0>;
81 cpu0: cpu@0 {
84 reg = <0x0 0x0>;
85 clocks = <&cpufreq_hw 0>;
96 qcom,freq-domain = <&cpufreq_hw 0>;
113 reg = <0x0 0x100>;
114 clocks = <&cpufreq_hw 0>;
125 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dsm8150.dtsi35 #clock-cells = <0>;
42 #clock-cells = <0>;
50 #size-cells = <0>;
52 cpu0: cpu@0 {
55 reg = <0x0 0x0>;
56 clocks = <&cpufreq_hw 0>;
61 qcom,freq-domain = <&cpufreq_hw 0>;
63 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
[all...]
H A Dsm8450.dtsi40 #clock-cells = <0>;
46 #clock-cells = <0>;
53 #size-cells = <0>;
55 cpu0: cpu@0 {
58 reg = <0x0 0x0>;
63 qcom,freq-domain = <&cpufreq_hw 0>;
65 clocks = <&cpufreq_hw 0>;
82 reg = <0x0 0x100>;
87 qcom,freq-domain = <&cpufreq_hw 0>;
89 clocks = <&cpufreq_hw 0>;
[all …]
H A Dsdm845.dtsi79 #clock-cells = <0>;
86 #clock-cells = <0>;
93 #size-cells = <0>;
95 cpu0: cpu@0 {
98 reg = <0x0 0x0>;
99 clocks = <&cpufreq_hw 0>;
103 qcom,freq-domain = <&cpufreq_hw 0>;
127 reg = <0x0 0x100>;
128 clocks = <&cpufreq_hw 0>;
132 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dmonaco.dtsi33 #clock-cells = <0>;
39 #clock-cells = <0>;
46 #size-cells = <0>;
48 cpu0: cpu@0 {
51 reg = <0x0 0x0>;
59 qcom,freq-domain = <&cpufreq_hw 0>;
77 reg = <0x0 0x100>;
85 qcom,freq-domain = <&cpufreq_hw 0>;
[all...]
H A Dsc8280xp.dtsi34 #clock-cells = <0>;
39 #clock-cells = <0>;
46 #size-cells = <0>;
48 cpu0: cpu@0 {
51 reg = <0x0 0x0>;
52 clocks = <&cpufreq_hw 0>;
59 qcom,freq-domain = <&cpufreq_hw 0>;
79 reg = <0x0 0x10
[all...]
H A Dsm8550.dtsi40 #clock-cells = <0>;
45 #clock-cells = <0>;
49 #clock-cells = <0>;
57 #clock-cells = <0>;
67 #size-cells = <0>;
69 cpu0: cpu@0 {
72 reg = <0 0>;
73 clocks = <&cpufreq_hw 0>;
78 qcom,freq-domain = <&cpufreq_hw 0>;
98 reg = <0 0x100>;
[all …]
H A Dsm8250.dtsi81 #clock-cells = <0>;
89 #clock-cells = <0>;
95 #size-cells = <0>;
97 cpu0: cpu@0 {
100 reg = <0x0 0x0>;
101 clocks = <&cpufreq_hw 0>;
108 qcom,freq-domain = <&cpufreq_hw 0>;
110 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
116 cache-size = <0x20000>;
122 cache-size = <0x400000>;
[all …]
H A Dkodiak.dtsi84 #clock-cells = <0>;
90 #clock-cells = <0>;
101 reg = <0x0 0x004cd000 0x0 0x1000>;
105 reg = <0x0 0x80000000 0x0 0x60000
[all...]
H A Dsm8650.dtsi42 #clock-cells = <0>;
47 #clock-cells = <0>;
52 #clock-cells = <0>;
61 #clock-cells = <0>;
71 #size-cells = <0>;
73 cpu0: cpu@0 {
76 reg = <0 0>;
78 clocks = <&cpufreq_hw 0>;
88 qcom,freq-domain = <&cpufreq_hw 0>;
[all...]
H A Dlemans.dtsi35 #clock-cells = <0>;
40 #clock-cells = <0>;
46 #size-cells = <0>;
48 cpu0: cpu@0 {
51 reg = <0x0 0x0>;
55 qcom,freq-domain = <&cpufreq_hw 0>;
81 reg = <0x0 0x100>;
85 qcom,freq-domain = <&cpufreq_hw 0>;
[all...]