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/linux/drivers/usb/storage/
H A Dunusual_isd200.h9 UNUSUAL_DEV( 0x054c, 0x002b, 0x0100, 0x0110,
13 0),
15 UNUSUAL_DEV( 0x05ab, 0x0031, 0x0100, 0x0110,
19 0),
21 UNUSUAL_DEV( 0x05ab, 0x0301, 0x0100, 0x0110,
25 0),
27 UNUSUAL_DEV( 0x05ab, 0x0351, 0x0100, 0x0110,
31 0),
33 UNUSUAL_DEV( 0x05ab, 0x5701, 0x0100, 0x0110,
37 0),
[all …]
/linux/drivers/pinctrl/mediatek/
H A Dpinctrl-mt8188.c13 * iocfg[0]:0x10005000, iocfg[1]:0x11c00000, iocfg[2]:0x11e10000,
14 * iocfg[3]:0x11e20000, iocfg[4]:0x11ea0000
20 32, 0)
27 PIN_FIELD(0, 177, 0x0300, 0x10, 0, 4),
31 PIN_FIELD(0, 177, 0x0000, 0x10, 0, 1),
35 PIN_FIELD(0, 177, 0x0200, 0x10, 0, 1),
39 PIN_FIELD(0, 177, 0x0100, 0x10, 0, 1),
43 PIN_FIELD_BASE(0, 0, 1, 0x0170, 0x10, 8, 1),
44 PIN_FIELD_BASE(1, 1, 1, 0x0170, 0x10, 9, 1),
45 PIN_FIELD_BASE(2, 2, 1, 0x0170, 0x10, 10, 1),
[all …]
H A Dpinctrl-mt8189.c13 32, 0)
20 PIN_FIELD(0, 182, 0x0300, 0x10, 0, 4),
24 PIN_FIELD(0, 182, 0x0000, 0x10, 0, 1),
28 PIN_FIELD(0, 182, 0x0200, 0x10, 0, 1),
32 PIN_FIELD(0, 182, 0x0100, 0x10, 0, 1),
36 PIN_FIELD_BASE(0, 0, 7, 0x00e0, 0x10, 5, 1),
37 PIN_FIELD_BASE(1, 1, 8, 0x00c0, 0x10, 3, 1),
38 PIN_FIELD_BASE(2, 2, 8, 0x00c0, 0x10, 4, 1),
39 PIN_FIELD_BASE(3, 3, 8, 0x00c0, 0x10, 5, 1),
40 PIN_FIELD_BASE(4, 4, 8, 0x00c0, 0x10, 6, 1),
[all …]
H A Dpinctrl-mt8196.c15 32, 0)
22 PIN_FIELD(0, 270, 0x0300, 0x10, 0, 4),
26 PIN_FIELD(0, 270, 0x0000, 0x10, 0, 1),
30 PIN_FIELD(0, 270, 0x0200, 0x10, 0, 1),
34 PIN_FIELD(0, 270, 0x0100, 0x10, 0, 1),
38 PIN_FIELD_BASE(0, 0, 8, 0x00d0, 0x10, 0, 1),
39 PIN_FIELD_BASE(1, 1, 8, 0x00d0, 0x10, 1, 1),
40 PIN_FIELD_BASE(2, 2, 11, 0x00a0, 0x10, 1, 1),
41 PIN_FIELD_BASE(3, 3, 11, 0x00a0, 0x10, 1, 1),
42 PIN_FIELD_BASE(4, 4, 11, 0x00a0, 0x10, 2, 1),
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8ulp-pinfunc.h13 #define MX8ULP_PAD_PTD0__PTD0 0x0000 0x0000 0x1 0x0
14 #define MX8ULP_PAD_PTD0__I2S6_RX_BCLK 0x0000 0x0B44 0x7 0x1
15 #define MX8ULP_PAD_PTD0__SDHC0_RESET_B 0x0000 0x0000 0x8 0x0
16 #define MX8ULP_PAD_PTD0__FLEXSPI2_B_DQS 0x0000 0x0974 0x9 0x1
17 #define MX8ULP_PAD_PTD0__CLKOUT2 0x0000 0x0000 0xa 0x0
18 #define MX8ULP_PAD_PTD0__EPDC0_SDCLK_B 0x0000 0x0000 0xb 0x0
19 #define MX8ULP_PAD_PTD0__LP_APD_DBG_MUX_0 0x0000 0x0000 0xc 0x0
20 #define MX8ULP_PAD_PTD0__CLKOUT1 0x0000 0x0000 0xd 0x0
21 #define MX8ULP_PAD_PTD0__DEBUG_MUX0_0 0x0000 0x0000 0xe 0x0
22 #define MX8ULP_PAD_PTD0__DEBUG_MUX1_0 0x0000 0x0000 0xf 0x0
[all …]
H A Dimx95-pinfunc.h13 #define IMX95_PAD_DAP_TDI__JTAG_MUX_TDI 0x0000 0x0204 0x0610 0x00 0x00
14 #define IMX95_PAD_DAP_TDI__NETCMIX_TOP_MQS2_LEFT 0x0000 0x0204 0x0000 0x01 0x00
15 #define IMX95_PAD_DAP_TDI__NETCMIX_TOP_NETC_TMR_1588_ALARM1 0x0000 0x0204 0x0000 0x02 0x00
16 #define IMX95_PAD_DAP_TDI__CAN2_TX 0x0000 0x0204 0x0000 0x03 0x00
17 #define IMX95_PAD_DAP_TDI__FLEXIO2_FLEXIO_BIT30 0x0000 0x0204 0x0000 0x04 0x00
18 #define IMX95_PAD_DAP_TDI__GPIO3_IO_BIT28 0x0000 0x0204 0x0000 0x05 0x00
19 #define IMX95_PAD_DAP_TDI__LPUART5_RX 0x0000 0x0204 0x0570 0x06 0x00
21 #define IMX95_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x0004 0x0208 0x0614 0x00 0x00
22 #define IMX95_PAD_DAP_TMS_SWDIO__CAN4_TX 0x0004 0x0208 0x0000 0x02 0x00
23 #define IMX95_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO_BIT31 0x0004 0x0208 0x0000 0x04 0x00
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx7ulp-pinfunc.h15 #define IMX7ULP_PAD_PTC0__PTC0 0x0000 0x0000 0x1 0x0
16 #define IMX7ULP_PAD_PTC0__TRACE_D15 0x0000 0x0000 0xa 0x0
17 #define IMX7ULP_PAD_PTC0__LPUART4_CTS_B 0x0000 0x0244 0x4 0x1
18 #define IMX7ULP_PAD_PTC0__LPI2C4_SCL 0x0000 0x0278 0x5 0x1
19 #define IMX7ULP_PAD_PTC0__TPM4_CLKIN 0x0000 0x0298 0x6 0x1
20 #define IMX7ULP_PAD_PTC0__FB_AD0 0x0000 0x0000 0x9 0x0
21 #define IMX7ULP_PAD_PTC1__PTC1 0x0004 0x0000 0x1 0x0
22 #define IMX7ULP_PAD_PTC1__TRACE_D14 0x0004 0x0000 0xa 0x0
23 #define IMX7ULP_PAD_PTC1__LPUART4_RTS_B 0x0004 0x0000 0x4 0x0
24 #define IMX7ULP_PAD_PTC1__LPI2C4_SDA 0x0004 0x027c 0x5 0x1
[all …]
H A Dimx6ul-pinfunc.h13 #define MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x0014 0x02a0 0x0000 5 0
14 #define MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x0018 0x02a4 0x0000 5 0
16 #define MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x001c 0x02a8 0x0000 5 0
17 #define MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x0020 0x02ac 0x0000 5 0
18 #define MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0024 0x02b0 0x0000 5 0
19 #define MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0028 0x02b4 0x0000 5 0
20 #define MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x002c 0x02b8 0x0000 5 0
21 #define MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0030 0x02bc 0x0000 5 0
22 #define MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0034 0x02c0 0x0000 5 0
23 #define MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0038 0x02c4 0x0000 5 0
[all …]
/linux/drivers/clk/samsung/
H A Dclk-exynos5260.h15 #define MUX_SEL_AUD 0x0200
16 #define MUX_ENABLE_AUD 0x0300
17 #define MUX_STAT_AUD 0x0400
18 #define MUX_IGNORE_AUD 0x0500
19 #define DIV_AUD0 0x0600
20 #define DIV_AUD1 0x0604
21 #define DIV_STAT_AUD0 0x0700
22 #define DIV_STAT_AUD1 0x0704
23 #define EN_ACLK_AUD 0x0800
24 #define EN_PCLK_AUD 0x0900
[all …]
/linux/drivers/clk/mediatek/
H A Dclk-mt7988-topckgen.c107 MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, 0x000, 0x004, 0x008,
108 0, 2, 7, 0x1c0, 0),
109 MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", netsys_500m_parents, 0x000,
110 0x004, 0x008, 8, 2, 15, 0x1C0, 1),
111 MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", netsys_2x_parents, 0x000,
112 0x004, 0x008, 16, 2, 23, 0x1C0, 2),
113 MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_GSW_SEL, "netsys_gsw_sel", netsys_gsw_parents, 0x000,
114 0x004, 0x008, 24, 2, 31, 0x1C0, 3),
116 MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_GMII_SEL, "eth_gmii_sel", eth_gmii_parents, 0x010, 0x014,
117 0x018, 0, 1, 7, 0x1C0, 4),
[all …]
H A Dclk-mt8186-topckgen.c22 FACTOR_FLAGS(CLK_TOP_MAINPLL_D2, "mainpll_d2", "mainpll", 1, 2, 0),
23 FACTOR_FLAGS(CLK_TOP_MAINPLL_D2_D2, "mainpll_d2_d2", "mainpll_d2", 1, 2, 0),
24 FACTOR_FLAGS(CLK_TOP_MAINPLL_D2_D4, "mainpll_d2_d4", "mainpll_d2", 1, 4, 0),
25 FACTOR_FLAGS(CLK_TOP_MAINPLL_D2_D16, "mainpll_d2_d16", "mainpll_d2", 1, 16, 0),
26 FACTOR_FLAGS(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3, 0),
27 FACTOR_FLAGS(CLK_TOP_MAINPLL_D3_D2, "mainpll_d3_d2", "mainpll_d3", 1, 2, 0),
28 FACTOR_FLAGS(CLK_TOP_MAINPLL_D3_D4, "mainpll_d3_d4", "mainpll_d3", 1, 4, 0),
29 FACTOR_FLAGS(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5, 0),
30 FACTOR_FLAGS(CLK_TOP_MAINPLL_D5_D2, "mainpll_d5_d2", "mainpll_d5", 1, 2, 0),
31 FACTOR_FLAGS(CLK_TOP_MAINPLL_D5_D4, "mainpll_d5_d4", "mainpll_d5", 1, 4, 0),
[all …]
/linux/drivers/net/ethernet/wangxun/ngbevf/
H A Dngbevf_type.h8 #define NGBEVF_DEV_ID_EM_WX1860AL_W 0x0110
9 #define NGBEVF_DEV_ID_EM_WX1860A2 0x0111
10 #define NGBEVF_DEV_ID_EM_WX1860A2S 0x0112
11 #define NGBEVF_DEV_ID_EM_WX1860A4 0x0113
12 #define NGBEVF_DEV_ID_EM_WX1860A4S 0x0114
13 #define NGBEVF_DEV_ID_EM_WX1860AL2 0x0115
14 #define NGBEVF_DEV_ID_EM_WX1860AL2S 0x0116
15 #define NGBEVF_DEV_ID_EM_WX1860AL4 0x0117
16 #define NGBEVF_DEV_ID_EM_WX1860AL4S 0x0118
17 #define NGBEVF_DEV_ID_EM_WX1860NCSI 0x0119
[all …]
/linux/arch/arm/mach-dove/
H A Dbridge-regs.h9 #define CPU_CONFIG (BRIDGE_VIRT_BASE + 0x0000)
11 #define CPU_CONTROL (BRIDGE_VIRT_BASE + 0x0104)
12 #define CPU_CTRL_PCIE0_LINK 0x00000001
13 #define CPU_RESET 0x00000002
14 #define CPU_CTRL_PCIE1_LINK 0x00000008
16 #define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108)
17 #define RSTOUTn_MASK_PHYS (BRIDGE_PHYS_BASE + 0x0108)
18 #define SOFT_RESET_OUT_EN 0x00000004
20 #define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE + 0x010c)
21 #define SOFT_RESET 0x00000001
[all …]
/linux/drivers/video/fbdev/nvidia/
H A Dnv_setup.c62 VGA_WR08(par->PCIO, par->IOBase + 0x04, index); in NVWriteCrtc()
63 VGA_WR08(par->PCIO, par->IOBase + 0x05, value); in NVWriteCrtc()
67 VGA_WR08(par->PCIO, par->IOBase + 0x04, index); in NVReadCrtc()
68 return (VGA_RD08(par->PCIO, par->IOBase + 0x05)); in NVReadCrtc()
93 VGA_RD08(par->PCIO, par->IOBase + 0x0a); in NVWriteAttr()
95 index &= ~0x20; in NVWriteAttr()
97 index |= 0x20; in NVWriteAttr()
103 VGA_RD08(par->PCIO, par->IOBase + 0x0a); in NVReadAttr()
105 index &= ~0x20; in NVReadAttr()
107 index |= 0x20; in NVReadAttr()
[all …]
/linux/arch/mips/include/asm/mips-boards/
H A Dmalta.h17 #define MIPS_MSC01_IC_REG_BASE 0x1bc40000
18 #define MIPS_SOCITSC_IC_REG_BASE 0x1ffa0000
25 #define MALTA_BONITO_PORT_BASE ((unsigned long)ioremap (0x1fd00000, 0x10000))
32 return (unsigned long) ioremap (((addr & 0xffff) << 21), 0x10000); in get_gt_port_base()
39 return (unsigned long) ioremap(addr, 0x10000); in get_msc_port_base()
45 #define GCMP_BASE_ADDR 0x1fbf8000
51 #define GIC_BASE_ADDR 0x1bdc0000
57 #define CPC_BASE_ADDR 0x1bde0000
63 #define MSC01_BIU_REG_BASE 0x1bc80000
65 #define MSC01_SC_CFG_OFS 0x0110
[all …]
/linux/drivers/gpu/drm/nouveau/
H A Dnouveau_bo90b5.c38 u64 src_offset = mem->vma[0].addr; in nvc0_bo_move_copy()
51 PUSH_NVSQ(push, NV90B5, 0x030c, upper_32_bits(src_offset), in nvc0_bo_move_copy()
52 0x0310, lower_32_bits(src_offset), in nvc0_bo_move_copy()
53 0x0314, upper_32_bits(dst_offset), in nvc0_bo_move_copy()
54 0x0318, lower_32_bits(dst_offset), in nvc0_bo_move_copy()
55 0x031c, PAGE_SIZE, in nvc0_bo_move_copy()
56 0x0320, PAGE_SIZE, in nvc0_bo_move_copy()
57 0x0324, PAGE_SIZE, in nvc0_bo_move_copy()
58 0x0328, line_count); in nvc0_bo_move_copy()
59 PUSH_NVIM(push, NV90B5, 0x0300, 0x0110); in nvc0_bo_move_copy()
[all …]
/linux/drivers/media/cec/platform/s5p/
H A Dregs-cec.h16 #define S5P_CEC_STATUS_0 (0x0000)
17 #define S5P_CEC_STATUS_1 (0x0004)
18 #define S5P_CEC_STATUS_2 (0x0008)
19 #define S5P_CEC_STATUS_3 (0x000C)
20 #define S5P_CEC_IRQ_MASK (0x0010)
21 #define S5P_CEC_IRQ_CLEAR (0x0014)
22 #define S5P_CEC_LOGIC_ADDR (0x0020)
23 #define S5P_CEC_DIVISOR_0 (0x0030)
24 #define S5P_CEC_DIVISOR_1 (0x0034)
25 #define S5P_CEC_DIVISOR_2 (0x0038)
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/smuio/
H A Dsmuio_10_0_2_offset.h24 // base address: 0x5a000
25 …SMUIO_MCM_CONFIG 0x0023
26 …ne mmSMUIO_MCM_CONFIG_BASE_IDX 0
27 …IP_DISCOVERY_VERSION 0x0000
29 …IO_SMUIO_PINSTRAP 0x01b1
31 …SCRATCH_REGISTER0 0x01b2
33 …SCRATCH_REGISTER1 0x01b3
35 …SCRATCH_REGISTER2 0x01b4
37 …SCRATCH_REGISTER3 0x01b5
39 …SCRATCH_REGISTER4 0x01b6
[all …]
H A Dsmuio_11_0_0_offset.h27 // base address: 0x5a000
28 …SMUSVI0_TEL_PLANE0 0x0004
29 …ne mmSMUSVI0_TEL_PLANE0_BASE_IDX 0
30 …SMUIO_MCM_CONFIG 0x0024
31 …ne mmSMUIO_MCM_CONFIG_BASE_IDX 0
32 …CKSVII2C_IC_CON 0x0040
33 …ne mmCKSVII2C_IC_CON_BASE_IDX 0
34 …CKSVII2C_IC_TAR 0x0041
35 …ne mmCKSVII2C_IC_TAR_BASE_IDX 0
36 …CKSVII2C_IC_SAR 0x0042
[all …]
/linux/drivers/gpu/drm/arm/
H A Dhdlcd_regs.h15 #define HDLCD_REG_VERSION 0x0000 /* ro */
16 #define HDLCD_REG_INT_RAWSTAT 0x0010 /* rw */
17 #define HDLCD_REG_INT_CLEAR 0x0014 /* wo */
18 #define HDLCD_REG_INT_MASK 0x0018 /* rw */
19 #define HDLCD_REG_INT_STATUS 0x001c /* ro */
20 #define HDLCD_REG_FB_BASE 0x0100 /* rw */
21 #define HDLCD_REG_FB_LINE_LENGTH 0x0104 /* rw */
22 #define HDLCD_REG_FB_LINE_COUNT 0x0108 /* rw */
23 #define HDLCD_REG_FB_LINE_PITCH 0x010c /* rw */
24 #define HDLCD_REG_BUS_OPTIONS 0x0110 /* rw */
[all …]
/linux/arch/arm64/boot/dts/ti/
H A Dk3-am642-evm-icssg1-dualemac.dtso24 #size-cells = <0>;
26 mdio@0 {
27 reg = <0x0>;
29 #size-cells = <0>;
43 AM64X_IOPAD(0x0108, PIN_INPUT, 2) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */
44 AM64X_IOPAD(0x010c, PIN_INPUT, 2) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */
45 AM64X_IOPAD(0x0110, PIN_INPUT, 2) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */
46 AM64X_IOPAD(0x0114, PIN_INPUT, 2) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */
47 AM64X_IOPAD(0x0120, PIN_INPUT, 2) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */
48 AM64X_IOPAD(0x0118, PIN_INPUT, 2) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */
[all …]
/linux/include/acpi/
H A Dvideo.h30 #define ACPI_VIDEO_DISPLAY_LEGACY_MONITOR 0x0100
31 #define ACPI_VIDEO_DISPLAY_LEGACY_PANEL 0x0110
32 #define ACPI_VIDEO_DISPLAY_LEGACY_TV 0x0200
34 #define ACPI_VIDEO_NOTIFY_SWITCH 0x80
35 #define ACPI_VIDEO_NOTIFY_PROBE 0x81
36 #define ACPI_VIDEO_NOTIFY_CYCLE 0x82
37 #define ACPI_VIDEO_NOTIFY_NEXT_OUTPUT 0x83
38 #define ACPI_VIDEO_NOTIFY_PREV_OUTPUT 0x84
39 #define ACPI_VIDEO_NOTIFY_CYCLE_BRIGHTNESS 0x85
40 #define ACPI_VIDEO_NOTIFY_INC_BRIGHTNESS 0x86
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/nbio/
H A Dnbio_7_0_offset.h27 // base address: 0x0
28 …NB_NBCFG0_NB_VENDOR_ID 0x0000
29 …NB_NBCFG0_NB_DEVICE_ID 0x0002
30 …NB_NBCFG0_NB_COMMAND 0x0004
31 …NB_NBCFG0_NB_STATUS 0x0006
32 …NB_NBCFG0_NB_REVISION_ID 0x0008
33 …NB_NBCFG0_NB_REGPROG_INF 0x0009
34 …NB_NBCFG0_NB_SUB_CLASS 0x000a
35 …NB_NBCFG0_NB_BASE_CODE 0x000b
36 …NB_NBCFG0_NB_CACHE_LINE 0x000c
[all …]
/linux/drivers/hwtracing/intel_th/
H A Dmsu.h12 REG_MSU_MSUPARAMS = 0x0000,
13 REG_MSU_MSUSTS = 0x0008,
14 REG_MSU_MINTCTL = 0x0004, /* MSU-global interrupt control */
15 REG_MSU_MSC0CTL = 0x0100, /* MSC0 control */
16 REG_MSU_MSC0STS = 0x0104, /* MSC0 status */
17 REG_MSU_MSC0BAR = 0x0108, /* MSC0 output base address */
18 REG_MSU_MSC0SIZE = 0x010c, /* MSC0 output size */
19 REG_MSU_MSC0MWP = 0x0110, /* MSC0 write pointer */
20 REG_MSU_MSC0NWSA = 0x011c, /* MSC0 next window start address */
22 REG_MSU_MSC1CTL = 0x0200, /* MSC1 control */
[all …]
/linux/Documentation/devicetree/bindings/clock/ti/
H A Dti,mux-clock.yaml25 0 foo_clock
50 const: 0
65 default: 0
107 #size-cells = <0>;
111 reg = <0x0110>;
112 #clock-cells = <0>;
120 reg = <0x0120>;
121 #clock-cells = <0>;

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