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/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8ulp-pinfunc.h13 #define MX8ULP_PAD_PTD0__PTD0 0x0000 0x0000 0x1 0x0
14 #define MX8ULP_PAD_PTD0__I2S6_RX_BCLK 0x0000 0x0B44 0x7 0x1
15 #define MX8ULP_PAD_PTD0__SDHC0_RESET_B 0x0000 0x0000 0x8 0x0
16 #define MX8ULP_PAD_PTD0__FLEXSPI2_B_DQS 0x0000 0x0974 0x9 0x1
17 #define MX8ULP_PAD_PTD0__CLKOUT2 0x0000 0x0000 0xa 0x0
18 #define MX8ULP_PAD_PTD0__EPDC0_SDCLK_B 0x0000 0x0000 0xb 0x0
19 #define MX8ULP_PAD_PTD0__LP_APD_DBG_MUX_0 0x0000 0x0000 0xc 0x0
20 #define MX8ULP_PAD_PTD0__CLKOUT1 0x0000 0x0000 0xd 0x0
21 #define MX8ULP_PAD_PTD0__DEBUG_MUX0_0 0x0000 0x0000 0xe 0x0
22 #define MX8ULP_PAD_PTD0__DEBUG_MUX1_0 0x0000 0x0000 0xf 0x0
[all …]
H A Dimx95-pinfunc.h13 #define IMX95_PAD_DAP_TDI__JTAG_MUX_TDI 0x0000 0x0204 0x0610 0x00 0x00
14 #define IMX95_PAD_DAP_TDI__NETCMIX_TOP_MQS2_LEFT 0x0000 0x0204 0x0000 0x01 0x00
15 #define IMX95_PAD_DAP_TDI__NETCMIX_TOP_NETC_TMR_1588_ALARM1 0x0000 0x0204 0x0000 0x02 0x00
16 #define IMX95_PAD_DAP_TDI__CAN2_TX 0x0000 0x0204 0x0000 0x03 0x00
17 #define IMX95_PAD_DAP_TDI__FLEXIO2_FLEXIO_BIT30 0x0000 0x0204 0x0000 0x04 0x00
18 #define IMX95_PAD_DAP_TDI__GPIO3_IO_BIT28 0x0000 0x0204 0x0000 0x05 0x00
19 #define IMX95_PAD_DAP_TDI__LPUART5_RX 0x0000 0x0204 0x0570 0x06 0x00
21 #define IMX95_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x0004 0x0208 0x0614 0x00 0x00
22 #define IMX95_PAD_DAP_TMS_SWDIO__CAN4_TX 0x0004 0x0208 0x0000 0x02 0x00
23 #define IMX95_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO_BIT31 0x0004 0x0208 0x0000 0x04 0x00
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx7ulp-pinfunc.h15 #define IMX7ULP_PAD_PTC0__PTC0 0x0000 0x0000 0x1 0x0
16 #define IMX7ULP_PAD_PTC0__TRACE_D15 0x0000 0x0000 0xa 0x0
17 #define IMX7ULP_PAD_PTC0__LPUART4_CTS_B 0x0000 0x0244 0x4 0x1
18 #define IMX7ULP_PAD_PTC0__LPI2C4_SCL 0x0000 0x0278 0x5 0x1
19 #define IMX7ULP_PAD_PTC0__TPM4_CLKIN 0x0000 0x0298 0x6 0x1
20 #define IMX7ULP_PAD_PTC0__FB_AD0 0x0000 0x0000 0x9 0x0
21 #define IMX7ULP_PAD_PTC1__PTC1 0x0004 0x0000 0x1 0x0
22 #define IMX7ULP_PAD_PTC1__TRACE_D14 0x0004 0x0000 0xa 0x0
23 #define IMX7ULP_PAD_PTC1__LPUART4_RTS_B 0x0004 0x0000 0x4 0x0
24 #define IMX7ULP_PAD_PTC1__LPI2C4_SDA 0x0004 0x027c 0x5 0x1
[all …]
H A Dimx6ul-pinfunc.h13 #define MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x0014 0x02a0 0x0000 5 0
14 #define MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x0018 0x02a4 0x0000 5 0
16 #define MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x001c 0x02a8 0x0000 5 0
17 #define MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x0020 0x02ac 0x0000 5 0
18 #define MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0024 0x02b0 0x0000 5 0
19 #define MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0028 0x02b4 0x0000 5 0
20 #define MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x002c 0x02b8 0x0000 5 0
21 #define MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0030 0x02bc 0x0000 5 0
22 #define MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0034 0x02c0 0x0000 5 0
23 #define MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0038 0x02c4 0x0000 5 0
[all …]
H A Dimx6ull-pinfunc.h16 #define MX6UL_PAD_UART5_TX_DATA__UART5_DTE_RX 0x00BC 0x0348 0x0644 0x0 0x6
18 #define MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x00C0 0x034C 0x0644 0x0 0x7
20 #define MX6UL_PAD_ENET1_RX_EN__UART5_DCE_RTS 0x00CC 0x0358 0x0640 0x1 0x5
22 #define MX6UL_PAD_ENET1_TX_DATA0__UART5_DTE_RTS 0x00D0 0x035C 0x0640 0x1 0x6
24 #define MX6UL_PAD_CSI_DATA02__UART5_DCE_RTS 0x01EC 0x0478 0x0640 0x8 0x7
27 #define MX6ULL_PAD_UART1_TX_DATA__UART5_DCE_TX 0x0084 0x0310 0x0000 0x9 0x0
28 #define MX6ULL_PAD_UART1_TX_DATA__UART5_DTE_RX 0x0084 0x0310 0x0644 0x9 0x4
29 #define MX6ULL_PAD_UART1_RX_DATA__UART5_DCE_RX 0x0088 0x0314 0x0644 0x9 0x5
30 #define MX6ULL_PAD_UART1_RX_DATA__UART5_DTE_TX 0x0088 0x0314 0x0000 0x9 0x0
31 #define MX6ULL_PAD_UART1_CTS_B__UART5_DCE_CTS 0x008C 0x0318 0x0000 0x9 0x0
[all …]
H A Dimx6sll-pinfunc.h15 #define MX6SLL_PAD_WDOG_B__WDOG1_B 0x0014 0x02DC 0x0000 0x0 0x0
16 #define MX6SLL_PAD_WDOG_B__WDOG1_RESET_B_DEB 0x0014 0x02DC 0x0000 0x1 0x0
17 #define MX6SLL_PAD_WDOG_B__UART5_RI_B 0x0014 0x02DC 0x0000 0x2 0x0
18 #define MX6SLL_PAD_WDOG_B__GPIO3_IO18 0x0014 0x02DC 0x0000 0x5 0x0
19 #define MX6SLL_PAD_REF_CLK_24M__XTALOSC_REF_CLK_24M 0x0018 0x02E0 0x0000 0x0 0x0
20 #define MX6SLL_PAD_REF_CLK_24M__I2C3_SCL 0x0018 0x02E0 0x068C 0x1 0x0
21 #define MX6SLL_PAD_REF_CLK_24M__PWM3_OUT 0x0018 0x02E0 0x0000 0x2 0x0
22 #define MX6SLL_PAD_REF_CLK_24M__USB_OTG2_ID 0x0018 0x02E0 0x0560 0x3 0x0
23 #define MX6SLL_PAD_REF_CLK_24M__CCM_PMIC_READY 0x0018 0x02E0 0x05AC 0x4 0x0
24 #define MX6SLL_PAD_REF_CLK_24M__GPIO3_IO21 0x0018 0x02E0 0x0000 0x5 0x0
[all …]
/freebsd/tools/test/iconv/ref/
H A DCP12581 0x0000 = 0x0000
2 0x0001 = 0x0001
3 0x0002 = 0x0002
4 0x0003 = 0x0003
5 0x0004 = 0x0004
6 0x0005 = 0x0005
7 0x0006 = 0x0006
8 0x0007 = 0x0007
9 0x0008 = 0x0008
10 0x0009 = 0x0009
[all …]
H A DTCVN5712-11 0x0000 = 0x0000
2 0x0001 = 0x0000
3 0x0002 = 0x1EE4
4 0x0003 = 0x0003
5 0x0004 = 0x1EEA
6 0x0005 = 0x1EEC
7 0x0006 = 0x1EEE
8 0x0007 = 0x0007
9 0x0008 = 0x0008
10 0x0009 = 0x0009
[all …]
/freebsd/contrib/bearssl/src/ec/
H A Dec_c25519_i15.c34 0x0110,
35 0x7FED, 0x7FFF, 0x7FFF, 0x7FFF, 0x7FFF, 0x7FFF, 0x7FFF, 0x7FFF,
36 0x7FFF, 0x7FFF, 0x7FFF, 0x7FFF, 0x7FFF, 0x7FFF, 0x7FFF, 0x7FFF,
37 0x7FFF
40 #define P0I 0x4A1B
43 0x0110,
44 0x0169, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
45 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
46 0x0000
63 for (u = 0; u < sizeof tmp; u ++) {
[all …]
/freebsd/share/i18n/csmapper/TCVN/
H A DTCVN5712-1%UCS.src5 SRC_ZONE 0x0000-0xF3FF
7 DST_ILSEQ 0xFFFE
46 0x0000 = 0x0000
47 0x0001 = 0x0000
48 0x0001 = 0x00DA
49 0x0002 = 0x1EE4
50 0x0003 = 0x0003
51 0x0004 = 0x1EEA
52 0x0005 = 0x1EEC
53 0x0006 = 0x1EEE
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/ti/
H A Dk3-am642-evm-icssg1-dualemac.dtso24 #size-cells = <0>;
26 mdio@0 {
27 reg = <0x0>;
29 #size-cells = <0>;
43 AM64X_IOPAD(0x0108, PIN_INPUT, 2) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */
44 AM64X_IOPAD(0x010c, PIN_INPUT, 2) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */
45 AM64X_IOPAD(0x0110, PIN_INPUT, 2) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */
46 AM64X_IOPAD(0x0114, PIN_INPUT, 2) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */
47 AM64X_IOPAD(0x0120, PIN_INPUT, 2) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */
48 AM64X_IOPAD(0x0118, PIN_INPUT, 2) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */
[all …]
H A Dk3-am642-evm-icssg1-dualemac-mii.dtso23 #size-cells = <0>;
25 mdio@0 {
26 reg = <0x0>;
28 #size-cells = <0>;
40 AM64X_IOPAD(0x00f8, PIN_INPUT, 1) /* (V9) PRG1_PRU0_GPO16.PR1_MII_MT0_CLK */
41 AM64X_IOPAD(0x00f4, PIN_OUTPUT, 0) /* (Y9) PRG1_PRU0_GPO15.PR1_MII0_TXEN */
42 AM64X_IOPAD(0x00f0, PIN_OUTPUT, 0) /* (AA9) PRG1_PRU0_GPO14.PR1_MII0_TXD3 */
43 AM64X_IOPAD(0x00ec, PIN_OUTPUT, 0) /* (W9) PRG1_PRU0_GPO13.PR1_MII0_TXD2 */
44 AM64X_IOPAD(0x00e8, PIN_OUTPUT, 0) /* (U9) PRG1_PRU0_GPO12.PR1_MII0_TXD1 */
45 AM64X_IOPAD(0x00e4, PIN_OUTPUT, 0) /* (AA8) PRG1_PRU0_GPO11.PR1_MII0_TXD0 */
[all …]
/freebsd/sys/contrib/device-tree/Bindings/clock/ti/
H A Dmux.txt16 0 foo_clock
38 - #clock-cells : from common clock binding; shall be set to 0.
45 0 if not present
57 #clock-cells = <0>;
60 reg = <0x0110>;
65 #clock-cells = <0>;
69 reg = <0x0108>;
73 #clock-cells = <0>;
77 reg = <0x02d8>;
H A Dti,mux-clock.yaml25 0 foo_clock
50 const: 0
65 default: 0
107 #size-cells = <0>;
111 reg = <0x0110>;
112 #clock-cells = <0>;
120 reg = <0x0120>;
121 #clock-cells = <0>;
/freebsd/share/i18n/csmapper/CP/
H A DCP1163%UCS.src30 SRC_ZONE 0x00-0xFF
32 DST_ILSEQ 0xFFFE
43 0x00 - 0xA3 = 0x0000 -
44 0xA4 = 0x20AC
45 0xA5 - 0xA7 = 0x00A5 -
46 0xA8 = 0x0153
47 0xA9 - 0xB3 = 0x00A9 -
48 0xB4 = 0x0178
49 0xB5 - 0xB7 = 0x00B5 -
50 0xB8 = 0x0152
[all …]
H A DCP852%UCS.src5 SRC_ZONE 0x00-0xFF
7 DST_ILSEQ 0xFFFE
26 # Column #2 is the Unicode (in hex as 0xXXXX)
31 0x00 - 0x7F = 0x0000 -
32 0x80 = 0x00C7
33 0x81 = 0x00FC
34 0x82 = 0x00E9
35 0x83 = 0x00E2
36 0x84 = 0x00E4
37 0x85 = 0x016F
[all …]
H A DCP1129%UCS.src30 SRC_ZONE 0x00-0xFF
32 DST_ILSEQ 0xFFFE
43 0x00 - 0x9F = 0x0000 -
44 0xA0 = 0x00A0
45 0xA1 = 0x00A1
46 0xA2 = 0x00A2
47 0xA3 = 0x00A3
48 0xA4 = 0x00A4
49 0xA5 = 0x00A5
50 0xA6 = 0x00A6
[all …]
H A DUCS%CP870.src5 SRC_ZONE 0x0000 - 0x02DD
7 DST_INVALID 0xB3
14 0x0000 = 0x00
15 0x0001 = 0x01
16 0x0002 = 0x02
17 0x0003 = 0x03
18 0x0004 = 0x04
19 0x0005 = 0x05
20 0x0006 = 0x06
21 0x0007 = 0x07
[all …]
H A DCP870%UCS.src5 SRC_ZONE 0x00 - 0xFF
7 DST_ILSEQ 0xFFFE
14 0x00 = 0x0000
15 0x01 = 0x0001
16 0x02 = 0x0002
17 0x03 = 0x0003
18 0x04 = 0x0004
19 0x05 = 0x0005
20 0x06 = 0x0006
21 0x07 = 0x0007
[all …]
/freebsd/sys/dev/qcom_qup/
H A Dqcom_qup_reg.h31 #define QUP_CONFIG 0x0000
32 #define QUP_CONFIG_N 0x001f
42 #define QUP_STATE 0x0004
44 #define QUP_STATE_RESET 0
50 #define QUP_IO_M_MODES 0x0008
51 #define QUP_IO_M_OUTPUT_BLOCK_SIZE_MASK 0x3
52 #define QUP_IO_M_OUTPUT_BLOCK_SIZE_SHIFT 0
54 #define QUP_IO_M_OUTPUT_FIFO_SIZE_MASK 0x7
57 #define QUP_IO_M_INPUT_BLOCK_SIZE_MASK 0x3
60 #define QUP_IO_M_INPUT_FIFO_SIZE_MASK 0x7
[all …]
/freebsd/sys/contrib/dev/mediatek/mt76/
H A Dsdio.h12 #define MCR_WCIR 0x0000
13 #define MCR_WHLPCR 0x0004
18 #define WHLPCR_INT_EN_SET BIT(0)
20 #define MCR_WSDIOCSR 0x0008
21 #define MCR_WHCR 0x000C
32 #define MCR_WHISR 0x0010
33 #define MCR_WHIER 0x0014
40 #define WHIER_TX_DONE_INT_EN BIT(0)
47 #define MCR_WASR 0x0020
48 #define MCR_WSICR 0x0024
[all …]
/freebsd/share/i18n/csmapper/ISO-8859/
H A DISO-8859-10%UCS.src5 SRC_ZONE 0x00-0xFF
7 DST_ILSEQ 0xFFFE
44 # Column #1 is the ISO/IEC 8859-10 code (in hex as 0xXX)
45 # Column #2 is the Unicode (in hex as 0xXXXX)
52 # 1.1 corrected mistake in mapping of 0xA4
61 0x00-0x7F = 0x00-
62 0x80 = 0x0080
63 0x81 = 0x0081
64 0x82 = 0x0082
65 0x83 = 0x0083
[all …]
H A DISO-8859-16%UCS.src5 SRC_ZONE 0x00-0xFF
7 DST_ILSEQ 0xFFFE
44 # Column #1 is the ISO/IEC 8859-16 code (in hex as 0xXX)
45 # Column #2 is the Unicode (in hex as 0xXXXX)
57 0x00-0x7F = 0x00-
58 0x80 = 0x0080
59 0x81 = 0x0081
60 0x82 = 0x0082
61 0x83 = 0x0083
62 0x84 = 0x0084
[all …]
H A DISO-8859-2%UCS.src5 SRC_ZONE 0x00-0xFF
7 DST_ILSEQ 0xFFFE
44 # Column #1 is the ISO/IEC 8859-2 code (in hex as 0xXX)
45 # Column #2 is the Unicode (in hex as 0xXXXX)
61 0x00-0x7F = 0x00-
62 0x80 = 0x0080
63 0x81 = 0x0081
64 0x82 = 0x0082
65 0x83 = 0x0083
66 0x84 = 0x0084
[all …]
H A DISO-8859-4%UCS.src5 SRC_ZONE 0x00-0xFF
7 DST_ILSEQ 0xFFFE
44 # Column #1 is the ISO/IEC 8859-4 code (in hex as 0xXX)
45 # Column #2 is the Unicode (in hex as 0xXXXX)
61 0x00-0x7F = 0x00-
62 0x80 = 0x0080
63 0x81 = 0x0081
64 0x82 = 0x0082
65 0x83 = 0x0083
66 0x84 = 0x0084
[all …]

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