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/linux/arch/powerpc/platforms/83xx/
H A Dmpc83xx.h8 #define MPC83XX_SCCR_OFFS 0xA08
9 #define MPC83XX_SCCR_USB_MASK 0x00f00000
10 #define MPC83XX_SCCR_USB_MPHCM_11 0x00c00000
11 #define MPC83XX_SCCR_USB_MPHCM_01 0x00400000
12 #define MPC83XX_SCCR_USB_MPHCM_10 0x00800000
13 #define MPC83XX_SCCR_USB_DRCM_11 0x00300000
14 #define MPC83XX_SCCR_USB_DRCM_01 0x00100000
15 #define MPC83XX_SCCR_USB_DRCM_10 0x00200000
16 #define MPC8315_SCCR_USB_MASK 0x00c00000
17 #define MPC8315_SCCR_USB_DRCM_11 0x00c00000
[all …]
/linux/drivers/media/pci/cx18/
H A Dcx18-i2c.c18 #define CX18_REG_I2C_1_WR 0xf15000
19 #define CX18_REG_I2C_1_RD 0xf15008
20 #define CX18_REG_I2C_2_WR 0xf25100
21 #define CX18_REG_I2C_2_RD 0xf25108
23 #define SETSCL_BIT 0x0001
24 #define SETSDL_BIT 0x0002
25 #define GETSCL_BIT 0x0004
26 #define GETSDL_BIT 0x0008
28 #define CX18_CS5345_I2C_ADDR 0x4c
29 #define CX18_Z8F0811_IR_TX_I2C_ADDR 0x70
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dmsm8992-lg-h815.dts26 qcom,msm-id = <0xfb 0x0>;
27 qcom,pmic-id = <0x10009 0x1000a 0x0 0x0>;
28 qcom,board-id = <0xb64 0x0>;
39 reg = <0x0 0x06000000 0x0 0x00001000>;
45 reg = <0x0 0x0ff00000 0x0 0x00100000>;
46 console-size = <0x20000>;
47 pmsg-size = <0x20000>;
48 record-size = <0x10000>;
49 ecc-size = <0x10>;
53 reg = <0x0 0x03400000 0x0 0x00c00000>;
[all …]
/linux/drivers/usb/gadget/udc/
H A Dfsl_qe_udc.h18 #define PORT_CPM 0
24 #define USB_MAX_CTRL_PAYLOAD 0x4000
31 #define USB_DIR_BOTH 0x88
32 #define R_BUF_MAXSIZE 0x800
36 #define USB_MODE_EN 0x01
37 #define USB_MODE_HOST 0x02
38 #define USB_MODE_TEST 0x04
39 #define USB_MODE_SFTE 0x08
40 #define USB_MODE_RESUME 0x40
41 #define USB_MODE_LSS 0x80
[all …]
/linux/arch/powerpc/boot/dts/
H A Dbluestone.dts16 dcr-parent = <&{/cpus/cpu@0}>;
26 #size-cells = <0>;
28 cpu@0 {
31 reg = <0x00000000>;
32 clock-frequency = <0>; /* Filled in by U-Boot */
33 timebase-frequency = <0>; /* Filled in by U-Boot */
46 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
52 cell-index = <0>;
53 dcr-reg = <0x0c0 0x009>;
54 #address-cells = <0>;
[all …]
H A Dstorcenter.dts30 #size-cells = <0>;
32 PowerPC,8241@0 {
34 reg = <0>;
37 bus-frequency = <0>; /* from bootwrapper */
47 reg = <0x00000000 0x04000000>; /* 64MB @ 0x0 */
55 store-gathering = <0>; /* 0 == off, !0 == on */
56 ranges = <0x0 0xfc000000 0x100000>;
57 reg = <0xfc000000 0x100000>; /* EUMB */
58 bus-frequency = <0>; /* fixed by loader */
62 #size-cells = <0>;
[all …]
H A Damigaone.dts20 #size-cells = <0>;
22 cpu@0 {
24 reg = <0>;
29 timebase-frequency = <0>; // 33.3 MHz, from U-boot
30 clock-frequency = <0>; // From U-boot
31 bus-frequency = <0>; // From U-boot
37 reg = <0 0>; // From U-boot
44 bus-range = <0 0xff>;
45 ranges = <0x01000000 0 0x00000000 0xfe000000 0 0x00c00000 // PCI I/O
46 0x02000000 0 0x80000000 0x80000000 0 0x7d000000 // PCI memory
[all …]
/linux/Documentation/devicetree/bindings/bus/
H A Dqcom,ssbi.yaml50 reg = <0x00c00000 0x1000>;
60 #size-cells = <0>;
/linux/drivers/net/ethernet/ibm/emac/
H A Dmal.h37 #define MAL_CFG 0x00
38 #define MAL_CFG_SR 0x80000000
39 #define MAL_CFG_PLBB 0x00004000
40 #define MAL_CFG_OPBBL 0x00000080
41 #define MAL_CFG_EOPIE 0x00000004
42 #define MAL_CFG_LEA 0x00000002
43 #define MAL_CFG_SD 0x00000001
46 #define MAL1_CFG_PLBP_MASK 0x00c00000
47 #define MAL1_CFG_PLBP_10 0x00800000
48 #define MAL1_CFG_GA 0x00200000
[all …]
H A Demac.h103 #define EMAC_MR0_RXI 0x80000000
104 #define EMAC_MR0_TXI 0x40000000
105 #define EMAC_MR0_SRST 0x20000000
106 #define EMAC_MR0_TXE 0x10000000
107 #define EMAC_MR0_RXE 0x08000000
108 #define EMAC_MR0_WKE 0x04000000
111 #define EMAC_MR1_FDE 0x80000000
112 #define EMAC_MR1_ILE 0x40000000
113 #define EMAC_MR1_VLE 0x20000000
114 #define EMAC_MR1_EIFC 0x10000000
[all …]
/linux/drivers/dma/
H A Dfsldma.h19 #define FSL_DMA_MR_CS 0x00000001
20 #define FSL_DMA_MR_CC 0x00000002
21 #define FSL_DMA_MR_CA 0x00000008
22 #define FSL_DMA_MR_EIE 0x00000040
23 #define FSL_DMA_MR_XFE 0x00000020
24 #define FSL_DMA_MR_EOLNIE 0x00000100
25 #define FSL_DMA_MR_EOLSIE 0x00000080
26 #define FSL_DMA_MR_EOSIE 0x00000200
27 #define FSL_DMA_MR_CDSM 0x00000010
28 #define FSL_DMA_MR_CTM 0x00000004
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx1-apf9328.dts19 reg = <0x08000000 0x00800000>;
25 pinctrl-0 = <&pinctrl_i2c>;
31 pinctrl-0 = <&pinctrl_uart1>;
38 pinctrl-0 = <&pinctrl_uart2>;
45 pinctrl-0 = <&pinctrl_weim>;
48 nor: flash@0,0 {
50 reg = <0 0x00000000 0x02000000>;
52 fsl,weim-cs-timing = <0x00330e04 0x00000d01>;
59 pinctrl-0 = <&pinctrl_eth>;
61 reg = <4 0x00c00000 0x2>,
[all …]
/linux/drivers/accel/habanalabs/include/gaudi/
H A Dgaudi_packets.h14 #define PACKET_HEADER_PACKET_ID_MASK 0x1F00000000000000ull
17 PACKET_WREG_32 = 0x1,
18 PACKET_WREG_BULK = 0x2,
19 PACKET_MSG_LONG = 0x3,
20 PACKET_MSG_SHORT = 0x4,
21 PACKET_CP_DMA = 0x5,
22 PACKET_REPEAT = 0x6,
23 PACKET_MSG_PROT = 0x7,
24 PACKET_FENCE = 0x8,
25 PACKET_LIN_DMA = 0x9,
[all …]
/linux/drivers/accel/habanalabs/include/gaudi2/
H A Dgaudi2_packets.h14 #define PACKET_HEADER_PACKET_ID_MASK 0x1F00000000000000ull
17 PACKET_WREG_32 = 0x1,
18 PACKET_WREG_BULK = 0x2,
19 PACKET_MSG_LONG = 0x3,
20 PACKET_MSG_SHORT = 0x4,
21 PACKET_CP_DMA = 0x5,
22 PACKET_REPEAT = 0x6,
23 PACKET_MSG_PROT = 0x7,
24 PACKET_FENCE = 0x8,
25 PACKET_LIN_DMA = 0x9,
[all …]
/linux/Documentation/devicetree/bindings/media/
H A Dqcom,msm8996-venus.yaml114 reg = <0x00c00000 0xff000>;
122 iommus = <&venus_smmu 0x00>,
123 <&venus_smmu 0x01>,
124 <&venus_smmu 0x0a>,
125 <&venus_smmu 0x07>,
126 <&venus_smmu 0x0e>,
127 <&venus_smmu 0x0f>,
128 <&venus_smmu 0x08>,
129 <&venus_smmu 0x09>,
130 <&venus_smmu 0x0b>,
[all …]
/linux/drivers/video/fbdev/
H A Dsm712.h23 #define dac_reg (0x3c8)
24 #define dac_val (0x3c9)
31 #define SIZE_SR00_SR04 (0x04 - 0x00 + 1)
32 #define SIZE_SR10_SR24 (0x24 - 0x10 + 1)
33 #define SIZE_SR30_SR75 (0x75 - 0x30 + 1)
34 #define SIZE_SR80_SR93 (0x93 - 0x80 + 1)
35 #define SIZE_SRA0_SRAF (0xAF - 0xA0 + 1)
36 #define SIZE_GR00_GR08 (0x08 - 0x00 + 1)
37 #define SIZE_AR00_AR14 (0x14 - 0x00 + 1)
38 #define SIZE_CR00_CR18 (0x18 - 0x00 + 1)
[all …]
/linux/arch/powerpc/platforms/embedded6xx/
H A Dmpc10x.h24 * Processor: 0x80000000 - 0x807fffff -> PCI I/O: 0x00000000 - 0x007fffff
25 * Processor: 0xc0000000 - 0xdfffffff -> PCI MEM: 0x00000000 - 0x1fffffff
26 * PCI MEM: 0x80000000 -> Processor System Memory: 0x00000000
29 * Processor: 0xfe000000 - 0xfebfffff -> PCI I/O: 0x00000000 - 0x00bfffff
30 * Processor: 0x80000000 - 0xbfffffff -> PCI MEM: 0x80000000 - 0xbfffffff
31 * PCI MEM: 0x00000000 -> Processor System Memory: 0x00000000
40 #define MPC10X_BRIDGE_8240 ((0x0003 << 16) | PCI_VENDOR_ID_MOTOROLA)
41 #define MPC10X_BRIDGE_107 ((0x0004 << 16) | PCI_VENDOR_ID_MOTOROLA)
42 #define MPC10X_BRIDGE_8245 ((0x0006 << 16) | PCI_VENDOR_ID_MOTOROLA)
49 #define MPC10X_MAPA_CNFG_ADDR 0x80000cf8
[all …]
/linux/arch/sh/kernel/cpu/sh4a/
H A Dsetup-sh7780.c25 DEFINE_RES_MEM(0xffe00000, 0x100),
26 DEFINE_RES_IRQ(evt2irq(0x700)),
31 .id = 0,
46 DEFINE_RES_MEM(0xffe10000, 0x100),
47 DEFINE_RES_IRQ(evt2irq(0xb80)),
65 DEFINE_RES_MEM(0xffd80000, 0x30),
66 DEFINE_RES_IRQ(evt2irq(0x580)),
67 DEFINE_RES_IRQ(evt2irq(0x5a0)),
68 DEFINE_RES_IRQ(evt2irq(0x5c0)),
73 .id = 0,
[all …]
H A Dsetup-sh7770.c22 DEFINE_RES_MEM(0xff923000, 0x100),
23 DEFINE_RES_IRQ(evt2irq(0x9a0)),
28 .id = 0,
42 DEFINE_RES_MEM(0xff924000, 0x100),
43 DEFINE_RES_IRQ(evt2irq(0x9c0)),
62 DEFINE_RES_MEM(0xff925000, 0x100),
63 DEFINE_RES_IRQ(evt2irq(0x9e0)),
82 DEFINE_RES_MEM(0xff926000, 0x100),
83 DEFINE_RES_IRQ(evt2irq(0xa00)),
102 DEFINE_RES_MEM(0xff927000, 0x100),
[all …]
/linux/drivers/staging/rtl8712/
H A Drtl8712_xmit.c73 case 0: in r8712_txframes_sta_ac_pending()
84 u32 addr = 0; in get_ff_hwaddr()
95 case 0: in get_ff_hwaddr()
111 case 0x10: in get_ff_hwaddr()
112 case 0x11: in get_ff_hwaddr()
113 case 0x12: in get_ff_hwaddr()
114 case 0x13: in get_ff_hwaddr()
123 case 0: in get_ff_hwaddr()
135 case 0x10: in get_ff_hwaddr()
136 case 0x11: in get_ff_hwaddr()
[all …]
/linux/drivers/net/wireless/ti/wl18xx/
H A Dreg.h11 #define WL18XX_REGISTERS_BASE 0x00800000
12 #define WL18XX_CODE_BASE 0x00000000
13 #define WL18XX_DATA_BASE 0x00400000
14 #define WL18XX_DOUBLE_BUFFER_BASE 0x00600000
15 #define WL18XX_MCU_KEY_SEARCH_BASE 0x00700000
16 #define WL18XX_PHY_BASE 0x00900000
17 #define WL18XX_TOP_OCP_BASE 0x00A00000
18 #define WL18XX_PACKET_RAM_BASE 0x00B00000
19 #define WL18XX_HOST_BASE 0x00C00000
21 #define WL18XX_REGISTERS_DOWN_SIZE 0x0000B000
[all …]
/linux/arch/arm/boot/dts/marvell/
H A Darmada-385-db-ap.dts26 reg = <0x00000000 0x80000000>; /* 2GB */
30 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
31 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
32 MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
33 MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
34 MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
39 pinctrl-0 = <&i2c0_pins>;
54 pinctrl-0 = <&mdio_pins>;
72 pinctrl-0 = <&uart0_pins>;
82 pinctrl-0 = <&uart1_pins>;
[all …]
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvpe_6_1_fw_if.h32 VPE_CMD_OPCODE_NOP = 0x0,
33 VPE_CMD_OPCODE_VPE_DESC = 0x1,
34 VPE_CMD_OPCODE_PLANE_CFG = 0x2,
35 VPE_CMD_OPCODE_VPEP_CFG = 0x3,
36 VPE_CMD_OPCODE_INDIRECT = 0x4,
37 VPE_CMD_OPCODE_FENCE = 0x5,
38 VPE_CMD_OPCODE_TRAP = 0x6,
39 VPE_CMD_OPCODE_REG_WRITE = 0x7,
40 VPE_CMD_OPCODE_POLL_REGMEM = 0x8,
41 VPE_CMD_OPCODE_COND_EXE = 0x9,
[all …]
/linux/sound/soc/sh/rcar/
H A Dsrc.c51 for ((i) = 0; \
69 rsnd_mod_write(mod, SRC_SWRSR, 0); in rsnd_src_activation()
76 rsnd_mod_write(mod, SRC_SWRSR, 0); in rsnd_src_halt()
98 return 0; in rsnd_src_convert_rate()
120 unsigned int rate = 0; in rsnd_src_get_rate()
148 0x01800000, /* 6 - 1/6 */
149 0x01000000, /* 6 - 1/4 */
150 0x00c00000, /* 6 - 1/3 */
151 0x00800000, /* 6 - 1/2 */
152 0x00600000, /* 6 - 2/3 */
[all …]
/linux/arch/powerpc/include/asm/
H A Dreg_booke.h23 #define MSR_CM_LG 31 /* Computation Mode (0=32-bit, 1=64-bit) */
48 #define SPRN_DECAR 0x036 /* Decrementer Auto Reload Register */
49 #define SPRN_IVPR 0x03F /* Interrupt Vector Prefix Register */
50 #define SPRN_USPRG0 0x100 /* User Special Purpose Register General 0 */
51 #define SPRN_SPRG3R 0x103 /* Special Purpose Register General 3 Read */
52 #define SPRN_SPRG4R 0x104 /* Special Purpose Register General 4 Read */
53 #define SPRN_SPRG5R 0x105 /* Special Purpose Register General 5 Read */
54 #define SPRN_SPRG6R 0x106 /* Special Purpose Register General 6 Read */
55 #define SPRN_SPRG7R 0x107 /* Special Purpose Register General 7 Read */
56 #define SPRN_SPRG4W 0x114 /* Special Purpose Register General 4 Write */
[all …]

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