Lines Matching +full:0 +full:x00c00000

19 #define FSL_DMA_MR_CS		0x00000001
20 #define FSL_DMA_MR_CC		0x00000002
21 #define FSL_DMA_MR_CA		0x00000008
22 #define FSL_DMA_MR_EIE		0x00000040
23 #define FSL_DMA_MR_XFE		0x00000020
24 #define FSL_DMA_MR_EOLNIE	0x00000100
25 #define FSL_DMA_MR_EOLSIE	0x00000080
26 #define FSL_DMA_MR_EOSIE	0x00000200
27 #define FSL_DMA_MR_CDSM		0x00000010
28 #define FSL_DMA_MR_CTM		0x00000004
29 #define FSL_DMA_MR_EMP_EN	0x00200000
30 #define FSL_DMA_MR_EMS_EN	0x00040000
31 #define FSL_DMA_MR_DAHE		0x00002000
32 #define FSL_DMA_MR_SAHE		0x00001000
34 #define FSL_DMA_MR_SAHTS_MASK	0x0000C000
35 #define FSL_DMA_MR_DAHTS_MASK	0x00030000
36 #define FSL_DMA_MR_BWC_MASK	0x0f000000
43 #define FSL_DMA_MR_BWC         0x0A000000
46 #define FSL_DMA_MR_EOTIE	0x00000080
47 #define FSL_DMA_MR_PRC_RM	0x00000800
49 #define FSL_DMA_SR_CH		0x00000020
50 #define FSL_DMA_SR_PE		0x00000010
51 #define FSL_DMA_SR_CB		0x00000004
52 #define FSL_DMA_SR_TE		0x00000080
53 #define FSL_DMA_SR_EOSI		0x00000002
54 #define FSL_DMA_SR_EOLSI	0x00000001
55 #define FSL_DMA_SR_EOCDI	0x00000001
56 #define FSL_DMA_SR_EOLNI	0x00000008
58 #define FSL_DMA_SATR_SBPATMU			0x20000000
59 #define FSL_DMA_SATR_STRANSINT_RIO		0x00c00000
60 #define FSL_DMA_SATR_SREADTYPE_SNOOP_READ	0x00050000
61 #define FSL_DMA_SATR_SREADTYPE_BP_IORH		0x00020000
62 #define FSL_DMA_SATR_SREADTYPE_BP_NREAD		0x00040000
63 #define FSL_DMA_SATR_SREADTYPE_BP_MREAD		0x00070000
65 #define FSL_DMA_DATR_DBPATMU			0x20000000
66 #define FSL_DMA_DATR_DTRANSINT_RIO		0x00c00000
67 #define FSL_DMA_DATR_DWRITETYPE_SNOOP_WRITE	0x00050000
68 #define FSL_DMA_DATR_DWRITETYPE_BP_FLUSH	0x00010000
70 #define FSL_DMA_EOL		((u64)0x1)
71 #define FSL_DMA_SNEN		((u64)0x10)
72 #define FSL_DMA_EOSIE		0x8
73 #define FSL_DMA_NLDA_MASK	(~(u64)0x1f)
75 #define FSL_DMA_BCR_MAX_CNT	0x03ffffffu
77 #define FSL_DMA_DGSR_TE		0x80
78 #define FSL_DMA_DGSR_CH		0x20
79 #define FSL_DMA_DGSR_PE		0x10
80 #define FSL_DMA_DGSR_EOLNI	0x08
81 #define FSL_DMA_DGSR_CB		0x04
82 #define FSL_DMA_DGSR_EOSI	0x02
83 #define FSL_DMA_DGSR_EOLSI	0x01
108 	u32 mr;		/* 0x00 - Mode Register */
109 	u32 sr;		/* 0x04 - Status Register */
110 	u64 cdar;	/* 0x08 - Current descriptor address register */
111 	u64 sar;	/* 0x10 - Source Address Register */
112 	u64 dar;	/* 0x18 - Destination Address Register */
113 	u32 bcr;	/* 0x20 - Byte Count Register */
114 	u64 ndar;	/* 0x24 - Next Descriptor Address Register */
130 #define FSL_DMA_LITTLE_ENDIAN	0x00000000
131 #define FSL_DMA_BIG_ENDIAN	0x00000001
133 #define FSL_DMA_IP_MASK		0x00000ff0
134 #define FSL_DMA_IP_85XX		0x00000010
135 #define FSL_DMA_IP_83XX		0x00000020
137 #define FSL_DMA_CHAN_PAUSE_EXT	0x00001000
138 #define FSL_DMA_CHAN_START_EXT	0x00002000
146 	RUNNING = 0,