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/linux/Documentation/devicetree/bindings/soc/qcom/
H A Dqcom,geni-se.yaml71 "spi@[0-9a-f]+$":
79 "i2c@[0-9a-f]+$":
84 "serial@[0-9a-f]+$":
108 "spi@[0-9a-f]+$": false
109 "serial@[0-9a-f]+$": false
135 reg = <0 0x008c0000 0 0x6000>;
146 reg = <0 0xa94000 0 0x4000>;
151 pinctrl-0 = <&qup_1_i2c_5_active>;
154 #size-cells = <0>;
159 reg = <0 0xa88000 0 0x7000>;
[all …]
/linux/drivers/media/platform/samsung/exynos4-is/
H A Dfimc-is.h41 #define FIMC_IS_CPU_MEM_SIZE (0xa00000)
43 #define FIMC_IS_REGION_SIZE 0x5000
45 #define FIMC_IS_DEBUG_REGION_OFFSET 0x0084b000
46 #define FIMC_IS_SHARED_REGION_OFFSET 0x008c0000
54 FIMC_IS_EXTRA_SETFILE_SIZE + 0x1000)
55 #define FIMC_IS_EXTRA_FW_SIZE 0x180000
56 #define FIMC_IS_EXTRA_SETFILE_SIZE 0x4b000
111 FIMC_IS_AF_IDLE = 0,
120 FIMC_IS_AF_UNLOCKED = 0,
125 FIMC_IS_AE_UNLOCKED = 0,
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dsdm670.dtsi37 #clock-cells = <0>;
43 #clock-cells = <0>;
50 #size-cells = <0>;
52 cpu0: cpu@0 {
55 reg = <0x0 0x0>;
59 qcom,freq-domain = <&cpufreq_hw 0>;
82 reg = <0x0 0x100>;
86 qcom,freq-domain = <&cpufreq_hw 0>;
[all...]
H A Dsm6350.dtsi35 #clock-cells = <0>;
43 #clock-cells = <0>;
49 #size-cells = <0>;
51 cpu0: cpu@0 {
54 reg = <0x0 0x0>;
55 clocks = <&cpufreq_hw 0>;
60 qcom,freq-domain = <&cpufreq_hw 0>;
84 reg = <0x0 0x10
[all...]
H A Dmsm8996.dtsi30 #clock-cells = <0>;
37 #clock-cells = <0>;
45 #size-cells = <0>;
47 cpu0: cpu@0 {
50 reg = <0x0 0x0>;
54 clocks = <&kryocc 0>;
69 reg = <0x0 0x1>;
73 clocks = <&kryocc 0>;
83 reg = <0x0 0x100>;
102 reg = <0x0 0x101>;
[all …]
H A Dsm8750.dtsi32 #size-cells = <0>;
34 cpu0: cpu@0 {
37 reg = <0x0 0x0>;
40 power-domains = <&cpu_pd0>, <&scmi_dvfs 0>;
53 reg = <0x0 0x100>;
56 power-domains = <&cpu_pd1>, <&scmi_dvfs 0>;
63 reg = <0x0 0x20
[all...]
H A Dsc8180x.dtsi32 #clock-cells = <0>;
38 #clock-cells = <0>;
46 #size-cells = <0>;
48 cpu0: cpu@0 {
51 reg = <0x0 0x0>;
55 qcom,freq-domain = <&cpufreq_hw 0>;
62 clocks = <&cpufreq_hw 0>;
80 reg = <0x0 0x100>;
84 qcom,freq-domain = <&cpufreq_hw 0>;
91 clocks = <&cpufreq_hw 0>;
[all …]
H A Dsm8350.dtsi40 #clock-cells = <0>;
48 #clock-cells = <0>;
54 #size-cells = <0>;
56 cpu0: cpu@0 {
59 reg = <0x0 0x0>;
60 clocks = <&cpufreq_hw 0>;
63 qcom,freq-domain = <&cpufreq_hw 0>;
83 reg = <0x0 0x100>;
84 clocks = <&cpufreq_hw 0>;
87 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dtalos.dtsi30 #size-cells = <0>;
32 cpu0: cpu@0 {
35 reg = <0x0 0x0>;
42 clocks = <&cpufreq_hw 0>;
43 qcom,freq-domain = <&cpufreq_hw 0>;
61 reg = <0x0 0x100>;
68 clocks = <&cpufreq_hw 0>;
69 qcom,freq-domain = <&cpufreq_hw 0>;
[all...]
H A Dsc7180.dtsi67 #clock-cells = <0>;
73 #clock-cells = <0>;
79 #size-cells = <0>;
81 cpu0: cpu@0 {
84 reg = <0x0 0x0>;
85 clocks = <&cpufreq_hw 0>;
96 qcom,freq-domain = <&cpufreq_hw 0>;
113 reg = <0x0 0x100>;
114 clocks = <&cpufreq_hw 0>;
125 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dsm8150.dtsi35 #clock-cells = <0>;
42 #clock-cells = <0>;
50 #size-cells = <0>;
52 cpu0: cpu@0 {
55 reg = <0x0 0x0>;
56 clocks = <&cpufreq_hw 0>;
61 qcom,freq-domain = <&cpufreq_hw 0>;
63 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
[all...]
H A Dsm8450.dtsi40 #clock-cells = <0>;
46 #clock-cells = <0>;
53 #size-cells = <0>;
55 cpu0: cpu@0 {
58 reg = <0x0 0x0>;
63 qcom,freq-domain = <&cpufreq_hw 0>;
65 clocks = <&cpufreq_hw 0>;
82 reg = <0x0 0x100>;
87 qcom,freq-domain = <&cpufreq_hw 0>;
89 clocks = <&cpufreq_hw 0>;
[all …]
H A Dsdm845.dtsi79 #clock-cells = <0>;
86 #clock-cells = <0>;
93 #size-cells = <0>;
95 cpu0: cpu@0 {
98 reg = <0x0 0x0>;
99 clocks = <&cpufreq_hw 0>;
103 qcom,freq-domain = <&cpufreq_hw 0>;
127 reg = <0x0 0x100>;
128 clocks = <&cpufreq_hw 0>;
132 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dsc8280xp.dtsi34 #clock-cells = <0>;
39 #clock-cells = <0>;
46 #size-cells = <0>;
48 cpu0: cpu@0 {
51 reg = <0x0 0x0>;
52 clocks = <&cpufreq_hw 0>;
59 qcom,freq-domain = <&cpufreq_hw 0>;
79 reg = <0x0 0x10
[all...]
H A Dsm8550.dtsi40 #clock-cells = <0>;
45 #clock-cells = <0>;
49 #clock-cells = <0>;
57 #clock-cells = <0>;
67 #size-cells = <0>;
69 cpu0: cpu@0 {
72 reg = <0 0>;
73 clocks = <&cpufreq_hw 0>;
78 qcom,freq-domain = <&cpufreq_hw 0>;
98 reg = <0 0x100>;
[all …]
H A Dsm8250.dtsi81 #clock-cells = <0>;
89 #clock-cells = <0>;
95 #size-cells = <0>;
97 cpu0: cpu@0 {
100 reg = <0x0 0x0>;
101 clocks = <&cpufreq_hw 0>;
108 qcom,freq-domain = <&cpufreq_hw 0>;
110 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
116 cache-size = <0x20000>;
122 cache-size = <0x400000>;
[all …]
H A Dsm8650.dtsi42 #clock-cells = <0>;
47 #clock-cells = <0>;
52 #clock-cells = <0>;
61 #clock-cells = <0>;
71 #size-cells = <0>;
73 cpu0: cpu@0 {
76 reg = <0 0>;
78 clocks = <&cpufreq_hw 0>;
88 qcom,freq-domain = <&cpufreq_hw 0>;
[all...]
H A Dlemans.dtsi35 #clock-cells = <0>;
40 #clock-cells = <0>;
46 #size-cells = <0>;
48 cpu0: cpu@0 {
51 reg = <0x0 0x0>;
55 qcom,freq-domain = <&cpufreq_hw 0>;
81 reg = <0x0 0x100>;
85 qcom,freq-domain = <&cpufreq_hw 0>;
[all...]
H A Dhamoa.dtsi38 #clock-cells = <0>;
44 #clock-cells = <0>;
49 #clock-cells = <0>;
58 #clock-cells = <0>;
68 #size-cells = <0>;
70 cpu0: cpu@0 {
73 reg = <0x0 0x0>;
76 power-domains = <&cpu_pd0>, <&scmi_dvfs 0>;
89 reg = <0x
[all...]