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/linux/drivers/clk/mediatek/
H A Dclk-mt8192.c26 FACTOR_FLAGS(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3, 0),
27 FACTOR_FLAGS(CLK_TOP_MAINPLL_D4, "mainpll_d4", "mainpll", 1, 4, 0),
28 FACTOR_FLAGS(CLK_TOP_MAINPLL_D4_D2, "mainpll_d4_d2", "mainpll_d4", 1, 2, 0),
29 FACTOR_FLAGS(CLK_TOP_MAINPLL_D4_D4, "mainpll_d4_d4", "mainpll_d4", 1, 4, 0),
30 FACTOR_FLAGS(CLK_TOP_MAINPLL_D4_D8, "mainpll_d4_d8", "mainpll_d4", 1, 8, 0),
31 FACTOR_FLAGS(CLK_TOP_MAINPLL_D4_D16, "mainpll_d4_d16", "mainpll_d4", 1, 16, 0),
32 FACTOR_FLAGS(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5, 0),
33 FACTOR_FLAGS(CLK_TOP_MAINPLL_D5_D2, "mainpll_d5_d2", "mainpll_d5", 1, 2, 0),
34 FACTOR_FLAGS(CLK_TOP_MAINPLL_D5_D4, "mainpll_d5_d4", "mainpll_d5", 1, 4, 0),
35 FACTOR_FLAGS(CLK_TOP_MAINPLL_D5_D8, "mainpll_d5_d8", "mainpll_d5", 1, 8, 0),
[all …]
H A Dclk-mt8183.c34 FACTOR_FLAGS(CLK_TOP_SYSPLL_CK, "syspll_ck", "mainpll", 1, 1, 0),
35 FACTOR_FLAGS(CLK_TOP_SYSPLL_D2, "syspll_d2", "syspll_ck", 1, 2, 0),
36 FACTOR_FLAGS(CLK_TOP_SYSPLL_D2_D2, "syspll_d2_d2", "syspll_d2", 1, 2, 0),
37 FACTOR_FLAGS(CLK_TOP_SYSPLL_D2_D4, "syspll_d2_d4", "syspll_d2", 1, 4, 0),
38 FACTOR_FLAGS(CLK_TOP_SYSPLL_D2_D8, "syspll_d2_d8", "syspll_d2", 1, 8, 0),
39 FACTOR_FLAGS(CLK_TOP_SYSPLL_D2_D16, "syspll_d2_d16", "syspll_d2", 1, 16, 0),
40 FACTOR_FLAGS(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll", 1, 3, 0),
41 FACTOR_FLAGS(CLK_TOP_SYSPLL_D3_D2, "syspll_d3_d2", "syspll_d3", 1, 2, 0),
42 FACTOR_FLAGS(CLK_TOP_SYSPLL_D3_D4, "syspll_d3_d4", "syspll_d3", 1, 4, 0),
43 FACTOR_FLAGS(CLK_TOP_SYSPLL_D3_D8, "syspll_d3_d8", "syspll_d3", 1, 8, 0),
[all …]
H A Dclk-mt7986-topckgen.c175 0x000, 0x004, 0x008, 0, 3, 7, 0x1C0, 0),
177 0x000, 0x004, 0x008, 8, 3, 15, 0x1C0, 1),
178 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x000,
179 0x004, 0x008, 16, 3, 23, 0x1C0, 2),
181 0x000, 0x004, 0x008, 24, 3, 31, 0x1C0, 3),
183 MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x010,
184 0x014, 0x018, 0, 2, 7, 0x1C0, 4),
185 MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x010,
186 0x014, 0x018, 8, 2, 15, 0x1C0, 5),
187 MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x010,
[all …]
H A Dclk-mt7981-topckgen.c292 0x000, 0x004, 0x008, 0, 3, 7, 0x1C0, 0),
294 0x000, 0x004, 0x008, 8, 3, 15, 0x1C0, 1),
296 0x000, 0x004, 0x008, 16, 3, 23, 0x1C0, 2),
298 0x000, 0x004, 0x008, 24, 3, 31, 0x1C0, 3),
301 0x010, 0x014, 0x018, 0, 2, 7, 0x1C0, 4),
303 0x010, 0x014, 0x018, 8, 3, 15, 0x1C0, 5),
305 0x010, 0x014, 0x018, 16, 2, 23, 0x1C0, 6),
307 pextp_tl_ck_parents, 0x010, 0x014, 0x018, 24, 2, 31,
308 0x1C0, 7),
311 emmc_208m_parents, 0x020, 0x024, 0x028, 0, 3, 7,
[all …]
/linux/sound/pci/oxygen/
H A Dwm8776.h14 #define WM8776_HPLVOL 0x00
15 #define WM8776_HPRVOL 0x01
16 #define WM8776_HPMASTER 0x02
17 #define WM8776_DACLVOL 0x03
18 #define WM8776_DACRVOL 0x04
19 #define WM8776_DACMASTER 0x05
20 #define WM8776_PHASESWAP 0x06
21 #define WM8776_DACCTRL1 0x07
22 #define WM8776_DACMUTE 0x08
23 #define WM8776_DACCTRL2 0x09
[all …]
H A Dwm8785.h5 #define WM8785_R0 0
11 #define WM8785_MCR_MASK 0x007
12 #define WM8785_MCR_SLAVE 0x000
13 #define WM8785_MCR_MASTER_128 0x001
14 #define WM8785_MCR_MASTER_192 0x002
15 #define WM8785_MCR_MASTER_256 0x003
16 #define WM8785_MCR_MASTER_384 0x004
17 #define WM8785_MCR_MASTER_512 0x005
18 #define WM8785_MCR_MASTER_768 0x006
19 #define WM8785_OSR_MASK 0x018
[all …]
H A Dwm8766.h5 #define WM8766_LDA1 0x00
6 #define WM8766_RDA1 0x01
7 #define WM8766_DAC_CTRL 0x02
8 #define WM8766_INT_CTRL 0x03
9 #define WM8766_LDA2 0x04
10 #define WM8766_RDA2 0x05
11 #define WM8766_LDA3 0x06
12 #define WM8766_RDA3 0x07
13 #define WM8766_MASTDA 0x08
14 #define WM8766_DAC_CTRL2 0x09
[all …]
/linux/drivers/clk/sophgo/
H A Dclk-sg2044.c24 #define DIV_ASSERT BIT(0)
105 return div->initval == 0 ? 1 : div->initval; in sg2044_div_get_reg_div()
190 return 0; in sg2044_div_set_rate()
205 return 0; in sg2044_div_enable()
259 static const u32 sg2044_mux_table[] = {0, 1};
269 int ret = 0; in sg2044_mux_notifier_cb()
274 ret = ops->set_parent(hw, 0); in sg2044_mux_notifier_cb()
461 clk_fpll0_parent, 0,
462 0x044, 16, 8,
468 clk_mpll0_parent, 0,
[all …]
/linux/drivers/gpu/drm/vc4/
H A Dvc4_hdmi_regs.h8 #define VC4_HDMI_PACKET_STRIDE 0x24
11 VC4_INVALID = 0,
183 VC4_HD_REG(HDMI_M_CTL, 0x000c),
184 VC4_HD_REG(HDMI_MAI_CTL, 0x0014),
185 VC4_HD_REG(HDMI_MAI_THR, 0x0018),
186 VC4_HD_REG(HDMI_MAI_FMT, 0x001c),
187 VC4_HD_REG(HDMI_MAI_DATA, 0x0020),
188 VC4_HD_REG(HDMI_MAI_SMP, 0x002c),
189 VC4_HD_REG(HDMI_VID_CTL, 0x0038),
190 VC4_HD_REG(HDMI_CSC_CTL, 0x0040),
[all …]
/linux/drivers/net/ethernet/seeq/
H A Dsgiseeq.h35 #define SEEQ_RSTAT_OVERF 0x001 /* Overflow */
36 #define SEEQ_RSTAT_CERROR 0x002 /* CRC error */
37 #define SEEQ_RSTAT_DERROR 0x004 /* Dribble error */
38 #define SEEQ_RSTAT_SFRAME 0x008 /* Short frame */
39 #define SEEQ_RSTAT_REOF 0x010 /* Received end of frame */
40 #define SEEQ_RSTAT_FIG 0x020 /* Frame is good */
41 #define SEEQ_RSTAT_TIMEO 0x040 /* Timeout, or late receive */
42 #define SEEQ_RSTAT_WHICH 0x080 /* Which status, 1=old 0=new */
43 #define SEEQ_RSTAT_LITTLE 0x100 /* DMA is done in little endian format */
44 #define SEEQ_RSTAT_SDMA 0x200 /* DMA has started */
[all …]
/linux/drivers/phy/qualcomm/
H A Dphy-qcom-qmp-dp-phy.h10 #define QSERDES_DP_PHY_REVISION_ID0 0x000
11 #define QSERDES_DP_PHY_REVISION_ID1 0x004
12 #define QSERDES_DP_PHY_REVISION_ID2 0x008
13 #define QSERDES_DP_PHY_REVISION_ID3 0x00c
14 #define QSERDES_DP_PHY_CFG 0x010
15 #define QSERDES_DP_PHY_CFG_1 0x014
16 #define QSERDES_DP_PHY_PD_CTL 0x018
17 #define QSERDES_DP_PHY_MODE 0x01c
18 #define QSERDES_DP_PHY_AUX_CFG0 0x020
19 #define QSERDES_DP_PHY_AUX_CFG1 0x024
[all …]
H A Dphy-qcom-qmp-qserdes-txrx-v3.h10 #define QSERDES_V3_TX_BIST_MODE_LANENO 0x000
11 #define QSERDES_V3_TX_CLKBUF_ENABLE 0x008
12 #define QSERDES_V3_TX_TX_EMP_POST1_LVL 0x00c
13 #define QSERDES_V3_TX_TX_DRV_LVL 0x01c
14 #define QSERDES_V3_TX_RESET_TSYNC_EN 0x024
15 #define QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN 0x028
16 #define QSERDES_V3_TX_TX_BAND 0x02c
17 #define QSERDES_V3_TX_SLEW_CNTL 0x030
18 #define QSERDES_V3_TX_INTERFACE_SELECT 0x034
19 #define QSERDES_V3_TX_RES_CODE_LANE_TX 0x03c
[all …]
H A Dphy-qcom-qmp-qserdes-txrx-v4.h10 #define QSERDES_V4_TX_BIST_MODE_LANENO 0x000
11 #define QSERDES_V4_TX_BIST_INVERT 0x004
12 #define QSERDES_V4_TX_CLKBUF_ENABLE 0x008
13 #define QSERDES_V4_TX_TX_EMP_POST1_LVL 0x00c
14 #define QSERDES_V4_TX_TX_IDLE_LVL_LARGE_AMP 0x010
15 #define QSERDES_V4_TX_TX_DRV_LVL 0x014
16 #define QSERDES_V4_TX_TX_DRV_LVL_OFFSET 0x018
17 #define QSERDES_V4_TX_RESET_TSYNC_EN 0x01c
18 #define QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN 0x020
19 #define QSERDES_V4_TX_TX_BAND 0x024
[all …]
H A Dphy-qcom-qmp-qserdes-txrx-v5.h11 #define QSERDES_V5_TX_BIST_MODE_LANENO 0x000
12 #define QSERDES_V5_TX_BIST_INVERT 0x004
13 #define QSERDES_V5_TX_CLKBUF_ENABLE 0x008
14 #define QSERDES_V5_TX_TX_EMP_POST1_LVL 0x00c
15 #define QSERDES_V5_TX_TX_IDLE_LVL_LARGE_AMP 0x010
16 #define QSERDES_V5_TX_TX_DRV_LVL 0x014
17 #define QSERDES_V5_TX_TX_DRV_LVL_OFFSET 0x018
18 #define QSERDES_V5_TX_RESET_TSYNC_EN 0x01c
19 #define QSERDES_V5_TX_PRE_STALL_LDO_BOOST_EN 0x020
20 #define QSERDES_V5_TX_TX_BAND 0x024
[all …]
H A Dphy-qcom-qmp-pcs-sgmii.h9 #define QPHY_PCS_PHY_START 0x000
10 #define QPHY_PCS_POWER_DOWN_CONTROL 0x004
11 #define QPHY_PCS_SW_RESET 0x008
12 #define QPHY_PCS_LINE_RESET_TIME 0x00c
13 #define QPHY_PCS_TX_LARGE_AMP_DRV_LVL 0x020
14 #define QPHY_PCS_TX_SMALL_AMP_DRV_LVL 0x028
15 #define QPHY_PCS_PCS_READY_STATUS 0x094
16 #define QPHY_PCS_TX_MID_TERM_CTRL1 0x0d8
17 #define QPHY_PCS_TX_MID_TERM_CTRL2 0x0dc
18 #define QPHY_PCS_SGMII_MISC_CTRL8 0x118
/linux/sound/soc/codecs/
H A Dssm2602.h33 #define SSM2602_LINVOL 0x00
34 #define SSM2602_RINVOL 0x01
35 #define SSM2602_LOUT1V 0x02
36 #define SSM2602_ROUT1V 0x03
37 #define SSM2602_APANA 0x04
38 #define SSM2602_APDIGI 0x05
39 #define SSM2602_PWR 0x06
40 #define SSM2602_IFACE 0x07
41 #define SSM2602_SRATE 0x08
42 #define SSM2602_ACTIVE 0x09
[all …]
/linux/drivers/net/wireless/ath/carl9170/
H A Dhw.h43 #define AR9170_UART_REG_BASE 0x1c0000
46 #define AR9170_UART_REG_RX_BUFFER (AR9170_UART_REG_BASE + 0x000)
47 #define AR9170_UART_REG_TX_HOLDING (AR9170_UART_REG_BASE + 0x004)
48 #define AR9170_UART_REG_FIFO_CONTROL (AR9170_UART_REG_BASE + 0x010)
49 #define AR9170_UART_FIFO_CTRL_RESET_RX_FIFO 0x02
50 #define AR9170_UART_FIFO_CTRL_RESET_TX_FIFO 0x04
52 #define AR9170_UART_REG_LINE_CONTROL (AR9170_UART_REG_BASE + 0x014)
53 #define AR9170_UART_REG_MODEM_CONTROL (AR9170_UART_REG_BASE + 0x018)
54 #define AR9170_UART_MODEM_CTRL_DTR_BIT 0x01
55 #define AR9170_UART_MODEM_CTRL_RTS_BIT 0x02
[all …]
/linux/sound/firewire/dice/
H A Ddice-interface.h24 #define DICE_PRIVATE_SPACE 0xffffe0000000uLL
34 #define DICE_GLOBAL_OFFSET 0x00
35 #define DICE_GLOBAL_SIZE 0x04
36 #define DICE_TX_OFFSET 0x08
37 #define DICE_TX_SIZE 0x0c
38 #define DICE_RX_OFFSET 0x10
39 #define DICE_RX_SIZE 0x14
40 #define DICE_EXT_SYNC_OFFSET 0x18
41 #define DICE_EXT_SYNC_SIZE 0x1c
42 #define DICE_UNUSED2_OFFSET 0x20
[all …]
/linux/arch/mips/boot/dts/mobileye/
H A Deyeq6h-pins.dtsi9 * [0] | MUX_SEL | 0 - GPIO, 1 - alternative func
14 * [13:12] | PUD | pull-up/pull-down. 0, 3 - no, 1 - PD, 2 - PU
27 0x000 0x200 // I2C0_SCL pin
28 0x004 0x200 // I2C0_SDA pin
33 0x008 0x200 // I2C1_SCL pin
34 0x00c 0x200 // I2C1_SDA pin
39 0x080 1 // GPIO_C4__SMA0_MDC pin
40 0x084 1 // GPIO_C5__SMA0_MDIO pin
44 pinctrl-single,pins = <0x0a8 1>; // UART0 pin group
47 pinctrl-single,pins = <0x0a0 1>; // UART1 pin group
[all …]
/linux/arch/arm64/boot/dts/hisilicon/
H A Dhikey960-pinctrl.dtsi18 reg = <0x0 0xe896c000 0x0 0x1f0>;
20 #gpio-range-cells = <0x3>;
21 pinctrl-single,register-width = <0x20>;
22 pinctrl-single,function-mask = <0x7>;
25 &range 0 7 0
26 &range 8 116 0>;
30 0x008 MUX_M1 /* PMU1_SSI */
31 0x00c MUX_M1 /* PMU2_SSI */
32 0x010 MUX_M1 /* PMU_CLKOUT */
33 0x100 MUX_M1 /* PMU_HKADC_SSI */
[all …]
/linux/tools/perf/pmu-events/arch/x86/grandridge/
H A Duncore-io.json4 "Counter": "0,1,2,3",
5 "EventCode": "0x01",
8 "PortMask": "0x000",
13 "Counter": "0,1,2,3",
14 "EventCode": "0xC2",
17 "FCMask": "0x07",
19 "PortMask": "0x0FF",
20 "UMask": "0x4",
25 "Counter": "0,1,2,3",
26 "EventCode": "0xC
2 { global() object
[all...]
/linux/tools/perf/pmu-events/arch/x86/sierraforest/
H A Duncore-io.json4 "Counter": "0,1,2,3",
5 "EventCode": "0x01",
8 "PortMask": "0x000",
13 "Counter": "0,1,2,3",
14 "EventCode": "0xC2",
17 "FCMask": "0x07",
19 "PortMask": "0x0FF",
20 "UMask": "0x4",
25 "Counter": "0,1,2,3",
26 "EventCode": "0xC2",
[all …]
/linux/tools/perf/pmu-events/arch/x86/graniterapids/
H A Duncore-io.json4 "Counter": "0,1,2,3",
5 "EventCode": "0x01",
8 "PortMask": "0x000",
13 "Counter": "0,1,2,3",
14 "EventCode": "0xC2",
17 "FCMask": "0x07",
19 "PortMask": "0x0FF",
20 "UMask": "0x4",
25 "Counter": "0,1,2,3",
26 "EventCode": "0xC2",
[all …]
/linux/arch/mips/include/asm/
H A Dmips-cpc.h33 * Attempt to detect the presence of a Cluster Power Controller. Returns 0 if
60 #define MIPS_CPC_GCB_OFS 0x0000
61 #define MIPS_CPC_CLCB_OFS 0x2000
62 #define MIPS_CPC_COCB_OFS 0x4000
81 CPC_ACCESSOR_RW(32, 0x000, access)
84 CPC_ACCESSOR_RW(32, 0x008, seqdel)
87 CPC_ACCESSOR_RW(32, 0x010, rail)
90 CPC_ACCESSOR_RW(32, 0x018, resetlen)
93 CPC_ACCESSOR_RO(32, 0x020, revision)
96 CPC_ACCESSOR_RW(32, 0x030, pwrup_ctl)
[all …]
/linux/drivers/video/fbdev/via/
H A Daccel.h14 #define MMIO_VGABASE 0x8000
15 #define MMIO_CR_READ (MMIO_VGABASE + 0x3D4)
16 #define MMIO_CR_WRITE (MMIO_VGABASE + 0x3D5)
17 #define MMIO_SR_READ (MMIO_VGABASE + 0x3C4)
18 #define MMIO_SR_WRITE (MMIO_VGABASE + 0x3C5)
21 #define HW_Cursor_ON 0
27 #define VIA_MMIO_BLTBASE 0x200000
28 #define VIA_MMIO_BLTSIZE 0x200000
31 #define VIA_REG_GECMD 0x000
32 #define VIA_REG_GEMODE 0x004
[all …]

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