Lines Matching +full:0 +full:x008
24 #define DIV_ASSERT BIT(0)
105 return div->initval == 0 ? 1 : div->initval; in sg2044_div_get_reg_div()
190 return 0; in sg2044_div_set_rate()
205 return 0; in sg2044_div_enable()
259 static const u32 sg2044_mux_table[] = {0, 1};
269 int ret = 0; in sg2044_mux_notifier_cb()
274 ret = ops->set_parent(hw, 0); in sg2044_mux_notifier_cb()
461 clk_fpll0_parent, 0,
462 0x044, 16, 8,
468 clk_mpll0_parent, 0,
469 0x040, 16, 8,
475 clk_fpll0_parent, 0,
476 0x050, 16, 8,
482 clk_mpll1_parent, 0,
483 0x04c, 16, 8,
489 clk_fpll0_parent, 0,
490 0x058, 16, 8,
496 clk_mpll2_parent, 0,
497 0x054, 16, 8,
503 clk_fpll0_parent, 0,
504 0x070, 16, 8,
510 clk_mpll3_parent, 0,
511 0x06c, 16, 8,
517 clk_fpll0_parent, 0,
518 0x078, 16, 8,
524 clk_mpll4_parent, 0,
525 0x074, 16, 8,
531 clk_fpll0_parent, 0,
532 0x080, 16, 8,
538 clk_mpll5_parent, 0,
539 0x07c, 16, 8,
545 clk_fpll0_parent, 0,
546 0x088, 16, 8,
552 clk_fpll1_parent, 0,
553 0x084, 16, 8,
559 clk_fpll0_parent, 0,
560 0x124, 16, 8,
565 clk_dpll0_parent, 0,
566 0x120, 16, 8,
571 clk_fpll0_parent, 0,
572 0x12c, 16, 8,
577 clk_dpll1_parent, 0,
578 0x128, 16, 8,
583 clk_fpll0_parent, 0,
584 0x134, 16, 8,
589 clk_dpll2_parent, 0,
590 0x130, 16, 8,
595 clk_fpll0_parent, 0,
596 0x13c, 16, 8,
601 clk_dpll3_parent, 0,
602 0x138, 16, 8,
607 clk_fpll0_parent, 0,
608 0x144, 16, 8,
613 clk_dpll4_parent, 0,
614 0x140, 16, 8,
619 clk_fpll0_parent, 0,
620 0x14c, 16, 8,
625 clk_dpll5_parent, 0,
626 0x148, 16, 8,
631 clk_fpll0_parent, 0,
632 0x154, 16, 8,
637 clk_dpll6_parent, 0,
638 0x150, 16, 8,
643 clk_fpll0_parent, 0,
644 0x15c, 16, 8,
649 clk_dpll7_parent, 0,
650 0x158, 16, 8,
655 clk_fpll0_parent, 0,
656 0x048, 16, 8,
665 clk_fpll0_parent, 0,
666 0x118, 16, 8,
675 clk_fpll0_parent, 0,
676 0x11c, 16, 8,
685 clk_div_top_50m_parent, 0,
686 0x0d0, 16, 16,
691 clk_div_top_50m_parent, 0,
692 0x0d4, 16, 16,
697 clk_div_top_50m_parent, 0,
698 0x0d8, 16, 16,
703 clk_div_top_50m_parent, 0,
704 0x0dc, 16, 16,
709 clk_div_top_50m_parent, 0,
710 0x0e0, 16, 16,
715 clk_div_top_50m_parent, 0,
716 0x0e4, 16, 16,
721 clk_div_top_50m_parent, 0,
722 0x0e8, 16, 16,
727 clk_div_top_50m_parent, 0,
728 0x0ec, 16, 16,
733 clk_fpll0_parent, 0,
734 0x064, 16, 8,
739 clk_fpll2_parent, 0,
740 0x068, 16, 8,
745 clk_fpll0_parent, 0,
746 0x05c, 16, 8,
751 clk_fpll0_parent, 0,
752 0x060, 16, 8,
757 clk_fpll1_parent, 0,
758 0x160, 16, 8,
763 clk_fpll0_parent, 0,
764 0x0cc, 16, 8,
769 clk_div_top_axi0_parent, 0,
770 0x0f8, 16, 16,
775 clk_fpll0_parent, 0,
776 0x110, 16, 16,
781 clk_div_top_axi0_parent, 0,
782 0x114, 16, 16,
787 clk_fpll0_parent, 0,
788 0x108, 16, 16,
793 clk_div_top_axi0_parent, 0,
794 0x10c, 16, 16,
799 clk_fpll0_parent, 0,
800 0x0f4, 16, 8,
805 clk_fpll0_parent, 0,
806 0x0fc, 16, 8,
811 clk_fpll0_parent, 0,
812 0x100, 16, 8,
817 clk_fpll0_parent, 0,
818 0x104, 16, 8,
823 clk_fpll0_parent, 0,
824 0x0f0, 16, 8,
836 0x020, 7, sg2044_mux_table, CLK_MUX_READ_ONLY);
846 0x020, 8, sg2044_mux_table, CLK_MUX_READ_ONLY);
856 0x020, 9, sg2044_mux_table, CLK_MUX_READ_ONLY);
866 0x020, 10, sg2044_mux_table, CLK_MUX_READ_ONLY);
876 0x020, 11, sg2044_mux_table, CLK_MUX_READ_ONLY);
886 0x020, 12, sg2044_mux_table, CLK_MUX_READ_ONLY);
896 0x020, 13, sg2044_mux_table, CLK_MUX_READ_ONLY);
906 0x020, 14, sg2044_mux_table, CLK_MUX_READ_ONLY);
916 0x020, 3, sg2044_mux_table, 0);
926 0x020, 2, sg2044_mux_table, 0);
936 0x020, 1, sg2044_mux_table, 0);
946 0x020, 0, sg2044_mux_table, 0);
956 0x020, 4, sg2044_mux_table, 0);
966 0x020, 5, sg2044_mux_table, 0);
976 0x020, 6, sg2044_mux_table, 0);
985 0x000, 0, 0);
994 0x000, 2, 0);
1003 0x000, 3, 0);
1012 0x000, 8, 0);
1021 0x000, 9, 0);
1030 0x000, 10, 0);
1039 0x008, 7, 0);
1048 0x008, 8, 0);
1057 0x008, 9, 0);
1066 0x008, 10, 0);
1075 0x008, 11, 0);
1084 0x008, 12, 0);
1093 0x008, 13, 0);
1102 0x008, 14, 0);
1111 0x000, 1, 0);
1120 0x000, 12, 0);
1129 0x000, 13, 0);
1134 0x008, 5, 0);
1143 0x020, 20, 0);
1148 0x020, 21, 0);
1153 0x020, 22, 0);
1158 0x020, 23, 0);
1163 0x020, 16, 0);
1168 0x020, 17, 0);
1173 0x020, 18, 0);
1178 0x020, 19, 0);
1183 0x008, 6, 0);
1188 0x004, 7, 0);
1197 0x004, 8, 0);
1206 0x004, 9, 0);
1215 0x004, 10, 0);
1224 0x004, 11, 0);
1233 0x004, 12, 0);
1242 0x004, 13, 0);
1251 0x004, 14, 0);
1260 0x004, 15, 0);
1265 0x000, 15, 0);
1274 0x000, 14, 0);
1283 0x000, 6, 0);
1292 0x000, 7, 0);
1301 0x008, 15, 0);
1310 0x000, 4, 0);
1319 0x000, 5, 0);
1328 0x004, 1, 0);
1333 0x004, 2, 0);
1338 0x004, 22, 0);
1343 0x004, 5, 0);
1348 0x004, 23, 0);
1353 0x004, 3, 0);
1362 0x004, 21, 0);
1367 0x004, 20, 0);
1372 0x004, 19, 0);
1381 0x008, 3, 0);
1386 0x008, 2, 0);
1395 0x008, 4, 0);
1404 0x008, 0, 0);
1409 0x004, 31, 0);
1418 0x008, 1, 0);
1427 0x004, 17, 0);
1432 0x004, 18, 0);
1437 0x004, 0, 0);
1446 0x004, 27, 0);
1451 0x004, 28, 0);
1460 0x004, 29, 0);
1469 0x004, 30, 0);
1474 0x004, 26, 0);
1479 0x004, 25, 0);
1484 0x004, 24, 0);
1489 0x004, 6, 0);
1494 0x004, 4, 0);
1503 0x004, 16, 0);
1665 for (i = 0; i < init->num_parents; i++) { in sg2044_clk_fix_init_parent()
1684 for (i = 0; i < desc->num_div; i++) { in sg2044_clk_init_ctrl()
1697 for (i = 0; i < desc->num_mux; i++) { in sg2044_clk_init_ctrl()
1723 if (ret < 0) in sg2044_clk_init_ctrl()
1732 for (i = 0; i < desc->num_gate; i++) { in sg2044_clk_init_ctrl()
1743 parent_hws[0], in sg2044_clk_init_ctrl()
1767 reg = devm_platform_ioremap_resource(pdev, 0); in sg2044_clk_probe()