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/linux/drivers/media/pci/saa7134/
H A Dsaa7134-input.c28 MODULE_PARM_DESC(pinnacle_remote, "Specify Pinnacle PCTV remote: 0=coloured, 1=grey (defaults to 0)…
33 } while (0)
38 } while (0)
53 saa_setb(SAA7134_GPIO_GPSTATUS1, 0x80); in build_key()
54 saa_clearb(SAA7134_GPIO_GPSTATUS1, 0x80); in build_key()
64 return 0; in build_key()
69 input_dbg("build_key gpio=0x%x mask=0x%x data=%d\n", in build_key()
78 0); in build_key()
79 return 0; in build_key()
83 if ((ir->mask_keydown && (0 != (gpio & ir->mask_keydown))) || in build_key()
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/linux/arch/arm/boot/dts/ti/keystone/
H A Dkeystone-k2g-ice.dts18 reg = <0x00000008 0x00000000 0x00000000 0x20000000>;
28 reg = <0x00000008 0x1f800000 0x00000000 0x800000>;
128 <&pca9536 0 GPIO_ACTIVE_HIGH>;
129 linux,axis = <0>; /* ABS_X */
136 pinctrl-0 = <&user_leds>;
223 K2G_CORE_IOPAD(0x11cc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* uart0_rxd.uart0_rxd */
224 K2G_CORE_IOPAD(0x11d0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
230 K2G_CORE_IOPAD(0x1204) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_clk.qspi_clk */
231 K2G_CORE_IOPAD(0x1208) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_rclk.qspi_rclk */
232 K2G_CORE_IOPAD(0x120c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d0.qspi_d0 */
[all …]
H A Dkeystone-k2g-evm.dts17 reg = <0x00000008 0x00000000 0x00000000 0x80000000>;
27 reg = <0x00000008 0x1f800000 0x00000000 0x800000>;
72 #clock-cells = <0>;
76 sound0: sound@0 {
88 simple-audio-card,dai-link@0 {
94 clocks = <&k2g_clks 0x6 1>;
110 clocks = <&k2g_clks 0x6 1>;
125 K2G_CORE_IOPAD(0x11cc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* uart0_rxd.uart0_rxd */
126 K2G_CORE_IOPAD(0x11d0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
132 K2G_CORE_IOPAD(0x1300) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_dat3.mmc0_dat3 */
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/linux/tools/perf/pmu-events/arch/riscv/sifive/u74/
H A Dinstructions.json4 "EventCode": "0x0000100",
9 "EventCode": "0x0000200",
14 "EventCode": "0x0000400",
19 "EventCode": "0x0000800",
24 "EventCode": "0x0001000",
29 "EventCode": "0x0002000",
34 "EventCode": "0x0004000",
39 "EventCode": "0x0008000",
44 "EventCode": "0x0010000",
49 "EventCode": "0x0020000",
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/linux/include/uapi/linux/
H A Dpersonality.h12 UNAME26 = 0x0020000,
13 ADDR_NO_RANDOMIZE = 0x0040000, /* disable randomization of VA space */
14 FDPIC_FUNCPTRS = 0x0080000, /* userspace function ptrs point to descriptors
17 MMAP_PAGE_ZERO = 0x0100000,
18 ADDR_COMPAT_LAYOUT = 0x0200000,
19 READ_IMPLIES_EXEC = 0x0400000,
20 ADDR_LIMIT_32BIT = 0x0800000,
21 SHORT_INODE = 0x1000000,
22 WHOLE_SECONDS = 0x2000000,
23 STICKY_TIMEOUTS = 0x4000000,
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/linux/Documentation/devicetree/bindings/watchdog/
H A Dsnps,dw-wdt.yaml70 default: [0x0001000 0x0002000 0x0004000 0x0008000
71 0x0010000 0x0020000 0x0040000 0x0080000
72 0x0100000 0x0200000 0x0400000 0x0800000
73 0x1000000 0x2000000 0x4000000 0x8000000]
88 reg = <0xffd02000 0x1000>;
89 interrupts = <0 171 4>;
97 reg = <0xffd02000 0x1000>;
98 interrupts = <0 171 4>;
101 snps,watchdog-tops = <0x000000FF 0x000001FF 0x000003FF
102 0x000007FF 0x0000FFFF 0x0001FFFF
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/linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dnv50.c35 return nvkm_rd32(gr->engine.subdev.device, 0x1540); in nv50_gr_units()
48 if (ret == 0) { in nv50_gr_object_bind()
50 nvkm_wo32(*pgpuobj, 0x00, object->oclass); in nv50_gr_object_bind()
51 nvkm_wo32(*pgpuobj, 0x04, 0x00000000); in nv50_gr_object_bind()
52 nvkm_wo32(*pgpuobj, 0x08, 0x00000000); in nv50_gr_object_bind()
53 nvkm_wo32(*pgpuobj, 0x0c, 0x00000000); in nv50_gr_object_bind()
75 if (ret == 0) { in nv50_gr_chan_bind()
100 return 0; in nv50_gr_chan_new()
108 { 0x01, "STACK_UNDERFLOW" },
109 { 0x02, "STACK_MISMATCH" },
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/linux/drivers/net/dsa/ocelot/
H A Dseville_vsc9953.c43 REG(ANA_ADVLEARN, 0x00b500),
44 REG(ANA_VLANMASK, 0x00b504),
46 REG(ANA_ANAGEFIL, 0x00b50c),
47 REG(ANA_ANEVENTS, 0x00b510),
48 REG(ANA_STORMLIMIT_BURST, 0x00b514),
49 REG(ANA_STORMLIMIT_CFG, 0x00b518),
50 REG(ANA_ISOLATED_PORTS, 0x00b528),
51 REG(ANA_COMMUNITY_PORTS, 0x00b52c),
52 REG(ANA_AUTOAGE, 0x00b530),
53 REG(ANA_MACTOPTIONS, 0x00b534),
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H A Dfelix_vsc9959.c31 #define VSC9959_IMDIO_PCI_BAR 0
49 REG(ANA_ADVLEARN, 0x0089a0),
50 REG(ANA_VLANMASK, 0x0089a4),
52 REG(ANA_ANAGEFIL, 0x0089ac),
53 REG(ANA_ANEVENTS, 0x0089b0),
54 REG(ANA_STORMLIMIT_BURST, 0x0089b4),
55 REG(ANA_STORMLIMIT_CFG, 0x0089b8),
56 REG(ANA_ISOLATED_PORTS, 0x0089c8),
57 REG(ANA_COMMUNITY_PORTS, 0x0089cc),
58 REG(ANA_AUTOAGE, 0x0089d0),
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/linux/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x.h42 #define DRV_MODULE_VERSION "1.713.36-0"
43 #define BNX2X_BC_VER 0x040200
77 #define BNX2X_MSG_OFF 0x0
78 #define BNX2X_MSG_MCP 0x0010000 /* was: NETIF_MSG_HW */
79 #define BNX2X_MSG_STATS 0x0020000 /* was: NETIF_MSG_TIMER */
80 #define BNX2X_MSG_NVM 0x0040000 /* was: NETIF_MSG_HW */
81 #define BNX2X_MSG_DMAE 0x0080000 /* was: NETIF_MSG_HW */
82 #define BNX2X_MSG_SP 0x0100000 /* was: NETIF_MSG_INTR */
83 #define BNX2X_MSG_FP 0x0200000 /* was: NETIF_MSG_INTR */
84 #define BNX2X_MSG_IOV 0x0800000
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/linux/drivers/net/ethernet/nvidia/
H A Dforcedeth.c66 #define DEV_NEED_TIMERIRQ 0x0000001 /* set the timer irq flag in the irq mask */
67 #define DEV_NEED_LINKTIMER 0x0000002 /* poll link settings. Relies on the timer irq */
68 #define DEV_HAS_LARGEDESC 0x0000004 /* device supports jumbo frames and needs packet form…
69 #define DEV_HAS_HIGH_DMA 0x0000008 /* device supports 64bit dma */
70 #define DEV_HAS_CHECKSUM 0x0000010 /* device supports tx and rx checksum offloads */
71 #define DEV_HAS_VLAN 0x0000020 /* device supports vlan tagging and striping */
72 #define DEV_HAS_MSI 0x0000040 /* device supports MSI */
73 #define DEV_HAS_MSI_X 0x0000080 /* device supports MSI-X */
74 #define DEV_HAS_POWER_CNTRL 0x0000100 /* device supports power savings */
75 #define DEV_HAS_STATISTICS_V1 0x0000200 /* device supports hw statistics version 1 */
[all …]