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/linux/arch/arm/boot/dts/microchip/
H A Dat91sam9xe.dtsi21 reg = <0x00300000 0x4000>;
24 ranges = <0 0x00300000 0x4000>;
/linux/drivers/accel/habanalabs/include/gaudi/
H A Dgaudi_packets.h14 #define PACKET_HEADER_PACKET_ID_MASK 0x1F00000000000000ull
17 PACKET_WREG_32 = 0x1,
18 PACKET_WREG_BULK = 0x2,
19 PACKET_MSG_LONG = 0x3,
20 PACKET_MSG_SHORT = 0x4,
21 PACKET_CP_DMA = 0x5,
22 PACKET_REPEAT = 0x6,
23 PACKET_MSG_PROT = 0x7,
24 PACKET_FENCE = 0x8,
25 PACKET_LIN_DMA = 0x9,
[all …]
/linux/arch/mips/include/asm/mach-ralink/
H A Drt288x.h15 #define RT2880_SYSC_BASE IOMEM(0x00300000)
17 #define SYSC_REG_CHIP_NAME0 0x00
18 #define SYSC_REG_CHIP_NAME1 0x04
19 #define SYSC_REG_CHIP_ID 0x0c
20 #define SYSC_REG_SYSTEM_CONFIG 0x10
22 #define RT2880_CHIP_NAME0 0x38325452
23 #define RT2880_CHIP_NAME1 0x20203038
25 #define CHIP_ID_ID_MASK 0xff
27 #define CHIP_ID_REV_MASK 0xff
29 #define RT2880_SDRAM_BASE 0x08000000
/linux/sound/pci/
H A Dsis7019.h17 #define SIS_GCR 0x00
18 #define SIS_GCR_MACRO_POWER_DOWN 0x80000000
19 #define SIS_GCR_MODEM_ENABLE 0x00010000
20 #define SIS_GCR_SOFTWARE_RESET 0x00000001
23 #define SIS_GIER 0x04
24 #define SIS_GIER_MODEM_TIMER_IRQ_ENABLE 0x00100000
25 #define SIS_GIER_MODEM_RX_DMA_IRQ_ENABLE 0x00080000
26 #define SIS_GIER_MODEM_TX_DMA_IRQ_ENABLE 0x00040000
27 #define SIS_GIER_AC97_GPIO1_IRQ_ENABLE 0x00020000
28 #define SIS_GIER_AC97_GPIO0_IRQ_ENABLE 0x00010000
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx1.dtsi38 reg = <0x00223000 0x1000>;
42 #size-cells = <0>;
45 cpu@0 {
47 reg = <0>;
59 #clock-cells = <0>;
75 reg = <0x00200000 0x10000>;
80 reg = <0x00202000 0x1000>;
89 reg = <0x00203000 0x1000>;
98 reg = <0x00205000 0x1000>;
109 reg = <0x00206000 0x1000>;
[all …]
/linux/include/linux/regulator/
H A Dmax8973-regulator.h20 #define MAX8973_CONTROL_REMOTE_SENSE_ENABLE 0x00000001
21 #define MAX8973_CONTROL_FALLING_SLEW_RATE_ENABLE 0x00000002
22 #define MAX8973_CONTROL_OUTPUT_ACTIVE_DISCH_ENABLE 0x00000004
23 #define MAX8973_CONTROL_BIAS_ENABLE 0x00000008
24 #define MAX8973_CONTROL_PULL_DOWN_ENABLE 0x00000010
25 #define MAX8973_CONTROL_FREQ_SHIFT_9PER_ENABLE 0x00000020
27 #define MAX8973_CONTROL_CLKADV_TRIP_DISABLED 0x00000000
28 #define MAX8973_CONTROL_CLKADV_TRIP_75mV_PER_US 0x00010000
29 #define MAX8973_CONTROL_CLKADV_TRIP_150mV_PER_US 0x00020000
30 #define MAX8973_CONTROL_CLKADV_TRIP_75mV_PER_US_HIST_DIS 0x00030000
[all …]
/linux/arch/powerpc/platforms/83xx/
H A Dmpc83xx.h8 #define MPC83XX_SCCR_OFFS 0xA08
9 #define MPC83XX_SCCR_USB_MASK 0x00f00000
10 #define MPC83XX_SCCR_USB_MPHCM_11 0x00c00000
11 #define MPC83XX_SCCR_USB_MPHCM_01 0x00400000
12 #define MPC83XX_SCCR_USB_MPHCM_10 0x00800000
13 #define MPC83XX_SCCR_USB_DRCM_11 0x00300000
14 #define MPC83XX_SCCR_USB_DRCM_01 0x00100000
15 #define MPC83XX_SCCR_USB_DRCM_10 0x00200000
16 #define MPC8315_SCCR_USB_MASK 0x00c00000
17 #define MPC8315_SCCR_USB_DRCM_11 0x00c00000
[all …]
/linux/arch/arm/mach-s3c/
H A Dmap-base.h13 /* Fit all our registers in at 0xF6000000 upwards, trying to use as
21 #define S3C_ADDR_BASE 0xF6000000
29 #define S3C_VA_IRQ S3C_ADDR(0x00000000) /* irq controller(s) */
30 #define S3C_VA_SYS S3C_ADDR(0x00100000) /* system control */
31 #define S3C_VA_MEM S3C_ADDR(0x00200000) /* memory control */
32 #define S3C_VA_TIMER S3C_ADDR(0x00300000) /* timer block */
33 #define S3C_VA_WATCHDOG S3C_ADDR(0x00400000) /* watchdog */
34 #define S3C_VA_UART S3C_ADDR(0x01000000) /* UART */
46 #define S3C_ADDR_CPU(x) S3C_ADDR(0x00500000 + (x))
/linux/arch/arm/boot/dts/intel/ixp/
H A Dintel-ixp42x-welltech-epbx100.dts16 memory@0 {
19 reg = <0x00000000 0x4000000>;
23 bootargs = "console=ttyS0,115200n8 root=/dev/ram0 initrd=0x00800000,9M";
33 flash@0,0 {
39 reg = <0 0x00000000 0x1000000>;
46 partition@0 {
48 reg = <0x00000000 0x00080000>;
53 reg = <0x00080000 0x00100000>;
58 reg = <0x00180000 0x00300000>;
63 reg = <0x00480000 0x00b60000>;
[all …]
/linux/arch/arm/boot/dts/marvell/
H A Dkirkwood-ts219.dtsi8 reg = <0x00000000 0x20000000>;
23 reg = <0x30>;
34 reg = <0x12100 0x100>;
40 m25p128@0 {
44 reg = <0>;
46 mode = <0>;
48 partition@0 {
49 reg = <0x00000000 0x00080000>;
54 reg = <0x00200000 0x00200000>;
59 reg = <0x00400000 0x00900000>;
[all …]
/linux/arch/sh/include/cpu-sh4/cpu/
H A Ddma-register.h17 #define CHCR_TS_LOW_MASK 0x00000018
19 #define CHCR_TS_HIGH_MASK 0
20 #define CHCR_TS_HIGH_SHIFT 0
26 #define CHCR_TS_LOW_MASK 0x00000018
28 #define CHCR_TS_HIGH_MASK 0x00300000
34 #define CHCR_TS_LOW_MASK 0x00000018
36 #define CHCR_TS_HIGH_MASK 0x00100000
42 XMIT_SZ_8BIT = 0,
48 XMIT_SZ_128BIT_BLK = 0xb,
49 XMIT_SZ_256BIT_BLK = 0xc,
[all …]
/linux/arch/mips/include/asm/mach-rc32434/
H A Ddma.h17 #define DMA0_BASE_ADDR 0x18040000
31 #define DMA_DESC_COUNT_BIT 0
32 #define DMA_DESC_COUNT_MSK 0x0003ffff
34 #define DMA_DESC_DS_MSK 0x00300000
37 #define DMA_DESC_DEV_CMD_MSK 0x01c00000
40 #define DMA_DESC_DEV_CMD_BYTE 0
71 #define DMA_CHAN_RUN_BIT (1 << 0)
74 #define DMA_CHAN_MODE_MSK 0x0000000c
75 #define DMA_CHAN_MODE_AUTO 0
82 #define DMA_STAT_FINI (1 << 0)
[all …]
H A Dddr.h49 #define DDR0_PHYS_ADDR 0x18018000
52 #define DDR_MASK 0xffff0000
58 #define RC32434_DDR0_ATA_MSK 0x000000E0
60 #define RC32434_DDR0_DBW_MSK 0x00000100
62 #define RC32434_DDR0_WR_MSK 0x00000600
64 #define RC32434_DDR0_PS_MSK 0x00001800
66 #define RC32434_DDR0_DTYPE_MSK 0x0000e000
68 #define RC32434_DDR0_RFC_MSK 0x000f0000
70 #define RC32434_DDR0_RP_MSK 0x00300000
72 #define RC32434_DDR0_AP_MSK 0x00400000
[all …]
/linux/drivers/net/ethernet/intel/igc/
H A Digc_base.h36 #define IGC_ADVTXD_MAC_TSTAMP 0x00080000 /* IEEE1588 Timestamp packet */
37 #define IGC_ADVTXD_TSTAMP_REG_1 0x00010000 /* Select register 1 for timestamp */
38 #define IGC_ADVTXD_TSTAMP_REG_2 0x00020000 /* Select register 2 for timestamp */
39 #define IGC_ADVTXD_TSTAMP_REG_3 0x00030000 /* Select register 3 for timestamp */
40 #define IGC_ADVTXD_TSTAMP_TIMER_1 0x00010000 /* Select timer 1 for timestamp */
41 #define IGC_ADVTXD_TSTAMP_TIMER_2 0x00020000 /* Select timer 2 for timestamp */
42 #define IGC_ADVTXD_TSTAMP_TIMER_3 0x00030000 /* Select timer 3 for timestamp */
44 #define IGC_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Descriptor */
45 #define IGC_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */
46 #define IGC_ADVTXD_DCMD_EOP 0x01000000 /* End of Packet */
[all …]
/linux/drivers/net/ethernet/
H A Djme.h19 #define PCI_DEVICE_ID_JMICRON_JMC250 0x0250
20 #define PCI_DEVICE_ID_JMICRON_JMC260 0x0260
38 if (0) \
40 } while (0)
46 #define PCI_DCSR_MRRS 0x59
47 #define PCI_DCSR_MRRS_MASK 0x70
50 MRRS_128B = 0x00,
51 MRRS_256B = 0x10,
52 MRRS_512B = 0x20,
53 MRRS_1024B = 0x30,
[all …]
/linux/arch/powerpc/boot/dts/
H A Duc101.dts75 phy0: ethernet-phy@0 {
77 reg = <0>;
91 reg = <0x2c>;
95 reg = <0x51>;
105 ranges = <0 0 0xff800000 0x00800000
106 1 0 0x80000000 0x00800000
107 3 0 0x80000000 0x00800000>;
109 flash@0,0 {
111 reg = <0 0 0x00800000>;
117 partition@0 {
[all …]
H A Ddigsy_mtc.dts19 memory@0 {
20 reg = <0x00000000 0x02000000>; // 32MB
57 phy0: ethernet-phy@0 {
58 reg = <0>;
65 reg = <0x50>;
70 reg = <0x56>;
75 reg = <0x68>;
85 interrupt-map-mask = <0xf800 0 0 7>;
86 interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3
87 0xc000 0 0 2 &mpc5200_pic 0 0 3
[all …]
H A Deiger.dts18 dcr-parent = <&{/cpus/cpu@0}>;
31 #size-cells = <0>;
33 cpu@0 {
36 reg = <0x00000000>;
37 clock-frequency = <0>; /* Filled in by U-Boot */
38 timebase-frequency = <0>; /* Filled in by U-Boot */
50 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
56 cell-index = <0>;
57 dcr-reg = <0x0c0 0x009>;
58 #address-cells = <0>;
[all …]
H A Dmucmc52.dts78 phy0: ethernet-phy@0 {
80 reg = <0>;
91 reg = <0x2c>;
95 reg = <0x51>;
101 interrupt-map-mask = <0xf800 0 0 7>;
103 /* IDSEL 0x10 */
104 0x8000 0 0 1 &mpc5200_pic 0 3 3
105 0x8000 0 0 2 &mpc5200_pic 0 3 3
106 0x8000 0 0 3 &mpc5200_pic 0 2 3
107 0x8000 0 0 4 &mpc5200_pic 0 1 3
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Domap4460.dtsi12 cpu0: cpu@0 {
32 reg = <0x4a002260 0x4
33 0x4a00232C 0x4
34 0x4a002378 0x18>;
36 interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>; /* talert */
39 #thermal-sensor-cells = <0>;
45 reg = <0x4a307bd0 0x8>, <0x4a306014 0x4>,
46 <0x4A002268 0x4>;
52 1025000 0 0 0 0 0
53 1200000 0 0 0 0 0
[all …]
/linux/drivers/video/fbdev/mb862xx/
H A Dmb862xx_reg.h9 #define MB862XX_MMIO_BASE 0x01fc0000
10 #define MB862XX_MMIO_HIGH_BASE 0x03fc0000
11 #define MB862XX_I2C_BASE 0x0000c000
12 #define MB862XX_DISP_BASE 0x00010000
13 #define MB862XX_CAP_BASE 0x00018000
14 #define MB862XX_DRAW_BASE 0x00030000
15 #define MB862XX_GEO_BASE 0x00038000
16 #define MB862XX_PIO_BASE 0x00038000
17 #define MB862XX_MMIO_SIZE 0x40000
20 #define GC_IST 0x00000020
[all …]
/linux/drivers/media/usb/cx231xx/
H A Dcx231xx-reg.h17 #define SAV_ACTIVE_VIDEO_FIELD1 0x80
18 #define EAV_ACTIVE_VIDEO_FIELD1 0x90
20 #define SAV_ACTIVE_VIDEO_FIELD2 0xc0
21 #define EAV_ACTIVE_VIDEO_FIELD2 0xd0
23 #define SAV_VBLANK_FIELD1 0xa0
24 #define EAV_VBLANK_FIELD1 0xb0
26 #define SAV_VBLANK_FIELD2 0xe0
27 #define EAV_VBLANK_FIELD2 0xf0
29 #define SAV_VBI_FIELD1 0x20
30 #define EAV_VBI_FIELD1 0x30
[all …]
/linux/arch/m68k/include/asm/
H A Dm54xxgpt.h20 #define MCF_GPT_GMS0 (MCF_MBAR + 0x000800)
21 #define MCF_GPT_GCIR0 (MCF_MBAR + 0x000804)
22 #define MCF_GPT_GPWM0 (MCF_MBAR + 0x000808)
23 #define MCF_GPT_GSR0 (MCF_MBAR + 0x00080C)
24 #define MCF_GPT_GMS1 (MCF_MBAR + 0x000810)
25 #define MCF_GPT_GCIR1 (MCF_MBAR + 0x000814)
26 #define MCF_GPT_GPWM1 (MCF_MBAR + 0x000818)
27 #define MCF_GPT_GSR1 (MCF_MBAR + 0x00081C)
28 #define MCF_GPT_GMS2 (MCF_MBAR + 0x000820)
29 #define MCF_GPT_GCIR2 (MCF_MBAR + 0x000824)
[all …]
/linux/drivers/video/fbdev/
H A Dcarminefb_regs.h5 #define CARMINE_OVERLAY_EXT_MODE (0x00000002)
6 #define CARMINE_GRAPH_REG (0x00000000)
7 #define CARMINE_DISP0_REG (0x00100000)
8 #define CARMINE_DISP1_REG (0x00140000)
9 #define CARMINE_WB_REG (0x00180000)
10 #define CARMINE_DCTL_REG (0x00300000)
11 #define CARMINE_CTL_REG (0x00400000)
12 #define CARMINE_WINDOW_MODE (0x00000001)
19 #define CARMINE_EXT_CMODE_DIRECT24_RGBA (0xC0000000)
20 #define CARMINE_DCTL_REG_MODE_ADD (0x00)
[all …]
/linux/drivers/net/ethernet/pasemi/
H A Dpasemi_mac.h110 PAS_MAC_CFG_PCFG = 0x80,
111 PAS_MAC_CFG_MACCFG = 0x84,
112 PAS_MAC_CFG_ADR0 = 0x8c,
113 PAS_MAC_CFG_ADR1 = 0x90,
114 PAS_MAC_CFG_TXP = 0x98,
115 PAS_MAC_CFG_RMON = 0x100,
116 PAS_MAC_IPC_CHNL = 0x208,
120 #define PAS_MAC_CFG_PCFG_PE 0x80000000
121 #define PAS_MAC_CFG_PCFG_CE 0x40000000
122 #define PAS_MAC_CFG_PCFG_BU 0x20000000
[all …]

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