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/linux/sound/soc/codecs/
H A Dwm8741.h18 #define WM8741_DACLLSB_ATTENUATION 0x00
19 #define WM8741_DACLMSB_ATTENUATION 0x01
20 #define WM8741_DACRLSB_ATTENUATION 0x02
21 #define WM8741_DACRMSB_ATTENUATION 0x03
22 #define WM8741_VOLUME_CONTROL 0x04
23 #define WM8741_FORMAT_CONTROL 0x05
24 #define WM8741_FILTER_CONTROL 0x06
25 #define WM8741_MODE_CONTROL_1 0x07
26 #define WM8741_MODE_CONTROL_2 0x08
27 #define WM8741_RESET 0x09
[all …]
H A Dwm8990.h16 #define WM8990_RESET 0x00
17 #define WM8990_POWER_MANAGEMENT_1 0x01
18 #define WM8990_POWER_MANAGEMENT_2 0x02
19 #define WM8990_POWER_MANAGEMENT_3 0x03
20 #define WM8990_AUDIO_INTERFACE_1 0x04
21 #define WM8990_AUDIO_INTERFACE_2 0x05
22 #define WM8990_CLOCKING_1 0x06
23 #define WM8990_CLOCKING_2 0x07
24 #define WM8990_AUDIO_INTERFACE_3 0x08
25 #define WM8990_AUDIO_INTERFACE_4 0x09
[all …]
H A Dwm8991.h16 #define WM8991_RESET 0x00
17 #define WM8991_POWER_MANAGEMENT_1 0x01
18 #define WM8991_POWER_MANAGEMENT_2 0x02
19 #define WM8991_POWER_MANAGEMENT_3 0x03
20 #define WM8991_AUDIO_INTERFACE_1 0x04
21 #define WM8991_AUDIO_INTERFACE_2 0x05
22 #define WM8991_CLOCKING_1 0x06
23 #define WM8991_CLOCKING_2 0x07
24 #define WM8991_AUDIO_INTERFACE_3 0x08
25 #define WM8991_AUDIO_INTERFACE_4 0x09
[all …]
H A Dwm8993.h15 #define WM8993_SOFTWARE_RESET 0x00
16 #define WM8993_POWER_MANAGEMENT_1 0x01
17 #define WM8993_POWER_MANAGEMENT_2 0x02
18 #define WM8993_POWER_MANAGEMENT_3 0x03
19 #define WM8993_AUDIO_INTERFACE_1 0x04
20 #define WM8993_AUDIO_INTERFACE_2 0x05
21 #define WM8993_CLOCKING_1 0x06
22 #define WM8993_CLOCKING_2 0x07
23 #define WM8993_AUDIO_INTERFACE_3 0x08
24 #define WM8993_AUDIO_INTERFACE_4 0x09
[all …]
H A Dwm8985.h13 #define WM8985_SOFTWARE_RESET 0x00
14 #define WM8985_POWER_MANAGEMENT_1 0x01
15 #define WM8985_POWER_MANAGEMENT_2 0x02
16 #define WM8985_POWER_MANAGEMENT_3 0x03
17 #define WM8985_AUDIO_INTERFACE 0x04
18 #define WM8985_COMPANDING_CONTROL 0x05
19 #define WM8985_CLOCK_GEN_CONTROL 0x06
20 #define WM8985_ADDITIONAL_CONTROL 0x07
21 #define WM8985_GPIO_CONTROL 0x08
22 #define WM8985_JACK_DETECT_CONTROL_1 0x09
[all …]
H A Dwm8983.h16 #define WM8983_SOFTWARE_RESET 0x00
17 #define WM8983_POWER_MANAGEMENT_1 0x01
18 #define WM8983_POWER_MANAGEMENT_2 0x02
19 #define WM8983_POWER_MANAGEMENT_3 0x03
20 #define WM8983_AUDIO_INTERFACE 0x04
21 #define WM8983_COMPANDING_CONTROL 0x05
22 #define WM8983_CLOCK_GEN_CONTROL 0x06
23 #define WM8983_ADDITIONAL_CONTROL 0x07
24 #define WM8983_GPIO_CONTROL 0x08
25 #define WM8983_JACK_DETECT_CONTROL_1 0x09
[all …]
H A Dtlv320aic23.h19 #define TLV320AIC23_LINVOL 0x00
20 #define TLV320AIC23_RINVOL 0x01
21 #define TLV320AIC23_LCHNVOL 0x02
22 #define TLV320AIC23_RCHNVOL 0x03
23 #define TLV320AIC23_ANLG 0x04
24 #define TLV320AIC23_DIGT 0x05
25 #define TLV320AIC23_PWR 0x06
26 #define TLV320AIC23_DIGT_FMT 0x07
27 #define TLV320AIC23_SRATE 0x08
28 #define TLV320AIC23_ACTIVE 0x09
[all …]
H A Dsgtl5000.h14 #define SGTL5000_CHIP_ID 0x0000
15 #define SGTL5000_CHIP_DIG_POWER 0x0002
16 #define SGTL5000_CHIP_CLK_CTRL 0x0004
17 #define SGTL5000_CHIP_I2S_CTRL 0x0006
18 #define SGTL5000_CHIP_SSS_CTRL 0x000a
19 #define SGTL5000_CHIP_ADCDAC_CTRL 0x000e
20 #define SGTL5000_CHIP_DAC_VOL 0x0010
21 #define SGTL5000_CHIP_PAD_STRENGTH 0x0014
22 #define SGTL5000_CHIP_ANA_ADC_CTRL 0x0020
23 #define SGTL5000_CHIP_ANA_HP_CTRL 0x0022
[all …]
/linux/include/sound/
H A Dwm8903.h15 #define WM8903_GPIO_CONFIG_ZERO 0x8000
18 * R6 (0x06) - Mic Bias Control 0
20 #define WM8903_MICDET_THR_MASK 0x0030 /* MICDET_THR - [5:4] */
23 #define WM8903_MICSHORT_THR_MASK 0x000C /* MICSHORT_THR - [3:2] */
26 #define WM8903_MICDET_ENA 0x0002 /* MICDET_ENA */
27 #define WM8903_MICDET_ENA_MASK 0x0002 /* MICDET_ENA */
30 #define WM8903_MICBIAS_ENA 0x0001 /* MICBIAS_ENA */
31 #define WM8903_MICBIAS_ENA_MASK 0x0001 /* MICBIAS_ENA */
32 #define WM8903_MICBIAS_ENA_SHIFT 0 /* MICBIAS_ENA */
40 #define WM8903_GPn_FN_GPIO_OUTPUT 0
[all …]
/linux/sound/pci/oxygen/
H A Dcm9780.h5 #define CM9780_JACK 0x62
6 #define CM9780_MIXER 0x64
7 #define CM9780_GPIO_SETUP 0x70
8 #define CM9780_GPIO_STATUS 0x72
11 #define CM9780_RSOE 0x0001
12 #define CM9780_CBOE 0x0002
13 #define CM9780_SSOE 0x0004
14 #define CM9780_FROE 0x0008
15 #define CM9780_HP2FMICOE 0x0010
16 #define CM9780_CB2MICOE 0x0020
[all …]
/linux/include/linux/mfd/wm8350/
H A Dgpio.h16 #define WM8350_GPIO_DEBOUNCE 0x80
17 #define WM8350_GPIO_PIN_PULL_UP_CONTROL 0x81
18 #define WM8350_GPIO_PULL_DOWN_CONTROL 0x82
19 #define WM8350_GPIO_INT_MODE 0x83
20 #define WM8350_GPIO_CONTROL 0x85
21 #define WM8350_GPIO_CONFIGURATION_I_O 0x86
22 #define WM8350_GPIO_PIN_POLARITY_TYPE 0x87
23 #define WM8350_GPIO_FUNCTION_SELECT_1 0x8C
24 #define WM8350_GPIO_FUNCTION_SELECT_2 0x8D
25 #define WM8350_GPIO_FUNCTION_SELECT_3 0x8E
[all …]
/linux/arch/arm/mach-omap2/
H A Dprcm_mpu7xx.h24 #define DRA7XX_PRCM_MPU_BASE 0x48243000
30 #define DRA7XX_MPU_PRCM_OCP_SOCKET_INST 0x0000
31 #define DRA7XX_MPU_PRCM_DEVICE_INST 0x0200
32 #define DRA7XX_MPU_PRCM_PRM_C0_INST 0x0400
33 #define DRA7XX_MPU_PRCM_CM_C0_INST 0x0600
34 #define DRA7XX_MPU_PRCM_PRM_C1_INST 0x0800
35 #define DRA7XX_MPU_PRCM_CM_C1_INST 0x0a00
38 #define DRA7XX_MPU_PRCM_CM_C0_CPU0_CDOFFS 0x0000
39 #define DRA7XX_MPU_PRCM_CM_C1_CPU1_CDOFFS 0x0000
45 #define DRA7XX_REVISION_PRCM_MPU_OFFSET 0x0000
[all …]
H A Dprcm_mpu54xx.h24 #define OMAP54XX_PRCM_MPU_BASE 0x48243000
30 #define OMAP54XX_PRCM_MPU_OCP_SOCKET_INST 0x0000
31 #define OMAP54XX_PRCM_MPU_DEVICE_INST 0x0200
32 #define OMAP54XX_PRCM_MPU_PRM_C0_INST 0x0400
33 #define OMAP54XX_PRCM_MPU_CM_C0_INST 0x0600
34 #define OMAP54XX_PRCM_MPU_PRM_C1_INST 0x0800
35 #define OMAP54XX_PRCM_MPU_CM_C1_INST 0x0a00
38 #define OMAP54XX_PRCM_MPU_CM_C0_CPU0_CDOFFS 0x0000
39 #define OMAP54XX_PRCM_MPU_CM_C1_CPU1_CDOFFS 0x0000
52 #define OMAP54XX_REVISION_PRCM_MPU_OFFSET 0x0000
[all …]
/linux/include/linux/mfd/wm831x/
H A Dirq.h14 #define WM831X_IRQ_TEMP_THW 0
75 * R16400 (0x4010) - System Interrupts
77 #define WM831X_PS_INT 0x8000 /* PS_INT */
78 #define WM831X_PS_INT_MASK 0x8000 /* PS_INT */
81 #define WM831X_TEMP_INT 0x4000 /* TEMP_INT */
82 #define WM831X_TEMP_INT_MASK 0x4000 /* TEMP_INT */
85 #define WM831X_GP_INT 0x2000 /* GP_INT */
86 #define WM831X_GP_INT_MASK 0x2000 /* GP_INT */
89 #define WM831X_ON_PIN_INT 0x1000 /* ON_PIN_INT */
90 #define WM831X_ON_PIN_INT_MASK 0x1000 /* ON_PIN_INT */
[all …]
/linux/include/linux/usb/
H A Dr8a66597.h13 #define R8A66597_PLATDATA_XTAL_12MHZ 0x01
14 #define R8A66597_PLATDATA_XTAL_24MHZ 0x02
15 #define R8A66597_PLATDATA_XTAL_48MHZ 0x03
44 #define SYSCFG0 0x00
45 #define SYSCFG1 0x02
46 #define SYSSTS0 0x04
47 #define SYSSTS1 0x06
48 #define DVSTCTR0 0x08
49 #define DVSTCTR1 0x0A
50 #define TESTMODE 0x0C
[all …]
/linux/drivers/pinctrl/mediatek/
H A Dpinctrl-mt8188.c13 * iocfg[0]:0x10005000, iocfg[1]:0x11c00000, iocfg[2]:0x11e10000,
14 * iocfg[3]:0x11e20000, iocfg[4]:0x11ea0000
20 32, 0)
27 PIN_FIELD(0, 177, 0x0300, 0x10, 0, 4),
31 PIN_FIELD(0, 177, 0x0000, 0x10, 0, 1),
35 PIN_FIELD(0, 177, 0x0200, 0x10, 0, 1),
39 PIN_FIELD(0, 177, 0x0100, 0x10, 0, 1),
43 PIN_FIELD_BASE(0, 0, 1, 0x0170, 0x10, 8, 1),
44 PIN_FIELD_BASE(1, 1, 1, 0x0170, 0x10, 9, 1),
45 PIN_FIELD_BASE(2, 2, 1, 0x0170, 0x10, 10, 1),
[all …]
H A Dpinctrl-mt6893.c14 32, 0)
21 PIN_FIELD(0, 219, 0x0300, 0x10, 0, 4),
25 PIN_FIELD(0, 219, 0x0000, 0x10, 0, 1),
29 PIN_FIELD(0, 219, 0x0200, 0x10, 0, 1),
33 PIN_FIELD(0, 219, 0x0100, 0x10, 0, 1),
37 PINS_FIELD_BASE(0, 9, 2, 0x00f0, 0x10, 7, 1),
38 PINS_FIELD_BASE(10, 15, 1, 0x0090, 0x10, 4, 1),
39 PIN_FIELD_BASE(16, 17, 5, 0x00c0, 0x10, 8, 1),
40 PINS_FIELD_BASE(18, 25, 7, 0x00f0, 0x10, 1, 1),
41 PINS_FIELD_BASE(26, 30, 6, 0x00e0, 0x10, 6, 1),
[all …]
/linux/include/linux/mfd/
H A Dwm8400-audio.h14 * R2 (0x02) - Power Management (1)
16 #define WM8400_CODEC_ENA 0x8000 /* CODEC_ENA */
17 #define WM8400_CODEC_ENA_MASK 0x8000 /* CODEC_ENA */
20 #define WM8400_SYSCLK_ENA 0x4000 /* SYSCLK_ENA */
21 #define WM8400_SYSCLK_ENA_MASK 0x4000 /* SYSCLK_ENA */
24 #define WM8400_SPK_MIX_ENA 0x2000 /* SPK_MIX_ENA */
25 #define WM8400_SPK_MIX_ENA_MASK 0x2000 /* SPK_MIX_ENA */
28 #define WM8400_SPK_ENA 0x1000 /* SPK_ENA */
29 #define WM8400_SPK_ENA_MASK 0x1000 /* SPK_ENA */
32 #define WM8400_OUT3_ENA 0x0800 /* OUT3_ENA */
[all …]
/linux/drivers/net/ethernet/qlogic/
H A Dqla3xxx.h14 #define OPCODE_OB_MAC_IOCB_FN0 0x01
15 #define OPCODE_OB_MAC_IOCB_FN2 0x21
17 #define OPCODE_IB_MAC_IOCB 0xF9
18 #define OPCODE_IB_3032_MAC_IOCB 0x09
19 #define OPCODE_IB_IP_IOCB 0xFA
20 #define OPCODE_IB_3032_IP_IOCB 0x0A
22 #define OPCODE_FUNC_ID_MASK 0x30
23 #define OUTBOUND_MAC_IOCB 0x01 /* plus function bits */
25 #define FN0_MA_BITS_MASK 0x00
26 #define FN1_MA_BITS_MASK 0x80
[all …]
/linux/drivers/phy/qualcomm/
H A Dphy-qcom-qmp-dp-phy.h10 #define QSERDES_DP_PHY_REVISION_ID0 0x000
11 #define QSERDES_DP_PHY_REVISION_ID1 0x004
12 #define QSERDES_DP_PHY_REVISION_ID2 0x008
13 #define QSERDES_DP_PHY_REVISION_ID3 0x00c
14 #define QSERDES_DP_PHY_CFG 0x010
15 #define QSERDES_DP_PHY_CFG_1 0x014
16 #define QSERDES_DP_PHY_PD_CTL 0x018
17 #define QSERDES_DP_PHY_MODE 0x01c
18 #define QSERDES_DP_PHY_AUX_CFG0 0x020
19 #define QSERDES_DP_PHY_AUX_CFG1 0x024
[all …]
/linux/include/linux/mfd/madera/
H A Dregisters.h14 #define MADERA_SOFTWARE_RESET 0x00
15 #define MADERA_HARDWARE_REVISION 0x01
16 #define MADERA_CTRL_IF_CFG_1 0x08
17 #define MADERA_CTRL_IF_CFG_2 0x09
18 #define MADERA_CTRL_IF_CFG_3 0x0A
19 #define MADERA_WRITE_SEQUENCER_CTRL_0 0x16
20 #define MADERA_WRITE_SEQUENCER_CTRL_1 0x17
21 #define MADERA_WRITE_SEQUENCER_CTRL_2 0x18
22 #define MADERA_TONE_GENERATOR_1 0x20
23 #define MADERA_TONE_GENERATOR_2 0x21
[all …]
/linux/drivers/usb/gadget/udc/
H A Dm66592-udc.h16 #define M66592_SYSCFG 0x00
17 #define M66592_XTAL 0xC000 /* b15-14: Crystal selection */
18 #define M66592_XTAL48 0x8000 /* 48MHz */
19 #define M66592_XTAL24 0x4000 /* 24MHz */
20 #define M66592_XTAL12 0x0000 /* 12MHz */
21 #define M66592_XCKE 0x2000 /* b13: External clock enable */
22 #define M66592_RCKE 0x1000 /* b12: Register clock enable */
23 #define M66592_PLLC 0x0800 /* b11: PLL control */
24 #define M66592_SCKE 0x0400 /* b10: USB clock enable */
25 #define M66592_ATCKM 0x0100 /* b8: Automatic clock supply */
[all …]
/linux/drivers/net/ipa/reg/
H A Dipa_reg-v3.1.c13 [COMP_CFG_ENABLE] = BIT(0),
21 REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c);
24 [CLKON_RX] = BIT(0),
44 REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044);
47 [ROUTE_DIS] = BIT(0),
57 REG_FIELDS(ROUTE, route, 0x00000048);
60 [MEM_SIZE] = GENMASK(15, 0),
64 REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054);
67 [GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0),
72 REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074);
[all …]
/linux/include/linux/mfd/wm8994/
H A Dregisters.h16 #define WM8994_SOFTWARE_RESET 0x00
17 #define WM8994_POWER_MANAGEMENT_1 0x01
18 #define WM8994_POWER_MANAGEMENT_2 0x02
19 #define WM8994_POWER_MANAGEMENT_3 0x03
20 #define WM8994_POWER_MANAGEMENT_4 0x04
21 #define WM8994_POWER_MANAGEMENT_5 0x05
22 #define WM8994_POWER_MANAGEMENT_6 0x06
23 #define WM8994_INPUT_MIXER_1 0x15
24 #define WM8994_LEFT_LINE_INPUT_1_2_VOLUME 0x18
25 #define WM8994_LEFT_LINE_INPUT_3_4_VOLUME 0x19
[all …]
/linux/drivers/net/ethernet/seeq/
H A Dether3.h13 /* use 0 for production, 1 for verification, >2 for debug. debug flags: */
19 #define NET_DEBUG 0
25 #define REG_COMMAND (priv(dev)->seeq + 0x0000)
26 #define CMD_ENINTDMA 0x0001
27 #define CMD_ENINTRX 0x0002
28 #define CMD_ENINTTX 0x0004
29 #define CMD_ENINTBUFWIN 0x0008
30 #define CMD_ACKINTDMA 0x0010
31 #define CMD_ACKINTRX 0x0020
32 #define CMD_ACKINTTX 0x0040
[all …]

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