Searched +full:0 +full:x0018 (Results 1 – 25 of 487) sorted by relevance
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13 power-domains = <&k2g_pds 0x0018>;14 clocks = <&k2g_clks 0x0018 0>;17 queue-range = <0 0x80>;18 linkram0 = <0x4020000 0x7ff>;26 managed-queues = <0 0x80>;27 reg = <0x4100000 0x800>,28 <0x4040000 0x100>,29 <0x4080000 0x800>,30 <0x40c0000 0x800>;38 qpend-0 {[all …]
1 0x0000 = 0x00002 0x0001 = 0x00013 0x0002 = 0x00024 0x0003 = 0x00035 0x0004 = 0x00046 0x0005 = 0x00057 0x0006 = 0x00068 0x0007 = 0x00079 0x0008 = 0x000810 0x0009 = 0x0009[all …]
15 #define IMX7ULP_PAD_PTC0__PTC0 0x0000 0x0000 0x1 0x016 #define IMX7ULP_PAD_PTC0__TRACE_D15 0x0000 0x0000 0xa 0x017 #define IMX7ULP_PAD_PTC0__LPUART4_CTS_B 0x0000 0x0244 0x4 0x118 #define IMX7ULP_PAD_PTC0__LPI2C4_SCL 0x0000 0x0278 0x5 0x119 #define IMX7ULP_PAD_PTC0__TPM4_CLKIN 0x0000 0x0298 0x6 0x120 #define IMX7ULP_PAD_PTC0__FB_AD0 0x0000 0x0000 0x9 0x021 #define IMX7ULP_PAD_PTC1__PTC1 0x0004 0x0000 0x1 0x022 #define IMX7ULP_PAD_PTC1__TRACE_D14 0x0004 0x0000 0xa 0x023 #define IMX7ULP_PAD_PTC1__LPUART4_RTS_B 0x0004 0x0000 0x4 0x024 #define IMX7ULP_PAD_PTC1__LPI2C4_SDA 0x0004 0x027c 0x5 0x1[all …]
14 #define MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x0000 0x0030 0x0000 0x0 0x015 #define MX7D_PAD_LPSR_GPIO1_IO00__PWM4_OUT 0x0000 0x0030 0x0000 0x1 0x016 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_ANY 0x0000 0x0030 0x0000 0x2 0x017 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x0000 0x0030 0x0000 0x3 0x018 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG__RST_B_DEB 0x0000 0x0030 0x0000 0x4 0x019 #define MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x0004 0x0034 0x0000 0x0 0x020 #define MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x0004 0x0034 0x0000 0x1 0x021 #define MX7D_PAD_LPSR_GPIO1_IO01__CCM_ENET_REF_CLK3 0x0004 0x0034 0x0000 0x2 0x022 #define MX7D_PAD_LPSR_GPIO1_IO01__SAI1_MCLK 0x0004 0x0034 0x0000 0x3 0x023 #define MX7D_PAD_LPSR_GPIO1_IO01__ANATOP_24M_OUT 0x0004 0x0034 0x0000 0x4 0x0[all …]
33 #define MII_RDCPHY_DEBUG 0x1134 #define DEBUG_JABBER_DIS 0x004035 #define DEBUG_LOOP_BACK_10MBPS 0x040037 #define MII_RDCPHY_CTRL 0x1438 #define CTRL_SQE_ENB 0x010039 #define CTRL_NEG_POLARITY 0x040040 #define CTRL_AUTO_POLARITY 0x080041 #define CTRL_MDIXSEL_RX 0x200042 #define CTRL_MDIXSEL_TX 0x400043 #define CTRL_AUTO_MDIX_DIS 0x8000[all …]
42 * Params: [in] P = Bit position of start of the bit field (lsb is 0).51 #define NTB_LINK_STATUS_ACTIVE 0x200052 #define NTB_LINK_SPEED_MASK 0x000f53 #define NTB_LINK_WIDTH_MASK 0x03f067 #define XEON_SPCICMD_OFFSET 0x050468 #define XEON_DEVCTRL_OFFSET 0x059869 #define XEON_DEVSTS_OFFSET 0x059a70 #define XEON_LINK_STATUS_OFFSET 0x01a271 #define XEON_SLINK_STATUS_OFFSET 0x05a273 #define XEON_PBAR2LMT_OFFSET 0x0000[all …]
91 #define SMU_POST_CONTEXT_PORT_CONTEXT_INDEX_SHIFT (0UL)92 #define SMU_POST_CONTEXT_PORT_CONTEXT_INDEX_MASK (0x00000FFFUL)94 #define SMU_POST_CONTEXT_PORT_LOGICAL_PORT_INDEX_MASK (0x0000F000UL)96 #define SMU_POST_CONTEXT_PORT_PROTOCOL_ENGINE_MASK (0x00030000UL)98 #define SMU_POST_CONTEXT_PORT_COMMAND_CONTEXT_MASK (0x00FC0000UL)99 #define SMU_POST_CONTEXT_PORT_RESERVED_MASK (0xFF000000UL)106 #define SMU_INTERRUPT_STATUS_COMPLETION_MASK (0x80000000UL)108 #define SMU_INTERRUPT_STATUS_QUEUE_SUSPEND_MASK (0x00000002UL)109 #define SMU_INTERRUPT_STATUS_QUEUE_ERROR_SHIFT (0UL)110 #define SMU_INTERRUPT_STATUS_QUEUE_ERROR_MASK (0x00000001UL)[all …]
13 #define MX8ULP_PAD_PTD0__PTD0 0x0000 0x0000 0x1 0x014 #define MX8ULP_PAD_PTD0__I2S6_RX_BCLK 0x0000 0x0B44 0x7 0x115 #define MX8ULP_PAD_PTD0__SDHC0_RESET_B 0x0000 0x0000 0x8 0x016 #define MX8ULP_PAD_PTD0__FLEXSPI2_B_DQS 0x0000 0x0974 0x9 0x117 #define MX8ULP_PAD_PTD0__CLKOUT2 0x0000 0x0000 0xa 0x018 #define MX8ULP_PAD_PTD0__EPDC0_SDCLK_B 0x0000 0x0000 0xb 0x019 #define MX8ULP_PAD_PTD0__LP_APD_DBG_MUX_0 0x0000 0x0000 0xc 0x020 #define MX8ULP_PAD_PTD0__CLKOUT1 0x0000 0x0000 0xd 0x021 #define MX8ULP_PAD_PTD0__DEBUG_MUX0_0 0x0000 0x0000 0xe 0x022 #define MX8ULP_PAD_PTD0__DEBUG_MUX1_0 0x0000 0x0000 0xf 0x0[all …]