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/linux/drivers/media/platform/qcom/venus/
H A Dhfi_venus_io.h9 #define VBIF_BASE 0x80000
11 #define VBIF_AXI_HALT_CTRL0 0x208
12 #define VBIF_AXI_HALT_CTRL1 0x20c
14 #define VBIF_AXI_HALT_CTRL0_HALT_REQ BIT(0)
15 #define VBIF_AXI_HALT_CTRL1_HALT_ACK BIT(0)
18 #define CPU_BASE 0xc0000
20 #define CPU_CS_BASE (CPU_BASE + 0x12000)
21 #define CPU_IC_BASE (CPU_BASE + 0x1f000)
22 #define CPU_BASE_V6 0xa0000
24 #define CPU_IC_BASE_V6 (CPU_BASE_V6 + 0x138)
[all …]
/linux/arch/powerpc/boot/
H A Ddcr.h8 asm volatile("mfdcr %0,%1" : "=r"(rval) : "i"(rn)); \
12 asm volatile("mtdcr %0,%1" : : "i"(rn), "r"(val))
16 asm volatile("mfdcrx %0,%1" : "=r"(rval) : "r"(rn)); \
21 asm volatile("mtdcrx %0,%1" : : "r"(rn), "r" (val)); \
25 #define DCRN_SDRAM0_CFGADDR 0x010
26 #define DCRN_SDRAM0_CFGDATA 0x011
35 #define SDRAM0_B0CR 0x40
36 #define SDRAM0_B1CR 0x44
37 #define SDRAM0_B2CR 0x48
38 #define SDRAM0_B3CR 0x4c
[all …]
/linux/arch/arm/boot/dts/marvell/
H A Darmada-xp-lenovo-ix4-300d.dts23 memory@0 {
25 reg = <0 0x00000000 0 0x20000000>; /* 512MB */
29 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
30 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
31 MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
32 MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
40 pinctrl-0 = <&ge0_rgmii_pins>;
48 pinctrl-0 = <&ge1_rgmii_pins>;
69 reg = <0x2e>;
74 reg = <0x50>;
[all …]
/linux/include/linux/mfd/
H A Dezx-pcap.h40 #define PCAP_REGISTER_WRITE_OP_BIT 0x80000000
41 #define PCAP_REGISTER_READ_OP_BIT 0x00000000
43 #define PCAP_REGISTER_VALUE_MASK 0x01ffffff
44 #define PCAP_REGISTER_ADDRESS_MASK 0x7c000000
47 #define PCAP_CLEAR_INTERRUPT_REGISTER 0x01ffffff
48 #define PCAP_MASK_ALL_INTERRUPT 0x01ffffff
51 #define PCAP_REG_ISR 0x0 /* Interrupt Status */
52 #define PCAP_REG_MSR 0x1 /* Interrupt Mask */
53 #define PCAP_REG_PSTAT 0x2 /* Processor Status */
54 #define PCAP_REG_VREG2 0x6 /* Regulator Bank 2 Control */
[all …]
/linux/drivers/mtd/maps/
H A Dnettel.c30 #define AMD_WINDOW_MAXSIZE 0x00200000
36 #define SC520_PAR_ADDR_MASK 0x00003fff
41 #define SC520_PAR_SIZE_MASK 0x01ffc000
51 #define SC520_PAR_BOOTCS 0x8a000000
52 #define SC520_PAR_ROMCS1 0xaa000000
53 #define SC520_PAR_ROMCS2 0xca000000 /* Cache disabled, 64K page */
69 .size = 0,
76 .offset = 0,
77 .size = 0x000e0000
81 .offset = 0x00100000,
[all …]
/linux/drivers/video/fbdev/geode/
H A Dvideo_cs5530.h18 #define CS5530_VIDEO_CONFIG 0x0000
19 # define CS5530_VCFG_VID_EN 0x00000001
20 # define CS5530_VCFG_VID_REG_UPDATE 0x00000002
21 # define CS5530_VCFG_VID_INP_FORMAT 0x0000000C
22 # define CS5530_VCFG_8_BIT_4_2_0 0x00000004
23 # define CS5530_VCFG_16_BIT_4_2_0 0x00000008
24 # define CS5530_VCFG_GV_SEL 0x00000010
25 # define CS5530_VCFG_CSC_BYPASS 0x00000020
26 # define CS5530_VCFG_X_FILTER_EN 0x00000040
27 # define CS5530_VCFG_Y_FILTER_EN 0x00000080
[all …]
H A Ddisplay_gx1.h21 #define CONFIG_CCR3 0xc3
22 # define CONFIG_CCR3_MAPEN 0x10
23 #define CONFIG_GCR 0xb8
27 #define MC_BANK_CFG 0x08
28 # define MC_BCFG_DIMM0_SZ_MASK 0x00000700
29 # define MC_BCFG_DIMM0_PG_SZ_MASK 0x00000070
30 # define MC_BCFG_DIMM0_PG_SZ_NO_DIMM 0x00000070
32 #define MC_GBASE_ADD 0x14
33 # define MC_GADD_GBADD_MASK 0x000003ff
37 #define DC_PAL_ADDRESS 0x70
[all …]
/linux/Documentation/arch/arm/sa1100/
H A Dassabet.rst91 load zImage -r -b 0x100000
95 load -m ymodem -r -b 0x100000
99 fis create "Linux kernel" -b 0x100000 -l 0xc0000
108 load ramdisk_image.gz -r -b 0x800000
119 exec -b 0x100000 -l 0xc0000
140 load sample_img.jffs2 -r -b 0x100000
144 RedBoot> load sample_img.jffs2 -r -b 0x100000
145 Raw file loaded 0x00100000-0x00377424
154 0x500E0000 .. 0x503C0000
162 size of unallocated flash: 0x503c0000 - 0x500e0000 = 0x2e0000
[all …]
/linux/Documentation/devicetree/bindings/timer/
H A Dnvidia,tegra186-timer.yaml45 One per each timer channels 0 through 9.
57 One per each timer channels 0 through 15.
73 reg = <0x03010000 0x000e0000>;
74 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
92 reg = <0x02080000 0x00121000>;
93 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
/linux/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
H A Dregsnv04.h5 #define NV04_PFIFO_DELAY_0 0x00002040
6 #define NV04_PFIFO_DMA_TIMESLICE 0x00002044
7 #define NV04_PFIFO_NEXT_CHANNEL 0x00002050
8 #define NV03_PFIFO_INTR_0 0x00002100
9 #define NV03_PFIFO_INTR_EN_0 0x00002140
10 # define NV_PFIFO_INTR_CACHE_ERROR (1<<0)
17 #define NV03_PFIFO_RAMHT 0x00002210
18 #define NV03_PFIFO_RAMFC 0x00002214
19 #define NV03_PFIFO_RAMRO 0x00002218
20 #define NV40_PFIFO_RAMFC 0x00002220
[all …]
/linux/arch/arm/boot/dts/qcom/
H A Dqcom-ipq4018-jalapeno.dts34 spi_0_pins: spi-0-state {
67 pinctrl-0 = <&spi_0_pins>;
71 flash@0 {
75 reg = <0>;
83 partition@0 {
85 reg = <0x00000000 0x00040000>;
91 reg = <0x00040000 0x00020000>;
97 reg = <0x00060000 0x00060000>;
103 reg = <0x000c0000 0x00010000>;
109 reg = <0x000d0000 0x00010000>;
[all …]
H A Dqcom-ipq4018-ap120c-ac.dtsi98 pinctrl-0 = <&i2c0_pins>;
103 reg = <0x29>;
110 pinctrl-0 = <&spi0_pins>;
114 flash@0 {
116 reg = <0>;
124 partition@0 {
126 reg = <0x00000000 0x00040000>;
132 reg = <0x00040000 0x00020000>;
138 reg = <0x00060000 0x00060000>;
144 reg = <0x000c0000 0x00010000>;
[all …]
/linux/drivers/scsi/bfa/
H A Dbfi_reg.h18 #define HOSTFN0_INT_STATUS 0x00014000 /* cb/ct */
19 #define HOSTFN1_INT_STATUS 0x00014100 /* cb/ct */
20 #define HOSTFN2_INT_STATUS 0x00014300 /* ct */
21 #define HOSTFN3_INT_STATUS 0x00014400 /* ct */
22 #define HOSTFN0_INT_MSK 0x00014004 /* cb/ct */
23 #define HOSTFN1_INT_MSK 0x00014104 /* cb/ct */
24 #define HOSTFN2_INT_MSK 0x00014304 /* ct */
25 #define HOSTFN3_INT_MSK 0x00014404 /* ct */
27 #define HOST_PAGE_NUM_FN0 0x00014008 /* cb/ct */
28 #define HOST_PAGE_NUM_FN1 0x00014108 /* cb/ct */
[all …]
/linux/drivers/net/ethernet/brocade/bna/
H A Dbfi_reg.h19 #define HOSTFN0_INT_STATUS 0x00014000 /* cb/ct */
20 #define HOSTFN1_INT_STATUS 0x00014100 /* cb/ct */
21 #define HOSTFN2_INT_STATUS 0x00014300 /* ct */
22 #define HOSTFN3_INT_STATUS 0x00014400 /* ct */
23 #define HOSTFN0_INT_MSK 0x00014004 /* cb/ct */
24 #define HOSTFN1_INT_MSK 0x00014104 /* cb/ct */
25 #define HOSTFN2_INT_MSK 0x00014304 /* ct */
26 #define HOSTFN3_INT_MSK 0x00014404 /* ct */
28 #define HOST_PAGE_NUM_FN0 0x00014008 /* cb/ct */
29 #define HOST_PAGE_NUM_FN1 0x00014108 /* cb/ct */
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Dam335x-nano.dts14 cpu@0 {
21 reg = <0x80000000 0x10000000>; /* 256 MB */
29 gpios = <&gpio1 5 0>;
37 pinctrl-0 = <&misc_pins>;
162 pinctrl-0 = <&uart0_pins>;
168 pinctrl-0 = <&uart1_pins>;
179 pinctrl-0 = <&uart2_pins>;
189 pinctrl-0 = <&uart3_pins>;
200 pinctrl-0 = <&uart4_pins>;
211 pinctrl-0 = <&uart5_pins>;
[all …]
/linux/sound/pci/cs46xx/
H A Dcs46xx.h25 #define BA0_HISR 0x00000000
26 #define BA0_HSR0 0x00000004
27 #define BA0_HICR 0x00000008
28 #define BA0_DMSR 0x00000100
29 #define BA0_HSAR 0x00000110
30 #define BA0_HDAR 0x00000114
31 #define BA0_HDMR 0x00000118
32 #define BA0_HDCR 0x0000011C
33 #define BA0_PFMC 0x00000200
34 #define BA0_PFCV1 0x00000204
[all …]
/linux/drivers/net/wireless/realtek/rtl8xxxu/
H A D8192c.c21 .reg_0e00 = 0x07090c0c,
22 .reg_0e04 = 0x01020405,
23 .reg_0e08 = 0x00000000,
24 .reg_086c = 0x00000000,
26 .reg_0e10 = 0x0b0c0c0e,
27 .reg_0e14 = 0x01030506,
28 .reg_0e18 = 0x0b0c0d0e,
29 .reg_0e1c = 0x01030509,
31 .reg_0830 = 0x07090c0c,
32 .reg_0834 = 0x01020405,
[all …]
/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac_dma.h15 #define DMA_BUS_MODE 0x00001000 /* Bus Mode */
16 #define DMA_XMT_POLL_DEMAND 0x00001004 /* Transmit Poll Demand */
17 #define DMA_RCV_POLL_DEMAND 0x00001008 /* Received Poll Demand */
18 #define DMA_RCV_BASE_ADDR 0x0000100c /* Receive List Base */
19 #define DMA_TX_BASE_ADDR 0x00001010 /* Transmit List Base */
20 #define DMA_STATUS 0x00001014 /* Status Register */
21 #define DMA_CONTROL 0x00001018 /* Ctrl (Operational Mode) */
22 #define DMA_INTR_ENA 0x0000101c /* Interrupt Enable */
23 #define DMA_MISSED_FRAME_CTR 0x00001020 /* Missed Frame Counter */
26 #define DMA_CHAN_BASE_OFFSET 0x100
[all …]
H A Ddwmac1000.h14 #define GMAC_CONTROL 0x00000000 /* Configuration */
15 #define GMAC_FRAME_FILTER 0x00000004 /* Frame Filter */
16 #define GMAC_HASH_HIGH 0x00000008 /* Multicast Hash Table High */
17 #define GMAC_HASH_LOW 0x0000000c /* Multicast Hash Table Low */
18 #define GMAC_MII_ADDR 0x00000010 /* MII Address */
19 #define GMAC_MII_DATA 0x00000014 /* MII Data */
20 #define GMAC_FLOW_CTRL 0x00000018 /* Flow Control */
21 #define GMAC_VLAN_TAG 0x0000001c /* VLAN Tag */
22 #define GMAC_DEBUG 0x00000024 /* GMAC debug register */
23 #define GMAC_WAKEUP_FILTER 0x00000028 /* Wake-up Frame Filter */
[all …]
/linux/arch/mips/include/asm/txx9/
H A Dtx4927.h36 #define TX4927_REG_BASE 0xffffffffff1f0000UL
38 #define TX4927_REG_BASE 0xff1f0000UL
40 #define TX4927_REG_SIZE 0x00010000
42 #define TX4927_SDRAMC_REG (TX4927_REG_BASE + 0x8000)
43 #define TX4927_EBUSC_REG (TX4927_REG_BASE + 0x9000)
44 #define TX4927_DMA_REG (TX4927_REG_BASE + 0xb000)
45 #define TX4927_PCIC_REG (TX4927_REG_BASE + 0xd000)
46 #define TX4927_CCFG_REG (TX4927_REG_BASE + 0xe000)
47 #define TX4927_IRC_REG (TX4927_REG_BASE + 0xf600)
49 #define TX4927_TMR_REG(ch) (TX4927_REG_BASE + 0xf000 + (ch) * 0x100)
[all …]
/linux/include/acpi/
H A Dacconfig.h91 #define ACPI_MAX_REFERENCE_COUNT 0x4000
150 #define ACPI_EBDA_PTR_LOCATION 0x0000040E /* Physical Address */
153 #define ACPI_HI_RSDP_WINDOW_BASE 0x000E0000 /* Physical Address */
154 #define ACPI_HI_RSDP_WINDOW_SIZE 0x00020000
159 #define ACPI_USER_REGION_BEGIN 0x80
/linux/drivers/soc/tegra/cbb/
H A Dtegra194-cbb.c27 #define ERRLOGGER_0_ID_COREID_0 0x00000000
28 #define ERRLOGGER_0_ID_REVISIONID_0 0x00000004
29 #define ERRLOGGER_0_FAULTEN_0 0x00000008
30 #define ERRLOGGER_0_ERRVLD_0 0x0000000c
31 #define ERRLOGGER_0_ERRCLR_0 0x00000010
32 #define ERRLOGGER_0_ERRLOG0_0 0x00000014
33 #define ERRLOGGER_0_ERRLOG1_0 0x00000018
34 #define ERRLOGGER_0_RSVD_00_0 0x0000001c
35 #define ERRLOGGER_0_ERRLOG3_0 0x00000020
36 #define ERRLOGGER_0_ERRLOG4_0 0x00000024
[all …]
/linux/drivers/net/wireless/ath/ath5k/
H A Drfbuffer.h108 AR5K_RF_TURBO = 0,
165 #define AR5K_RF5111_RF_TURBO { 1, 3, 0 }
168 #define AR5K_RF5111_OB_2GHZ { 3, 119, 0 }
169 #define AR5K_RF5111_DB_2GHZ { 3, 122, 0 }
171 #define AR5K_RF5111_OB_5GHZ { 3, 104, 0 }
172 #define AR5K_RF5111_DB_5GHZ { 3, 107, 0 }
174 #define AR5K_RF5111_PWD_XPD { 1, 95, 0 }
175 #define AR5K_RF5111_XPD_GAIN { 4, 96, 0 }
181 #define AR5K_RF5111_GAIN_I { 6, 29, 0 }
182 #define AR5K_RF5111_PLO_SEL { 1, 4, 0 }
[all …]
/linux/drivers/net/fddi/
H A Ddefza.h25 #define FZA_REG_BASE 0x100000 /* register base address */
26 #define FZA_REG_RESET 0x100200 /* reset, r/w */
27 #define FZA_REG_INT_EVENT 0x100400 /* interrupt event, r/w1c */
28 #define FZA_REG_STATUS 0x100402 /* status, r/o */
29 #define FZA_REG_INT_MASK 0x100404 /* interrupt mask, r/w */
30 #define FZA_REG_CONTROL_A 0x100500 /* control A, r/w1s */
31 #define FZA_REG_CONTROL_B 0x100502 /* control B, r/w */
33 /* Reset register constants. Bits 1:0 are r/w, others are fixed at 0. */
34 #define FZA_RESET_DLU 0x0002 /* OR with INIT to blast flash memory */
35 #define FZA_RESET_INIT 0x0001 /* switch into the reset state */
[all …]
/linux/include/net/
H A Dieee80211_radiotap.h29 * @it_version: radiotap version, always 0
58 /* version is always 0 */
59 #define PKTHDR_RADIOTAP_VERSION 0
63 IEEE80211_RADIOTAP_TSFT = 0,
102 IEEE80211_RADIOTAP_F_CFP = 0x01,
103 IEEE80211_RADIOTAP_F_SHORTPRE = 0x02,
104 IEEE80211_RADIOTAP_F_WEP = 0x04,
105 IEEE80211_RADIOTAP_F_FRAG = 0x08,
106 IEEE80211_RADIOTAP_F_FCS = 0x10,
107 IEEE80211_RADIOTAP_F_DATAPAD = 0x20,
[all …]

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