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/linux/drivers/clk/mediatek/
H A Dclk-mt8186-topckgen.c22 FACTOR_FLAGS(CLK_TOP_MAINPLL_D2, "mainpll_d2", "mainpll", 1, 2, 0),
23 FACTOR_FLAGS(CLK_TOP_MAINPLL_D2_D2, "mainpll_d2_d2", "mainpll_d2", 1, 2, 0),
24 FACTOR_FLAGS(CLK_TOP_MAINPLL_D2_D4, "mainpll_d2_d4", "mainpll_d2", 1, 4, 0),
25 FACTOR_FLAGS(CLK_TOP_MAINPLL_D2_D16, "mainpll_d2_d16", "mainpll_d2", 1, 16, 0),
26 FACTOR_FLAGS(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3, 0),
27 FACTOR_FLAGS(CLK_TOP_MAINPLL_D3_D2, "mainpll_d3_d2", "mainpll_d3", 1, 2, 0),
28 FACTOR_FLAGS(CLK_TOP_MAINPLL_D3_D4, "mainpll_d3_d4", "mainpll_d3", 1, 4, 0),
29 FACTOR_FLAGS(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5, 0),
30 FACTOR_FLAGS(CLK_TOP_MAINPLL_D5_D2, "mainpll_d5_d2", "mainpll_d5", 1, 2, 0),
31 FACTOR_FLAGS(CLK_TOP_MAINPLL_D5_D4, "mainpll_d5_d4", "mainpll_d5", 1, 4, 0),
[all …]
/linux/include/linux/mfd/wm8350/
H A Dcore.h27 #define WM8350_RESET_ID 0x00
28 #define WM8350_ID 0x01
29 #define WM8350_REVISION 0x02
30 #define WM8350_SYSTEM_CONTROL_1 0x03
31 #define WM8350_SYSTEM_CONTROL_2 0x04
32 #define WM8350_SYSTEM_HIBERNATE 0x05
33 #define WM8350_INTERFACE_CONTROL 0x06
34 #define WM8350_POWER_MGMT_1 0x08
35 #define WM8350_POWER_MGMT_2 0x09
36 #define WM8350_POWER_MGMT_3 0x0A
[all …]
H A Dgpio.h16 #define WM8350_GPIO_DEBOUNCE 0x80
17 #define WM8350_GPIO_PIN_PULL_UP_CONTROL 0x81
18 #define WM8350_GPIO_PULL_DOWN_CONTROL 0x82
19 #define WM8350_GPIO_INT_MODE 0x83
20 #define WM8350_GPIO_CONTROL 0x85
21 #define WM8350_GPIO_CONFIGURATION_I_O 0x86
22 #define WM8350_GPIO_PIN_POLARITY_TYPE 0x87
23 #define WM8350_GPIO_FUNCTION_SELECT_1 0x8C
24 #define WM8350_GPIO_FUNCTION_SELECT_2 0x8D
25 #define WM8350_GPIO_FUNCTION_SELECT_3 0x8E
[all …]
/linux/drivers/media/usb/gspca/
H A Dspca508.c23 #define CreativeVista 0
51 .priv = 0},
62 {0x0000, 0x870b},
64 {0x0020, 0x8112}, /* Video drop enable, ISO streaming disable */
65 {0x0003, 0x8111}, /* Reset compression & memory */
66 {0x0000, 0x8110}, /* Disable all outputs */
67 /* READ {0x0000, 0x8114} -> 0000: 00 */
68 {0x0000, 0x8114}, /* SW GPIO data */
69 {0x0008, 0x8110}, /* Enable charge pump output */
70 {0x0002, 0x8116}, /* 200 kHz pump clock */
[all …]
/linux/arch/arm/boot/dts/nvidia/
H A Dtegra124-peripherals-opp.dtsi10 opp-supported-hw = <0x0003>;
16 opp-supported-hw = <0x0008>;
22 opp-supported-hw = <0x0010>;
28 opp-supported-hw = <0x0004>;
34 opp-supported-hw = <0x0003>;
40 opp-supported-hw = <0x0008>;
46 opp-supported-hw = <0x0010>;
52 opp-supported-hw = <0x0004>;
58 opp-supported-hw = <0x0003>;
64 opp-supported-hw = <0x0008>;
[all …]
H A Dtegra30-cpu-opp.dtsi10 opp-supported-hw = <0x1F 0x31FE>;
16 opp-supported-hw = <0x1F 0x0C01>;
22 opp-supported-hw = <0x1F 0x0200>;
28 opp-supported-hw = <0x1F 0x31FE>;
34 opp-supported-hw = <0x1F 0x0C01>;
40 opp-supported-hw = <0x1F 0x0200>;
46 opp-supported-hw = <0x1F 0x31FE>;
53 opp-supported-hw = <0x1F 0x0C01>;
60 opp-supported-hw = <0x1F 0x0200>;
67 opp-supported-hw = <0x1F 0x0C00>;
[all …]
/linux/include/sound/
H A Dwm8903.h15 #define WM8903_GPIO_CONFIG_ZERO 0x8000
18 * R6 (0x06) - Mic Bias Control 0
20 #define WM8903_MICDET_THR_MASK 0x0030 /* MICDET_THR - [5:4] */
23 #define WM8903_MICSHORT_THR_MASK 0x000C /* MICSHORT_THR - [3:2] */
26 #define WM8903_MICDET_ENA 0x0002 /* MICDET_ENA */
27 #define WM8903_MICDET_ENA_MASK 0x0002 /* MICDET_ENA */
30 #define WM8903_MICBIAS_ENA 0x0001 /* MICBIAS_ENA */
31 #define WM8903_MICBIAS_ENA_MASK 0x0001 /* MICBIAS_ENA */
32 #define WM8903_MICBIAS_ENA_SHIFT 0 /* MICBIAS_ENA */
40 #define WM8903_GPn_FN_GPIO_OUTPUT 0
[all …]
/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra132-peripherals-opp.dtsi11 opp-supported-hw = <0x0003>;
17 opp-supported-hw = <0x0008>;
23 opp-supported-hw = <0x0010>;
29 opp-supported-hw = <0x0004>;
35 opp-supported-hw = <0x0003>;
41 opp-supported-hw = <0x0008>;
47 opp-supported-hw = <0x0010>;
53 opp-supported-hw = <0x0004>;
59 opp-supported-hw = <0x0003>;
65 opp-supported-hw = <0x0008>;
[all …]
/linux/include/linux/mfd/wm831x/
H A Dirq.h14 #define WM831X_IRQ_TEMP_THW 0
75 * R16400 (0x4010) - System Interrupts
77 #define WM831X_PS_INT 0x8000 /* PS_INT */
78 #define WM831X_PS_INT_MASK 0x8000 /* PS_INT */
81 #define WM831X_TEMP_INT 0x4000 /* TEMP_INT */
82 #define WM831X_TEMP_INT_MASK 0x4000 /* TEMP_INT */
85 #define WM831X_GP_INT 0x2000 /* GP_INT */
86 #define WM831X_GP_INT_MASK 0x2000 /* GP_INT */
89 #define WM831X_ON_PIN_INT 0x1000 /* ON_PIN_INT */
90 #define WM831X_ON_PIN_INT_MASK 0x1000 /* ON_PIN_INT */
[all …]
/linux/arch/arm/mach-omap2/
H A Dprm33xx.h14 #define AM33XX_PRM_BASE 0x44E00000
21 #define AM33XX_PRM_OCP_SOCKET_MOD 0x0B00
22 #define AM33XX_PRM_PER_MOD 0x0C00
23 #define AM33XX_PRM_WKUP_MOD 0x0D00
24 #define AM33XX_PRM_MPU_MOD 0x0E00
25 #define AM33XX_PRM_DEVICE_MOD 0x0F00
26 #define AM33XX_PRM_RTC_MOD 0x1000
27 #define AM33XX_PRM_GFX_MOD 0x1100
28 #define AM33XX_PRM_CEFUSE_MOD 0x1200
31 #define AM33XX_PM_PER_PWRSTST_OFFSET 0x0008
[all …]
H A Dprcm_mpu44xx.h27 #define OMAP4430_PRCM_MPU_BASE 0x48243000
33 #define OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST 0x0000
34 #define OMAP4430_PRCM_MPU_DEVICE_PRM_INST 0x0200
35 #define OMAP4430_PRCM_MPU_CPU0_INST 0x0400
36 #define OMAP4430_PRCM_MPU_CPU1_INST 0x0800
39 #define OMAP4430_PRCM_MPU_CPU0_CPU0_CDOFFS 0x0018
40 #define OMAP4430_PRCM_MPU_CPU1_CPU1_CDOFFS 0x0018
53 #define OMAP4_REVISION_PRCM_OFFSET 0x0000
54 … OMAP4430_REVISION_PRCM OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST, 0x0000)
57 #define OMAP4_PRCM_MPU_PRM_RSTST_OFFSET 0x0000
[all …]
/linux/drivers/scsi/
H A Dqlogicpti.h11 #define SBUS_CFG1 0x006UL
12 #define SBUS_CTRL 0x008UL
13 #define SBUS_STAT 0x00aUL
14 #define SBUS_SEMAPHORE 0x00cUL
15 #define CMD_DMA_CTRL 0x022UL
16 #define DATA_DMA_CTRL 0x042UL
17 #define MBOX0 0x080UL
18 #define MBOX1 0x082UL
19 #define MBOX2 0x084UL
20 #define MBOX3 0x086UL
[all …]
/linux/sound/soc/codecs/
H A Dtlv320aic23.h19 #define TLV320AIC23_LINVOL 0x00
20 #define TLV320AIC23_RINVOL 0x01
21 #define TLV320AIC23_LCHNVOL 0x02
22 #define TLV320AIC23_RCHNVOL 0x03
23 #define TLV320AIC23_ANLG 0x04
24 #define TLV320AIC23_DIGT 0x05
25 #define TLV320AIC23_PWR 0x06
26 #define TLV320AIC23_DIGT_FMT 0x07
27 #define TLV320AIC23_SRATE 0x08
28 #define TLV320AIC23_ACTIVE 0x09
[all …]
H A Dwm8903.h22 #define WM8903_SW_RESET_AND_ID 0x00
23 #define WM8903_REVISION_NUMBER 0x01
24 #define WM8903_BIAS_CONTROL_0 0x04
25 #define WM8903_VMID_CONTROL_0 0x05
26 #define WM8903_MIC_BIAS_CONTROL_0 0x06
27 #define WM8903_ANALOGUE_DAC_0 0x08
28 #define WM8903_ANALOGUE_ADC_0 0x0A
29 #define WM8903_POWER_MANAGEMENT_0 0x0C
30 #define WM8903_POWER_MANAGEMENT_1 0x0D
31 #define WM8903_POWER_MANAGEMENT_2 0x0E
[all …]
H A Dwm8985.h13 #define WM8985_SOFTWARE_RESET 0x00
14 #define WM8985_POWER_MANAGEMENT_1 0x01
15 #define WM8985_POWER_MANAGEMENT_2 0x02
16 #define WM8985_POWER_MANAGEMENT_3 0x03
17 #define WM8985_AUDIO_INTERFACE 0x04
18 #define WM8985_COMPANDING_CONTROL 0x05
19 #define WM8985_CLOCK_GEN_CONTROL 0x06
20 #define WM8985_ADDITIONAL_CONTROL 0x07
21 #define WM8985_GPIO_CONTROL 0x08
22 #define WM8985_JACK_DETECT_CONTROL_1 0x09
[all …]
H A Dwm8961.h14 #define WM8961_BCLK_DIV_1 0
32 #define WM8961_LEFT_INPUT_VOLUME 0x00
33 #define WM8961_RIGHT_INPUT_VOLUME 0x01
34 #define WM8961_LOUT1_VOLUME 0x02
35 #define WM8961_ROUT1_VOLUME 0x03
36 #define WM8961_CLOCKING1 0x04
37 #define WM8961_ADC_DAC_CONTROL_1 0x05
38 #define WM8961_ADC_DAC_CONTROL_2 0x06
39 #define WM8961_AUDIO_INTERFACE_0 0x07
40 #define WM8961_CLOCKING2 0x08
[all …]
H A Dwm8904.h13 #define WM8904_CLK_AUTO 0
25 #define WM8904_SW_RESET_AND_ID 0x00
26 #define WM8904_REVISION 0x01
27 #define WM8904_BIAS_CONTROL_0 0x04
28 #define WM8904_VMID_CONTROL_0 0x05
29 #define WM8904_MIC_BIAS_CONTROL_0 0x06
30 #define WM8904_MIC_BIAS_CONTROL_1 0x07
31 #define WM8904_ANALOGUE_DAC_0 0x08
32 #define WM8904_MIC_FILTER_CONTROL 0x09
33 #define WM8904_ANALOGUE_ADC_0 0x0A
[all …]
H A Dwm8737.h16 #define WM8737_LEFT_PGA_VOLUME 0x00
17 #define WM8737_RIGHT_PGA_VOLUME 0x01
18 #define WM8737_AUDIO_PATH_L 0x02
19 #define WM8737_AUDIO_PATH_R 0x03
20 #define WM8737_3D_ENHANCE 0x04
21 #define WM8737_ADC_CONTROL 0x05
22 #define WM8737_POWER_MANAGEMENT 0x06
23 #define WM8737_AUDIO_FORMAT 0x07
24 #define WM8737_CLOCKING 0x08
25 #define WM8737_MIC_PREAMP_CONTROL 0x09
[all …]
/linux/include/linux/mfd/madera/
H A Dregisters.h14 #define MADERA_SOFTWARE_RESET 0x00
15 #define MADERA_HARDWARE_REVISION 0x01
16 #define MADERA_CTRL_IF_CFG_1 0x08
17 #define MADERA_CTRL_IF_CFG_2 0x09
18 #define MADERA_CTRL_IF_CFG_3 0x0A
19 #define MADERA_WRITE_SEQUENCER_CTRL_0 0x16
20 #define MADERA_WRITE_SEQUENCER_CTRL_1 0x17
21 #define MADERA_WRITE_SEQUENCER_CTRL_2 0x18
22 #define MADERA_TONE_GENERATOR_1 0x20
23 #define MADERA_TONE_GENERATOR_2 0x21
[all …]
/linux/sound/pci/oxygen/
H A Dcm9780.h5 #define CM9780_JACK 0x62
6 #define CM9780_MIXER 0x64
7 #define CM9780_GPIO_SETUP 0x70
8 #define CM9780_GPIO_STATUS 0x72
11 #define CM9780_RSOE 0x0001
12 #define CM9780_CBOE 0x0002
13 #define CM9780_SSOE 0x0004
14 #define CM9780_FROE 0x0008
15 #define CM9780_HP2FMICOE 0x0010
16 #define CM9780_CB2MICOE 0x0020
[all …]
/linux/include/linux/
H A Dsungem_phy.h47 /* 1: autoneg enabled, 0: disabled */
72 #define BMCR_SPD2 0x0040 /* Gigabit enable (bcm54xx) */
73 #define LPA_PAUSE 0x0400
78 #define MII_BCM5201_INTERRUPT 0x1A
79 #define MII_BCM5201_INTERRUPT_INTENABLE 0x4000
81 #define MII_BCM5201_AUXMODE2 0x1B
82 #define MII_BCM5201_AUXMODE2_LOWPOWER 0x0008
84 #define MII_BCM5201_MULTIPHY 0x1E
87 #define MII_BCM5201_MULTIPHY_SERIALMODE 0x0002
88 #define MII_BCM5201_MULTIPHY_SUPERISOLATE 0x0008
[all …]
H A Dmicrochipphy.h9 #define LAN88XX_INT_MASK (0x19)
10 #define LAN88XX_INT_MASK_MDINTPIN_EN_ (0x8000)
11 #define LAN88XX_INT_MASK_SPEED_CHANGE_ (0x4000)
12 #define LAN88XX_INT_MASK_LINK_CHANGE_ (0x2000)
13 #define LAN88XX_INT_MASK_FDX_CHANGE_ (0x1000)
14 #define LAN88XX_INT_MASK_AUTONEG_ERR_ (0x0800)
15 #define LAN88XX_INT_MASK_AUTONEG_DONE_ (0x0400)
16 #define LAN88XX_INT_MASK_POE_DETECT_ (0x0200)
17 #define LAN88XX_INT_MASK_SYMBOL_ERR_ (0x0100)
18 #define LAN88XX_INT_MASK_FAST_LINK_FAIL_ (0x0080)
[all …]
/linux/drivers/phy/rockchip/
H A Dphy-rockchip-naneng-combphy.c3 * Rockchip PIPE USB3.0 PCIE SATA Combo Phy driver
24 #define PHYREG6 0x14
29 #define PHYREG7 0x18
33 #define PHYREG7_RX_RTERM_MASK GENMASK(3, 0)
34 #define PHYREG7_RX_RTERM_SHIFT 0
37 #define PHYREG8 0x1C
40 #define PHYREG10 0x24
41 #define PHYREG10_SSC_PCM_MASK GENMASK(3, 0)
44 #define PHYREG11 0x28
45 #define PHYREG11_SU_TRIM_0_7 0xF0
[all …]
/linux/drivers/net/ethernet/qlogic/
H A Dqla3xxx.h14 #define OPCODE_OB_MAC_IOCB_FN0 0x01
15 #define OPCODE_OB_MAC_IOCB_FN2 0x21
17 #define OPCODE_IB_MAC_IOCB 0xF9
18 #define OPCODE_IB_3032_MAC_IOCB 0x09
19 #define OPCODE_IB_IP_IOCB 0xFA
20 #define OPCODE_IB_3032_IP_IOCB 0x0A
22 #define OPCODE_FUNC_ID_MASK 0x30
23 #define OUTBOUND_MAC_IOCB 0x01 /* plus function bits */
25 #define FN0_MA_BITS_MASK 0x00
26 #define FN1_MA_BITS_MASK 0x80
[all …]
/linux/include/sound/ac97/
H A Dregs.h13 #define AC97_RESET 0x00 /* Reset */
14 #define AC97_MASTER 0x02 /* Master Volume */
15 #define AC97_HEADPHONE 0x04 /* Headphone Volume (optional) */
16 #define AC97_MASTER_MONO 0x06 /* Master Volume Mono (optional) */
17 #define AC97_MASTER_TONE 0x08 /* Master Tone (Bass & Treble) (optional) */
18 #define AC97_PC_BEEP 0x0a /* PC Beep Volume (optional) */
19 #define AC97_PHONE 0x0c /* Phone Volume (optional) */
20 #define AC97_MIC 0x0e /* MIC Volume */
21 #define AC97_LINE 0x10 /* Line In Volume */
22 #define AC97_CD 0x12 /* CD Volume */
[all …]

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