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/linux/arch/arm/boot/dts/nvidia/
H A Dtegra30-asus-tf201.dts67 reg = <0x4d>;
82 mount-matrix = "-1", "0", "0",
83 "0", "-1", "0",
84 "0", "0", "-1";
88 mount-matrix = "0", "-1", "0",
89 "-1", "0", "0",
90 "0", "0", "-1";
95 mount-matrix = "1", "0", "0",
96 "0", "-1", "0",
97 "0", "0", "1";
[all …]
/linux/Documentation/devicetree/bindings/opp/
H A Dopp-v2-kryo-cpu.yaml43 '^opp-?[0-9]+$':
58 0: MSM8996, speedbin 0
65 0-3: unused
66 4: MSM8996SG, speedbin 0
72 0: IPQ8062
84 '^opp-microvolt-speed[0-9]+-pvs[0-9]+$': true
97 '^opp-?[0-9]+$':
113 #size-cells = <0>;
115 CPU0: cpu@0 {
118 reg = <0x0 0x0>;
[all …]
/linux/drivers/ata/
H A Dpata_macio.c45 ({ if (0) dev_printk(KERN_DEBUG, dev, format, ##arg); 0; })
75 #define IDE_TIMING_CONFIG 0x200
76 #define IDE_INTERRUPT 0x300
79 #define IDE_KAUAI_PIO_CONFIG 0x200
80 #define IDE_KAUAI_ULTRA_CONFIG 0x210
81 #define IDE_KAUAI_POLL_CONFIG 0x220
98 #define TR_133_PIOREG_PIO_MASK 0xff000fff
99 #define TR_133_PIOREG_MDMA_MASK 0x00fff800
100 #define TR_133_UDMAREG_UDMA_MASK 0x0003ffff
101 #define TR_133_UDMAREG_UDMA_EN 0x00000001
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Domap5-l4.dtsi1 &l4_cfg { /* 0x4a000000 */
4 clocks = <&l4cfg_clkctrl OMAP5_L4_CFG_CLKCTRL 0>;
6 reg = <0x4a000000 0x800>,
7 <0x4a000800 0x800>,
8 <0x4a001000 0x1000>;
12 ranges = <0x00000000 0x4a000000 0x080000>, /* segment 0 */
13 <0x00080000 0x4a080000 0x080000>, /* segment 1 */
14 <0x00100000 0x4a100000 0x080000>, /* segment 2 */
15 <0x00180000 0x4a180000 0x080000>, /* segment 3 */
16 <0x00200000 0x4a200000 0x080000>, /* segment 4 */
[all …]
H A Domap4-l4.dtsi2 &l4_cfg { /* 0x4a000000 */
5 clocks = <&l4_cfg_clkctrl OMAP4_L4_CFG_CLKCTRL 0>;
7 reg = <0x4a000000 0x800>,
8 <0x4a000800 0x800>,
9 <0x4a001000 0x1000>;
13 ranges = <0x00000000 0x4a000000 0x080000>, /* segment 0 */
14 <0x00080000 0x4a080000 0x080000>, /* segment 1 */
15 <0x00100000 0x4a100000 0x080000>, /* segment 2 */
16 <0x00180000 0x4a180000 0x080000>, /* segment 3 */
17 <0x00200000 0x4a200000 0x080000>, /* segment 4 */
[all …]
/linux/drivers/net/ethernet/intel/i40e/
H A Di40e_register.h11 #define I40E_GL_ATQLEN_ATQCRIT_MASK I40E_MASK(0x1, I40E_GL_ATQLEN_ATQCRIT_SHIFT)
12 #define I40E_PF_ARQBAH 0x00080180 /* Reset: EMPR */
13 #define I40E_PF_ARQBAL 0x00080080 /* Reset: EMPR */
14 #define I40E_PF_ARQH 0x00080380 /* Reset: EMPR */
15 #define I40E_PF_ARQH_ARQH_SHIFT 0
16 #define I40E_PF_ARQH_ARQH_MASK I40E_MASK(0x3FF, I40E_PF_ARQH_ARQH_SHIFT)
17 #define I40E_PF_ARQLEN 0x00080280 /* Reset: EMPR */
19 #define I40E_PF_ARQLEN_ARQVFE_MASK I40E_MASK(0x1, I40E_PF_ARQLEN_ARQVFE_SHIFT)
21 #define I40E_PF_ARQLEN_ARQOVFL_MASK I40E_MASK(0x1, I40E_PF_ARQLEN_ARQOVFL_SHIFT)
23 #define I40E_PF_ARQLEN_ARQCRIT_MASK I40E_MASK(0x1, I40E_PF_ARQLEN_ARQCRIT_SHIFT)
[all …]
/linux/drivers/net/wireless/realtek/rtw89/
H A Drtw8852c_table.c10 {0xF0FF0000, 0x00000000},
11 {0xF03300FF, 0x00000001},
12 {0xF03400FF, 0x00000002},
13 {0xF03500FF, 0x00000003},
14 {0xF03600FF, 0x00000004},
15 {0x70C, 0x00000020},
16 {0x704, 0x601E0100},
17 {0x4000, 0x00000000},
18 {0x4004, 0xCA014000},
19 {0x4008, 0xC751D4F0},
[all …]