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/linux/drivers/gpu/drm/nouveau/nvkm/subdev/privring/
H A Dgk104.c31 u32 addr = nvkm_rd32(device, 0x122120 + (i * 0x0800)); in gk104_privring_intr_hub()
32 u32 data = nvkm_rd32(device, 0x122124 + (i * 0x0800)); in gk104_privring_intr_hub()
33 u32 stat = nvkm_rd32(device, 0x122128 + (i * 0x0800)); in gk104_privring_intr_hub()
41 u32 addr = nvkm_rd32(device, 0x124120 + (i * 0x0800)); in gk104_privring_intr_rop()
42 u32 data = nvkm_rd32(device, 0x124124 + (i * 0x0800)); in gk104_privring_intr_rop()
43 u32 stat = nvkm_rd32(device, 0x124128 + (i * 0x0800)); in gk104_privring_intr_rop()
51 u32 addr = nvkm_rd32(device, 0x128120 + (i * 0x0800)); in gk104_privring_intr_gpc()
52 u32 data = nvkm_rd32(device, 0x128124 + (i * 0x0800)); in gk104_privring_intr_gpc()
53 u32 stat = nvkm_rd32(device, 0x128128 + (i * 0x0800)); in gk104_privring_intr_gpc()
61 u32 intr0 = nvkm_rd32(device, 0x120058); in gk104_privring_intr()
[all …]
H A Dgf117.c30 nvkm_mask(device, 0x122310, 0x0003ffff, 0x00000800); in gf117_privring_init()
31 nvkm_mask(device, 0x122348, 0x0003ffff, 0x00000100); in gf117_privring_init()
32 nvkm_mask(device, 0x1223b0, 0x0003ffff, 0x00000fff); in gf117_privring_init()
33 return 0; in gf117_privring_init()
H A Dgf100.c31 u32 addr = nvkm_rd32(device, 0x122120 + (i * 0x0400)); in gf100_privring_intr_hub()
32 u32 data = nvkm_rd32(device, 0x122124 + (i * 0x0400)); in gf100_privring_intr_hub()
33 u32 stat = nvkm_rd32(device, 0x122128 + (i * 0x0400)); in gf100_privring_intr_hub()
41 u32 addr = nvkm_rd32(device, 0x124120 + (i * 0x0400)); in gf100_privring_intr_rop()
42 u32 data = nvkm_rd32(device, 0x124124 + (i * 0x0400)); in gf100_privring_intr_rop()
43 u32 stat = nvkm_rd32(device, 0x124128 + (i * 0x0400)); in gf100_privring_intr_rop()
51 u32 addr = nvkm_rd32(device, 0x128120 + (i * 0x0400)); in gf100_privring_intr_gpc()
52 u32 data = nvkm_rd32(device, 0x128124 + (i * 0x0400)); in gf100_privring_intr_gpc()
53 u32 stat = nvkm_rd32(device, 0x128128 + (i * 0x0400)); in gf100_privring_intr_gpc()
61 u32 intr0 = nvkm_rd32(device, 0x121c58); in gf100_privring_intr()
[all …]
/linux/drivers/net/wireless/realtek/rtw89/
H A Drtw8852c_rfk_table.c8 RTW89_DECL_RFK_WM(0xc004, BIT(17), 0x1),
9 RTW89_DECL_RFK_WM(0xc024, BIT(17), 0x1),
10 RTW89_DECL_RFK_WM(0xc104, BIT(17), 0x1),
11 RTW89_DECL_RFK_WM(0xc124, BIT(17), 0x1),
17 RTW89_DECL_RFK_WM(0xc000, BIT(17), 0x0),
18 RTW89_DECL_RFK_WM(0xc000, BIT(17), 0x1),
24 RTW89_DECL_RFK_WM(0xc100, BIT(17), 0x0),
25 RTW89_DECL_RFK_WM(0xc100, BIT(17), 0x1),
31 RTW89_DECL_RFK_WM(0x12b8, BIT(30), 0x1),
32 RTW89_DECL_RFK_WM(0x030c, BIT(28), 0x1),
[all …]
H A Drtw8852a_rfk_table.c8 RTW89_DECL_RFK_WM(0x12a8, 0x00000001, 0x00000001),
9 RTW89_DECL_RFK_WM(0x12a8, 0x0000000e, 0x00000002),
10 RTW89_DECL_RFK_WM(0x32a8, 0x00000001, 0x00000001),
11 RTW89_DECL_RFK_WM(0x32a8, 0x0000000e, 0x00000002),
12 RTW89_DECL_RFK_WM(0x12bc, 0x000000f0, 0x00000005),
13 RTW89_DECL_RFK_WM(0x12bc, 0x00000f00, 0x00000005),
14 RTW89_DECL_RFK_WM(0x12bc, 0x000f0000, 0x00000005),
15 RTW89_DECL_RFK_WM(0x12bc, 0x0000f000, 0x00000005),
16 RTW89_DECL_RFK_WM(0x120c, 0x000000ff, 0x00000033),
17 RTW89_DECL_RFK_WM(0x12c0, 0x0ff00000, 0x00000033),
[all …]
H A Drtw8851b_rfk_table.c8 RTW89_DECL_RFK_WM(0xc210, 0x003fc000, 0x80),
9 RTW89_DECL_RFK_WM(0xc224, 0x003fc000, 0x80),
10 RTW89_DECL_RFK_WM(0xc0f8, 0x30000000, 0x3),
11 RTW89_DECL_RFK_WM(0x12b8, BIT(30), 0x1),
12 RTW89_DECL_RFK_WM(0x030c, 0x1f000000, 0x1f),
13 RTW89_DECL_RFK_WM(0x032c, 0xc0000000, 0x0),
14 RTW89_DECL_RFK_WM(0x032c, BIT(22), 0x0),
15 RTW89_DECL_RFK_WM(0x032c, BIT(22), 0x1),
16 RTW89_DECL_RFK_WM(0x032c, BIT(16), 0x0),
17 RTW89_DECL_RFK_WM(0x032c, BIT(20), 0x1),
[all …]
H A Drtw8852bt_rfk_table.c8 RTW89_DECL_RFK_WM(0x12a8, 0x0000000f, 0x4),
9 RTW89_DECL_RFK_WM(0x32a8, 0x0000000f, 0x4),
10 RTW89_DECL_RFK_WM(0x12bc, 0x000ffff0, 0x5555),
11 RTW89_DECL_RFK_WM(0x32bc, 0x000ffff0, 0x5555),
12 RTW89_DECL_RFK_WM(0x0300, 0xff000000, 0x16),
13 RTW89_DECL_RFK_WM(0x0304, 0x000000ff, 0x19),
14 RTW89_DECL_RFK_WM(0x0314, 0xffff0000, 0x2041),
15 RTW89_DECL_RFK_WM(0x0318, 0xffffffff, 0x2041),
16 RTW89_DECL_RFK_WM(0x0318, 0xffffffff, 0x20012041),
17 RTW89_DECL_RFK_WM(0x0020, 0x00006000, 0x3),
[all …]
H A Drtw8852b_rfk_table.c8 RTW89_DECL_RFK_WM(0xC0D4, 0xffffffff, 0x4486888c),
9 RTW89_DECL_RFK_WM(0xC0D8, 0xffffffff, 0xc6ba10e0),
10 RTW89_DECL_RFK_WM(0xc0dc, 0xffffffff, 0x30c52868),
11 RTW89_DECL_RFK_WM(0xc0e0, 0xffffffff, 0x05008128),
12 RTW89_DECL_RFK_WM(0xc0e4, 0xffffffff, 0x0000272b),
13 RTW89_DECL_RFK_WM(0xC1D4, 0xffffffff, 0x4486888c),
14 RTW89_DECL_RFK_WM(0xC1D8, 0xffffffff, 0xc6ba10e0),
15 RTW89_DECL_RFK_WM(0xc1dc, 0xffffffff, 0x30c52868),
16 RTW89_DECL_RFK_WM(0xc1e0, 0xffffffff, 0x05008128),
17 RTW89_DECL_RFK_WM(0xc1e4, 0xffffffff, 0x0000272b),
[all …]
/linux/drivers/gpu/drm/radeon/
H A Dr600_reg.h31 #define R600_PCIE_PORT_INDEX 0x0038
32 #define R600_PCIE_PORT_DATA 0x003c
34 #define R600_RCU_INDEX 0x0100
35 #define R600_RCU_DATA 0x0104
37 #define R600_UVD_CTX_INDEX 0xf4a0
38 #define R600_UVD_CTX_DATA 0xf4a4
40 #define R600_MC_VM_FB_LOCATION 0x2180
41 #define R600_MC_FB_BASE_MASK 0x0000FFFF
42 #define R600_MC_FB_BASE_SHIFT 0
43 #define R600_MC_FB_TOP_MASK 0xFFFF0000
[all …]
/linux/drivers/media/pci/dm1105/
H A Ddm1105.c41 #define DM1105_BOARD_UNKNOWN 0
52 #define PCI_VENDOR_ID_TRIGEM 0x109f
55 #define PCI_VENDOR_ID_AXESS 0x195d
58 #define PCI_DEVICE_ID_DM1105 0x036f
61 #define PCI_DEVICE_ID_DW2002 0x2002
64 #define PCI_DEVICE_ID_DW2004 0x2004
67 #define PCI_DEVICE_ID_DM05 0x1105
73 #define DM1105_TSCTR 0x00
74 #define DM1105_DTALENTH 0x04
77 #define DM1105_GPIOVAL 0x08
[all …]
/linux/drivers/media/usb/cx231xx/
H A Dcx231xx-reg.h17 #define SAV_ACTIVE_VIDEO_FIELD1 0x80
18 #define EAV_ACTIVE_VIDEO_FIELD1 0x90
20 #define SAV_ACTIVE_VIDEO_FIELD2 0xc0
21 #define EAV_ACTIVE_VIDEO_FIELD2 0xd0
23 #define SAV_VBLANK_FIELD1 0xa0
24 #define EAV_VBLANK_FIELD1 0xb0
26 #define SAV_VBLANK_FIELD2 0xe0
27 #define EAV_VBLANK_FIELD2 0xf0
29 #define SAV_VBI_FIELD1 0x20
30 #define EAV_VBI_FIELD1 0x30
[all …]
/linux/drivers/net/ethernet/sfc/siena/
H A Dsiena.c53 FRF_CZ_TC_TIMER_VAL, 0); in siena_push_irq_moderation()
61 if (efx->fc_disable++ == 0) in efx_siena_prepare_flush()
67 if (--efx->fc_disable == 0) in siena_finish_flush()
73 EFX_OWORD32(0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF) },
75 EFX_OWORD32(0x000103FF, 0x00000000, 0x00000000, 0x00000000) },
77 EFX_OWORD32(0xFFFFFFFE, 0xFFFFFFFF, 0x0003FFFF, 0x00000000) },
79 EFX_OWORD32(0x7FFF0037, 0xFFFF8000, 0xFFFFFFFF, 0x03FFFFFF) },
81 EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
83 EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
85 EFX_OWORD32(0x00000003, 0x00000000, 0x00000000, 0x00000000) },
[all …]
/linux/Documentation/devicetree/bindings/watchdog/
H A Dsnps,dw-wdt.yaml70 default: [0x0001000 0x0002000 0x0004000 0x0008000
71 0x0010000 0x0020000 0x0040000 0x0080000
72 0x0100000 0x0200000 0x0400000 0x0800000
73 0x1000000 0x2000000 0x4000000 0x8000000]
88 reg = <0xffd02000 0x1000>;
89 interrupts = <0 171 4>;
97 reg = <0xffd02000 0x1000>;
98 interrupts = <0 171 4>;
101 snps,watchdog-tops = <0x000000FF 0x000001FF 0x000003FF
102 0x000007FF 0x0000FFFF 0x0001FFFF
[all …]
/linux/arch/mips/include/asm/mach-rc32434/
H A Ddma.h17 #define DMA0_BASE_ADDR 0x18040000
31 #define DMA_DESC_COUNT_BIT 0
32 #define DMA_DESC_COUNT_MSK 0x0003ffff
34 #define DMA_DESC_DS_MSK 0x00300000
37 #define DMA_DESC_DEV_CMD_MSK 0x01c00000
40 #define DMA_DESC_DEV_CMD_BYTE 0
71 #define DMA_CHAN_RUN_BIT (1 << 0)
74 #define DMA_CHAN_MODE_MSK 0x0000000c
75 #define DMA_CHAN_MODE_AUTO 0
82 #define DMA_STAT_FINI (1 << 0)
[all …]
/linux/arch/xtensa/kernel/
H A Djump_label.c13 #define J_OFFSET_MASK 0x0003ffff
17 #define J_INSN 0x6
18 #define NOP_INSN 0x0020f0
20 #define J_INSN 0x60000000
21 #define NOP_INSN 0x0f020000
51 return 0; in patch_text_stop_machine()
58 .cpu_count = ATOMIC_INIT(0), in patch_text()
81 BUG_ON(!((d & J_SIGN_MASK) == 0 || in arch_jump_label_transform()
/linux/drivers/net/ethernet/dec/tulip/
H A D21142.c21 static u16 t21142_csr13[] = { 0x0001, 0x0009, 0x0009, 0x0000, 0x0001, };
22 u16 t21142_csr14[] = { 0xFFFF, 0x0705, 0x0705, 0x0000, 0x7F3D, };
23 static u16 t21142_csr15[] = { 0x0008, 0x0006, 0x000E, 0x0008, 0x0008, };
36 int new_csr6 = 0; in t21142_media_task()
40 if ((csr14 & 0x80) && (csr12 & 0x7000) != 0x5000) in t21142_media_task()
46 if (tulip_check_duplex(dev) < 0) { in t21142_media_task()
70 } else if ((csr12 & 0x7000) != 0x5000) { in t21142_media_task()
77 new_csr6 = 0x82420000; in t21142_media_task()
78 dev->if_port = 0; in t21142_media_task()
79 iowrite32(0, ioaddr + CSR13); in t21142_media_task()
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/mmhub/
H A Dmmhub_9_4_1_default.h26 #define mmDAGB0_RDCLI0_DEFAULT 0xfe5fe0f9
27 #define mmDAGB0_RDCLI1_DEFAULT 0xfe5fe0f9
28 #define mmDAGB0_RDCLI2_DEFAULT 0xfe5fe0f9
29 #define mmDAGB0_RDCLI3_DEFAULT 0xfe5fe0f9
30 #define mmDAGB0_RDCLI4_DEFAULT 0xfe5fe0f9
31 #define mmDAGB0_RDCLI5_DEFAULT 0xfe5fe0f9
32 #define mmDAGB0_RDCLI6_DEFAULT 0xfe5fe0f9
33 #define mmDAGB0_RDCLI7_DEFAULT 0xfe5fe0f9
34 #define mmDAGB0_RDCLI8_DEFAULT 0xfe5fe0f9
35 #define mmDAGB0_RDCLI9_DEFAULT 0xfe5fe0f9
[all …]
H A Dmmhub_1_0_default.h26 #define mmDAGB0_RDCLI0_DEFAULT 0xfe5fe0f9
27 #define mmDAGB0_RDCLI1_DEFAULT 0xfe5fe0f9
28 #define mmDAGB0_RDCLI2_DEFAULT 0xfe5fe0f9
29 #define mmDAGB0_RDCLI3_DEFAULT 0xfe5fe0f9
30 #define mmDAGB0_RDCLI4_DEFAULT 0xfe5fe0f9
31 #define mmDAGB0_RDCLI5_DEFAULT 0xfe5fe0f9
32 #define mmDAGB0_RDCLI6_DEFAULT 0xfe5fe0f9
33 #define mmDAGB0_RDCLI7_DEFAULT 0xfe5fe0f9
34 #define mmDAGB0_RDCLI8_DEFAULT 0xfe5fe0f9
35 #define mmDAGB0_RDCLI9_DEFAULT 0xfe5fe0f9
[all …]
/linux/drivers/net/wireless/mediatek/mt76/mt7996/
H A Dcoredump.c16 .start = 0x00800000,
17 .len = 0x0004ffff,
21 .start = 0x00900000,
22 .len = 0x00037fff,
26 .start = 0x02200000,
27 .len = 0x0003ffff,
31 .start = 0x00400000,
32 .len = 0x00067fff,
36 .start = 0xe0000000,
37 .len = 0x0015ffff,
[all …]
/linux/arch/mips/rb532/
H A Dirq.c61 .mask = 0x0000efff,
62 .base_addr = (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 0 * IC_GROUP_OFFSET)},
64 .mask = 0x00001fff,
67 .mask = 0x00000007,
70 .mask = 0x0003ffff,
73 .mask = 0xffffffff,
93 int ipnum = 0x100 << ip; in enable_local_irq()
100 int ipnum = 0x100 << ip; in disable_local_irq()
107 int ipnum = 0x100 << ip; in ack_local_irq()
118 if (ip < 0) in rb532_enable_irq()
[all …]
/linux/include/linux/
H A Dtimer.h44 #define TIMER_CPUMASK 0x0003FFFF
45 #define TIMER_MIGRATING 0x00040000
47 #define TIMER_DEFERRABLE 0x00080000
48 #define TIMER_PINNED 0x00100000
49 #define TIMER_IRQSAFE 0x00200000
52 #define TIMER_ARRAYMASK 0xFFC00000
65 __TIMER_INITIALIZER(_function, 0)
95 } while (0)
102 } while (0)
143 * Returns: 1 if the timer is pending, 0 if not.
[all …]
/linux/sound/isa/gus/
H A Dgus_dma.c17 snd_gf1_write8(gus, SNDRV_GF1_GB_DRAM_DMA_CONTROL, 0x00); in snd_gf1_dma_ack()
34 "dma_transfer: addr=0x%x, buf=0x%lx, count=0x%x\n", in snd_gf1_dma_program()
41 if (addr & 0x1f) { in snd_gf1_dma_program()
43 "%s: unaligned address (0x%x)?\n", in snd_gf1_dma_program()
47 address = (addr & 0x000c0000) | ((addr & 0x0003ffff) >> 1); in snd_gf1_dma_program()
54 #if 0 in snd_gf1_dma_program()
55 dma_cmd |= 0x08; in snd_gf1_dma_program()
68 #if 0 in snd_gf1_dma_program()
70 "address = 0x%x, count = 0x%x, dma_cmd = 0x%x\n", in snd_gf1_dma_program()
75 address_high = ((address >> 16) & 0x000000f0) | (address & 0x0000000f); in snd_gf1_dma_program()
[all …]
/linux/drivers/gpu/drm/msm/disp/mdp5/
H A Dmdp5_cfg.c22 0,
35 .base = { 0x00500, 0x00600, 0x00700, 0x00800, 0x00900 },
36 .flush_hw_mask = 0x0003ffff,
40 .base = { 0x01100, 0x01500, 0x01900 },
45 0,
49 .base = { 0x01d00, 0x02100, 0x02500 },
53 0,
57 .base = { 0x02900, 0x02d00 },
60 0,
64 .base = { 0x03100, 0x03500, 0x03900, 0x03d00, 0x04100 },
[all …]
/linux/arch/mips/include/asm/mach-ath79/
H A Dar71xx_regs.h19 #define AR71XX_APB_BASE 0x18000000
20 #define AR71XX_GE0_BASE 0x19000000
21 #define AR71XX_GE0_SIZE 0x10000
22 #define AR71XX_GE1_BASE 0x1a000000
23 #define AR71XX_GE1_SIZE 0x10000
24 #define AR71XX_EHCI_BASE 0x1b000000
25 #define AR71XX_EHCI_SIZE 0x1000
26 #define AR71XX_OHCI_BASE 0x1c000000
27 #define AR71XX_OHCI_SIZE 0x1000
28 #define AR71XX_SPI_BASE 0x1f000000
[all …]
/linux/arch/mips/ath25/
H A Dar2315_regs.h20 #define AR2315_IRQ_MISC (MIPS_CPU_IRQ_BASE + 2) /* C0_CAUSE: 0x0400 */
21 #define AR2315_IRQ_WLAN0 (MIPS_CPU_IRQ_BASE + 3) /* C0_CAUSE: 0x0800 */
22 #define AR2315_IRQ_ENET0 (MIPS_CPU_IRQ_BASE + 4) /* C0_CAUSE: 0x1000 */
23 #define AR2315_IRQ_LCBUS_PCI (MIPS_CPU_IRQ_BASE + 5) /* C0_CAUSE: 0x2000 */
24 #define AR2315_IRQ_WLAN0_POLL (MIPS_CPU_IRQ_BASE + 6) /* C0_CAUSE: 0x4000 */
29 #define AR2315_MISC_IRQ_UART0 0
43 #define AR2315_SPI_READ_BASE 0x08000000 /* SPI flash */
44 #define AR2315_SPI_READ_SIZE 0x01000000
45 #define AR2315_WLAN0_BASE 0x10000000 /* Wireless MMR */
46 #define AR2315_PCI_BASE 0x10100000 /* PCI MMR */
[all …]

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