| /linux/include/linux/mfd/madera/ |
| H A D | registers.h | 14 #define MADERA_SOFTWARE_RESET 0x00
15 #define MADERA_HARDWARE_REVISION 0x01
16 #define MADERA_CTRL_IF_CFG_1 0x08
17 #define MADERA_CTRL_IF_CFG_2 0x09
18 #define MADERA_CTRL_IF_CFG_3 0x0A
19 #define MADERA_WRITE_SEQUENCER_CTRL_0 0x16
20 #define MADERA_WRITE_SEQUENCER_CTRL_1 0x17
21 #define MADERA_WRITE_SEQUENCER_CTRL_2 0x18
22 #define MADERA_TONE_GENERATOR_1 0x20
23 #define MADERA_TONE_GENERATOR_2 0x21
[all …]
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| /linux/include/linux/mfd/wm8350/ |
| H A D | core.h | 27 #define WM8350_RESET_ID 0x00
28 #define WM8350_ID 0x01
29 #define WM8350_REVISION 0x02
30 #define WM8350_SYSTEM_CONTROL_1 0x03
31 #define WM8350_SYSTEM_CONTROL_2 0x04
32 #define WM8350_SYSTEM_HIBERNATE 0x05
33 #define WM8350_INTERFACE_CONTROL 0x06
34 #define WM8350_POWER_MGMT_1 0x08
35 #define WM8350_POWER_MGMT_2 0x09
36 #define WM8350_POWER_MGMT_3 0x0A
[all …]
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| H A D | gpio.h | 16 #define WM8350_GPIO_DEBOUNCE 0x80
17 #define WM8350_GPIO_PIN_PULL_UP_CONTROL 0x81
18 #define WM8350_GPIO_PULL_DOWN_CONTROL 0x82
19 #define WM8350_GPIO_INT_MODE 0x83
20 #define WM8350_GPIO_CONTROL 0x85
21 #define WM8350_GPIO_CONFIGURATION_I_O 0x86
22 #define WM8350_GPIO_PIN_POLARITY_TYPE 0x87
23 #define WM8350_GPIO_FUNCTION_SELECT_1 0x8C
24 #define WM8350_GPIO_FUNCTION_SELECT_2 0x8D
25 #define WM8350_GPIO_FUNCTION_SELECT_3 0x8E
[all …]
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| /linux/drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/ |
| H A D | phytbl_lcn.c | 10 0x00000000,
11 0x00000000,
12 0x00000000,
13 0x00000000,
14 0x00000000,
15 0x00000000,
16 0x00000000,
17 0x00000000,
18 0x00000004,
19 0x00000000,
[all …]
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| /linux/drivers/media/i2c/s5c73m3/ |
| H A D | s5c73m3.h | 44 #define AHB_MSB_ADDR_PTR 0xfcfc
45 #define REG_CMDWR_ADDRH 0x0050
46 #define REG_CMDWR_ADDRL 0x0054
47 #define REG_CMDRD_ADDRH 0x0058
48 #define REG_CMDRD_ADDRL 0x005c
49 #define REG_CMDBUF_ADDR 0x0f14
51 #define REG_I2C_SEQ_STATUS S5C73M3_REG(0x0009, 0x59A6)
52 #define SEQ_END_PLL (1<<0x0)
53 #define SEQ_END_SENSOR (1<<0x1)
54 #define SEQ_END_GPIO (1<<0x2)
[all …]
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| /linux/sound/soc/codecs/ |
| H A D | wm8903.h | 22 #define WM8903_SW_RESET_AND_ID 0x00
23 #define WM8903_REVISION_NUMBER 0x01
24 #define WM8903_BIAS_CONTROL_0 0x04
25 #define WM8903_VMID_CONTROL_0 0x05
26 #define WM8903_MIC_BIAS_CONTROL_0 0x06
27 #define WM8903_ANALOGUE_DAC_0 0x08
28 #define WM8903_ANALOGUE_ADC_0 0x0A
29 #define WM8903_POWER_MANAGEMENT_0 0x0C
30 #define WM8903_POWER_MANAGEMENT_1 0x0D
31 #define WM8903_POWER_MANAGEMENT_2 0x0E
[all …]
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| H A D | tlv320aic23.h | 19 #define TLV320AIC23_LINVOL 0x00
20 #define TLV320AIC23_RINVOL 0x01
21 #define TLV320AIC23_LCHNVOL 0x02
22 #define TLV320AIC23_RCHNVOL 0x03
23 #define TLV320AIC23_ANLG 0x04
24 #define TLV320AIC23_DIGT 0x05
25 #define TLV320AIC23_PWR 0x06
26 #define TLV320AIC23_DIGT_FMT 0x07
27 #define TLV320AIC23_SRATE 0x08
28 #define TLV320AIC23_ACTIVE 0x09
[all …]
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| H A D | wm8904.h | 13 #define WM8904_CLK_AUTO 0
25 #define WM8904_SW_RESET_AND_ID 0x00
26 #define WM8904_REVISION 0x01
27 #define WM8904_BIAS_CONTROL_0 0x04
28 #define WM8904_VMID_CONTROL_0 0x05
29 #define WM8904_MIC_BIAS_CONTROL_0 0x06
30 #define WM8904_MIC_BIAS_CONTROL_1 0x07
31 #define WM8904_ANALOGUE_DAC_0 0x08
32 #define WM8904_MIC_FILTER_CONTROL 0x09
33 #define WM8904_ANALOGUE_ADC_0 0x0A
[all …]
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| H A D | wm8996.h | 29 #define WM8996_SOFTWARE_RESET 0x00
30 #define WM8996_POWER_MANAGEMENT_1 0x01
31 #define WM8996_POWER_MANAGEMENT_2 0x02
32 #define WM8996_POWER_MANAGEMENT_3 0x03
33 #define WM8996_POWER_MANAGEMENT_4 0x04
34 #define WM8996_POWER_MANAGEMENT_5 0x05
35 #define WM8996_POWER_MANAGEMENT_6 0x06
36 #define WM8996_POWER_MANAGEMENT_7 0x07
37 #define WM8996_POWER_MANAGEMENT_8 0x08
38 #define WM8996_LEFT_LINE_INPUT_VOLUME 0x10
[all …]
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| H A D | wm5100.h | 26 #define WM5100_CLKSRC_MCLK1 0
34 #define WM5100_CLKSRC_ASYNCCLK 0x100
39 #define WM5100_FLL_SRC_MCLK1 0x0
40 #define WM5100_FLL_SRC_MCLK2 0x1
41 #define WM5100_FLL_SRC_FLL1 0x4
42 #define WM5100_FLL_SRC_FLL2 0x5
43 #define WM5100_FLL_SRC_AIF1BCLK 0x8
44 #define WM5100_FLL_SRC_AIF2BCLK 0x9
45 #define WM5100_FLL_SRC_AIF3BCLK 0xa
50 #define WM5100_SOFTWARE_RESET 0x00
[all …]
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| /linux/include/sound/ |
| H A D | wm8903.h | 15 #define WM8903_GPIO_CONFIG_ZERO 0x8000
18 * R6 (0x06) - Mic Bias Control 0
20 #define WM8903_MICDET_THR_MASK 0x0030 /* MICDET_THR - [5:4] */
23 #define WM8903_MICSHORT_THR_MASK 0x000C /* MICSHORT_THR - [3:2] */
26 #define WM8903_MICDET_ENA 0x0002 /* MICDET_ENA */
27 #define WM8903_MICDET_ENA_MASK 0x0002 /* MICDET_ENA */
30 #define WM8903_MICBIAS_ENA 0x0001 /* MICBIAS_ENA */
31 #define WM8903_MICBIAS_ENA_MASK 0x0001 /* MICBIAS_ENA */
32 #define WM8903_MICBIAS_ENA_SHIFT 0 /* MICBIAS_ENA */
40 #define WM8903_GPn_FN_GPIO_OUTPUT 0
[all …]
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| /linux/arch/arm/boot/dts/nvidia/ |
| H A D | tegra30-cpu-opp.dtsi | 10 opp-supported-hw = <0x1F 0x31FE>;
16 opp-supported-hw = <0x1F 0x0C01>;
22 opp-supported-hw = <0x1F 0x0200>;
28 opp-supported-hw = <0x1F 0x31FE>;
34 opp-supported-hw = <0x1F 0x0C01>;
40 opp-supported-hw = <0x1F 0x0200>;
46 opp-supported-hw = <0x1F 0x31FE>;
53 opp-supported-hw = <0x1F 0x0C01>;
60 opp-supported-hw = <0x1F 0x0200>;
67 opp-supported-hw = <0x1F 0x0C00>;
[all …]
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| /linux/include/linux/mfd/wm831x/ |
| H A D | irq.h | 14 #define WM831X_IRQ_TEMP_THW 0
75 * R16400 (0x4010) - System Interrupts
77 #define WM831X_PS_INT 0x8000 /* PS_INT */
78 #define WM831X_PS_INT_MASK 0x8000 /* PS_INT */
81 #define WM831X_TEMP_INT 0x4000 /* TEMP_INT */
82 #define WM831X_TEMP_INT_MASK 0x4000 /* TEMP_INT */
85 #define WM831X_GP_INT 0x2000 /* GP_INT */
86 #define WM831X_GP_INT_MASK 0x2000 /* GP_INT */
89 #define WM831X_ON_PIN_INT 0x1000 /* ON_PIN_INT */
90 #define WM831X_ON_PIN_INT_MASK 0x1000 /* ON_PIN_INT */
[all …]
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| /linux/arch/powerpc/include/asm/ |
| H A D | ps3av.h | 13 #define PS3AV_VERSION 0x205 /* version of ps3av command */
15 #define PS3AV_CID_AV_INIT 0x00000001
16 #define PS3AV_CID_AV_FIN 0x00000002
17 #define PS3AV_CID_AV_GET_HW_CONF 0x00000003
18 #define PS3AV_CID_AV_GET_MONITOR_INFO 0x00000004
19 #define PS3AV_CID_AV_ENABLE_EVENT 0x00000006
20 #define PS3AV_CID_AV_DISABLE_EVENT 0x00000007
21 #define PS3AV_CID_AV_TV_MUTE 0x0000000a
23 #define PS3AV_CID_AV_VIDEO_CS 0x00010001
24 #define PS3AV_CID_AV_VIDEO_MUTE 0x00010002
[all …]
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| /linux/include/linux/mfd/arizona/ |
| H A D | registers.h | 16 #define ARIZONA_SOFTWARE_RESET 0x00
17 #define ARIZONA_DEVICE_REVISION 0x01
18 #define ARIZONA_CTRL_IF_SPI_CFG_1 0x08
19 #define ARIZONA_CTRL_IF_I2C1_CFG_1 0x09
20 #define ARIZONA_CTRL_IF_I2C2_CFG_1 0x0A
21 #define ARIZONA_CTRL_IF_I2C1_CFG_2 0x0B
22 #define ARIZONA_CTRL_IF_I2C2_CFG_2 0x0C
23 #define ARIZONA_CTRL_IF_STATUS_1 0x0D
24 #define ARIZONA_WRITE_SEQUENCER_CTRL_0 0x16
25 #define ARIZONA_WRITE_SEQUENCER_CTRL_1 0x17
[all …]
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| /linux/sound/pci/oxygen/ |
| H A D | cm9780.h | 5 #define CM9780_JACK 0x62
6 #define CM9780_MIXER 0x64
7 #define CM9780_GPIO_SETUP 0x70
8 #define CM9780_GPIO_STATUS 0x72
11 #define CM9780_RSOE 0x0001
12 #define CM9780_CBOE 0x0002
13 #define CM9780_SSOE 0x0004
14 #define CM9780_FROE 0x0008
15 #define CM9780_HP2FMICOE 0x0010
16 #define CM9780_CB2MICOE 0x0020
[all …]
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| /linux/drivers/net/wireless/broadcom/b43/ |
| H A D | phy_ht.h | 8 #define B43_PHY_HT_BBCFG 0x001 /* BB config */
9 #define B43_PHY_HT_BBCFG_RSTCCA 0x4000 /* Reset CCA */
10 #define B43_PHY_HT_BBCFG_RSTRX 0x8000 /* Reset RX */
11 #define B43_PHY_HT_BANDCTL 0x009 /* Band control */
12 #define B43_PHY_HT_BANDCTL_5GHZ 0x0001 /* Use the 5GHz band */
13 #define B43_PHY_HT_TABLE_ADDR 0x072 /* Table address */
14 #define B43_PHY_HT_TABLE_DATALO 0x073 /* Table data low */
15 #define B43_PHY_HT_TABLE_DATAHI 0x074 /* Table data high */
16 #define B43_PHY_HT_CLASS_CTL 0x0B0 /* Classifier control */
17 #define B43_PHY_HT_CLASS_CTL_CCK_EN 0x0001 /* CCK enable */
[all …]
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| /linux/drivers/scsi/ |
| H A D | qlogicpti.h | 11 #define SBUS_CFG1 0x006UL
12 #define SBUS_CTRL 0x008UL
13 #define SBUS_STAT 0x00aUL
14 #define SBUS_SEMAPHORE 0x00cUL
15 #define CMD_DMA_CTRL 0x022UL
16 #define DATA_DMA_CTRL 0x042UL
17 #define MBOX0 0x080UL
18 #define MBOX1 0x082UL
19 #define MBOX2 0x084UL
20 #define MBOX3 0x086UL
[all …]
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| /linux/drivers/net/ethernet/qlogic/ |
| H A D | qla3xxx.h | 14 #define OPCODE_OB_MAC_IOCB_FN0 0x01
15 #define OPCODE_OB_MAC_IOCB_FN2 0x21
17 #define OPCODE_IB_MAC_IOCB 0xF9
18 #define OPCODE_IB_3032_MAC_IOCB 0x09
19 #define OPCODE_IB_IP_IOCB 0xFA
20 #define OPCODE_IB_3032_IP_IOCB 0x0A
22 #define OPCODE_FUNC_ID_MASK 0x30
23 #define OUTBOUND_MAC_IOCB 0x01 /* plus function bits */
25 #define FN0_MA_BITS_MASK 0x00
26 #define FN1_MA_BITS_MASK 0x80
[all …]
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| /linux/drivers/usb/serial/ |
| H A D | kobil_sct.h | 3 #define SUSBCR_SBR_MASK 0xFF00
4 #define SUSBCR_SBR_1200 0x0100
5 #define SUSBCR_SBR_9600 0x0200
6 #define SUSBCR_SBR_19200 0x0400
7 #define SUSBCR_SBR_28800 0x0800
8 #define SUSBCR_SBR_38400 0x1000
9 #define SUSBCR_SBR_57600 0x2000
10 #define SUSBCR_SBR_115200 0x4000
12 #define SUSBCR_SPASB_MASK 0x0070
13 #define SUSBCR_SPASB_NoParity 0x0010
[all …]
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| /linux/include/linux/usb/ |
| H A D | r8a66597.h | 13 #define R8A66597_PLATDATA_XTAL_12MHZ 0x01
14 #define R8A66597_PLATDATA_XTAL_24MHZ 0x02
15 #define R8A66597_PLATDATA_XTAL_48MHZ 0x03
44 #define SYSCFG0 0x00
45 #define SYSCFG1 0x02
46 #define SYSSTS0 0x04
47 #define SYSSTS1 0x06
48 #define DVSTCTR0 0x08
49 #define DVSTCTR1 0x0A
50 #define TESTMODE 0x0C
[all …]
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| /linux/include/uapi/linux/ |
| H A D | nfs4.h | 30 #define NFS4_ACCESS_READ 0x0001
31 #define NFS4_ACCESS_LOOKUP 0x0002
32 #define NFS4_ACCESS_MODIFY 0x0004
33 #define NFS4_ACCESS_EXTEND 0x0008
34 #define NFS4_ACCESS_DELETE 0x0010
35 #define NFS4_ACCESS_EXECUTE 0x0020
36 #define NFS4_ACCESS_XAREAD 0x0040
37 #define NFS4_ACCESS_XAWRITE 0x0080
38 #define NFS4_ACCESS_XALIST 0x010
[all...] |
| /linux/drivers/usb/gadget/udc/ |
| H A D | m66592-udc.h | 16 #define M66592_SYSCFG 0x00
17 #define M66592_XTAL 0xC000 /* b15-14: Crystal selection */
18 #define M66592_XTAL48 0x8000 /* 48MHz */
19 #define M66592_XTAL24 0x4000 /* 24MHz */
20 #define M66592_XTAL12 0x0000 /* 12MHz */
21 #define M66592_XCKE 0x2000 /* b13: External clock enable */
22 #define M66592_RCKE 0x1000 /* b12: Register clock enable */
23 #define M66592_PLLC 0x0800 /* b11: PLL control */
24 #define M66592_SCKE 0x0400 /* b10: USB clock enable */
25 #define M66592_ATCKM 0x0100 /* b8: Automatic clock supply */
[all …]
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| /linux/drivers/net/phy/mscc/ |
| H A D | mscc_ptp.h | 13 #define BIU_ADDR_EXE 0x8000
14 #define BIU_ADDR_READ 0x4000
15 #define BIU_ADDR_WRITE 0x0000
23 #define MSCC_PHY_1588_INGR_VSC85XX_INT_STATUS 0x002d
24 #define MSCC_PHY_1588_VSC85XX_INT_STATUS 0x004d
25 #define VSC85XX_1588_INT_FIFO_ADD 0x0004
26 #define VSC85XX_1588_INT_FIFO_OVERFLOW 0x0001
28 #define MSCC_PHY_1588_INGR_VSC85XX_INT_MASK 0x002e
29 #define MSCC_PHY_1588_VSC85XX_INT_MASK 0x004e
34 #define MSCC_PHY_ANA_ETH1_NTX_PROT 0x0000
[all …]
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| /linux/drivers/phy/cadence/ |
| H A D | phy-cadence-salvo.c | 19 #define USB3_PHY_OFFSET 0x0
20 #define USB2_PHY_OFFSET 0x38000
22 #define PHY_PMA_CMN_CTRL1 0xC800
23 #define TB_ADDR_CMN_DIAG_HSCLK_SEL 0x01e0
24 #define TB_ADDR_CMN_PLL0_VCOCAL_INIT_TMR 0x0084
25 #define TB_ADDR_CMN_PLL0_VCOCAL_ITER_TMR 0x0085
26 #define TB_ADDR_CMN_PLL0_INTDIV 0x0094
27 #define TB_ADDR_CMN_PLL0_FRACDIV 0x0095
28 #define TB_ADDR_CMN_PLL0_HIGH_THR 0x0096
29 #define TB_ADDR_CMN_PLL0_SS_CTRL1 0x0098
[all …]
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