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/freebsd/crypto/openssl/crypto/conf/
H A Dconf_def.h43 0x0008, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
44 0x0000, 0x0010, 0x0010, 0x0000, 0x0000, 0x0010, 0x0000, 0x0000,
45 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
46 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
47 0x0010, 0x0200, 0x0040, 0x0080, 0x1000, 0x0200, 0x0200, 0x0040,
48 0x0000, 0x0000, 0x0200, 0x0200, 0x0200, 0x0200, 0x0200, 0x0200,
49 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001,
50 0x0001, 0x0001, 0x0000, 0x0200, 0x0000, 0x0000, 0x0000, 0x0200,
51 0x0200, 0x0002, 0x0002, 0x0002, 0x0002, 0x0002, 0x0002, 0x0002,
52 0x0002, 0x0002, 0x0002, 0x0002, 0x0002, 0x0002, 0x0002, 0x0002,
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nvidia/
H A Dtegra30-cpu-opp.dtsi10 opp-supported-hw = <0x1F 0x31FE>;
16 opp-supported-hw = <0x1F 0x0C01>;
22 opp-supported-hw = <0x1F 0x0200>;
28 opp-supported-hw = <0x1F 0x31FE>;
34 opp-supported-hw = <0x1F 0x0C01>;
40 opp-supported-hw = <0x1F 0x0200>;
46 opp-supported-hw = <0x1F 0x31FE>;
53 opp-supported-hw = <0x1F 0x0C01>;
60 opp-supported-hw = <0x1F 0x0200>;
67 opp-supported-hw = <0x1F 0x0C00>;
[all …]
H A Dtegra20-cpu-opp.dtsi10 opp-supported-hw = <0x0F 0x0003>;
17 opp-supported-hw = <0x0F 0x0004>;
24 opp-supported-hw = <0x0F 0x0003>;
30 opp-supported-hw = <0x0F 0x0004>;
36 opp-supported-hw = <0x0C 0x0003>;
42 opp-supported-hw = <0x03 0x0006>, <0x04 0x0004>,
43 <0x08 0x0004>;
49 opp-supported-hw = <0x03 0x0001>;
55 opp-supported-hw = <0x08 0x0003>;
61 opp-supported-hw = <0x04 0x0006>, <0x08 0x0004>;
[all …]
H A Dtegra20-peripherals-opp.dtsi50 opp-supported-hw = <0x000F>;
57 opp-supported-hw = <0x000F>;
64 opp-supported-hw = <0x000F>;
71 opp-supported-hw = <0x000F>;
78 opp-supported-hw = <0x000F>;
85 opp-supported-hw = <0x000F>;
92 opp-supported-hw = <0x000F>;
99 opp-supported-hw = <0x000F>;
106 opp-supported-hw = <0x000F>;
113 opp-supported-hw = <0x000F>;
[all …]
/freebsd/sys/dev/mii/
H A Dbmtphyreg.h41 #define MII_BMTPHY_AUX_CTL 0x10 /* auxiliary control */
42 #define AUX_CTL_TXDIS 0x2000 /* transmitter disable */
43 #define AUX_CTL_4B5B_BYPASS 0x0400 /* bypass 4b5b encoder */
44 #define AUX_CTL_SCR_BYPASS 0x0200 /* bypass scrambler */
45 #define AUX_CTL_NRZI_BYPASS 0x0100 /* bypass NRZI encoder */
46 #define AUX_CTL_RXALIGN_BYPASS 0x0080 /* bypass rx symbol alignment */
47 #define AUX_CTL_BASEWANDER_DIS 0x0040 /* disable baseline wander correction */
48 #define AUX_CTL_FEF_EN 0x0020 /* far-end fault enable */
50 #define MII_BMTPHY_AUX_STS 0x11 /* auxiliary status */
51 #define AUX_STS_FX_MODE 0x0400 /* 100base-FX mode (strap pin) */
[all …]
H A De1000phyreg.h72 #define E1000_MAX_REG_ADDRESS 0x1F
74 #define E1000_CR 0x00 /* control register */
75 #define E1000_CR_SPEED_SELECT_MSB 0x0040
76 #define E1000_CR_COLL_TEST_ENABLE 0x0080
77 #define E1000_CR_FULL_DUPLEX 0x0100
78 #define E1000_CR_RESTART_AUTO_NEG 0x0200
79 #define E1000_CR_ISOLATE 0x0400
80 #define E1000_CR_POWER_DOWN 0x0800
81 #define E1000_CR_AUTO_NEG_ENABLE 0x1000
82 #define E1000_CR_SPEED_SELECT_LSB 0x2000
[all …]
H A Dbrgphyreg.h42 #define BRGPHY_MII_BMCR 0x00
43 #define BRGPHY_BMCR_RESET 0x8000
44 #define BRGPHY_BMCR_LOOP 0x4000
45 #define BRGPHY_BMCR_SPD0 0x2000 /* Speed select, lower bit */
46 #define BRGPHY_BMCR_AUTOEN 0x1000 /* Autoneg enabled */
47 #define BRGPHY_BMCR_PDOWN 0x0800 /* Power down */
48 #define BRGPHY_BMCR_ISO 0x0400 /* Isolate */
49 #define BRGPHY_BMCR_STARTNEG 0x0200 /* Restart autoneg */
50 #define BRGPHY_BMCR_FDX 0x0100 /* Duplex mode */
51 #define BRGPHY_BMCR_CTEST 0x0080 /* Collision test enable */
[all …]
H A Dciphyreg.h44 #define CIPHY_MII_BMCR 0x00
45 #define CIPHY_BMCR_RESET 0x8000
46 #define CIPHY_BMCR_LOOP 0x4000
47 #define CIPHY_BMCR_SPD0 0x2000 /* speed select, lower bit */
48 #define CIPHY_BMCR_AUTOEN 0x1000 /* Autoneg enabled */
49 #define CIPHY_BMCR_PDOWN 0x0800 /* Power down */
50 #define CIPHY_BMCR_STARTNEG 0x0200 /* Restart autoneg */
51 #define CIPHY_BMCR_FDX 0x0100 /* Duplex mode */
52 #define CIPHY_BMCR_CTEST 0x0080 /* Collision test enable */
53 #define CIPHY_BMCR_SPD1 0x0040 /* Speed select, upper bit */
[all …]
H A Dmiidevs48 oui AGERE 0x00053d Agere Systems
49 oui ALTIMA 0x0010a9 Altima Communications
50 oui AMD 0x00001a Advanced Micro Devices
51 oui BROADCOM 0x001018 Broadcom Corporation
52 oui BROADCOM2 0x000af7 Broadcom Corporation
53 oui BROADCOM3 0x001be9 Broadcom Corporation
54 oui BROADCOM4 0x18c086 Broadcom Corporation
55 oui CICADA 0x0003f1 Cicada Semiconductor
56 oui DAVICOM 0x00606e Davicom Semiconductor
57 oui ENABLESEMI 0x0010dd Enable Semiconductor
[all …]
/freebsd/sys/dev/sk/
H A Dxmaciireg.h43 #define XM_DEVICEID 0x00E0AE20
44 #define XM_XAQTI_OUI 0x00E0AE
46 #define XM_XMAC_REV(x) (((x) & 0x000000E0) >> 5)
48 #define XM_XMAC_REV_B2 0x0
49 #define XM_XMAC_REV_C1 0x1
51 #define XM_MMUCMD 0x0000
52 #define XM_POFF 0x0008
53 #define XM_BURST 0x000C
54 #define XM_VLAN_TAGLEV1 0x0010
55 #define XM_VLAN_TAGLEV2 0x0014
[all …]
/freebsd/sys/dev/hyperv/netvsc/
H A Dif_hnvar.h107 #define HN_TRUST_HCSUM_IP 0x0001
108 #define HN_TRUST_HCSUM_TCP 0x0002
109 #define HN_TRUST_HCSUM_UDP 0x0004
111 #define HN_RX_FLAG_ATTACHED 0x0001
112 #define HN_RX_FLAG_BR_REF 0x0002
113 #define HN_RX_FLAG_XPNT_VF 0x0004
114 #define HN_RX_FLAG_UDP_HASH 0x0008
185 #define HN_TX_FLAG_ATTACHED 0x0001
186 #define HN_TX_FLAG_HASHVAL 0x0002 /* support HASHVAL pktinfo */
267 int hn_vf_rdytick; /* ticks, 0 == ready */
[all …]
/freebsd/sys/dev/usb/net/
H A Dif_urereg.h30 #define URE_CONFIG_IDX 0 /* config number 1 */
31 #define URE_IFACE_IDX 0
33 #define URE_CTL_READ 0x01
34 #define URE_CTL_WRITE 0x02
39 #define URE_BYTE_EN_DWORD 0xff
40 #define URE_BYTE_EN_WORD 0x33
41 #define URE_BYTE_EN_BYTE 0x11
42 #define URE_BYTE_EN_SIX_BYTES 0x3f
49 #define URE_PLA_IDR 0xc000
50 #define URE_PLA_RCR 0xc010
[all …]
H A Dif_axereg.h46 * the data length (0 to 15) and D represents the direction (0 for vendor read,
50 #define AXE_CMD_IS_WRITE(x) (((x) & 0x0F00) >> 8)
51 #define AXE_CMD_LEN(x) (((x) & 0xF000) >> 12)
52 #define AXE_CMD_CMD(x) ((x) & 0x00FF)
54 #define AXE_172_CMD_READ_RXTX_SRAM 0x2002
55 #define AXE_182_CMD_READ_RXTX_SRAM 0x8002
56 #define AXE_172_CMD_WRITE_RX_SRAM 0x0103
57 #define AXE_182_CMD_WRITE_RXTX_SRAM 0x8103
58 #define AXE_172_CMD_WRITE_TX_SRAM 0x0104
59 #define AXE_CMD_MII_OPMODE_SW 0x0106
[all …]
/freebsd/sys/dev/vte/
H A Dif_vtereg.h36 #define VENDORID_RDC 0x17F3
41 #define DEVICEID_RDC_R6040 0x6040 /* PMX-1000 */
43 /* MAC control register 0 */
44 #define VTE_MCR0 0x00
45 #define MCR0_ACCPT_ERR 0x0001
46 #define MCR0_RX_ENB 0x0002
47 #define MCR0_ACCPT_RUNT 0x0004
48 #define MCR0_ACCPT_LONG_PKT 0x0008
49 #define MCR0_ACCPT_DRIBBLE 0x0010
50 #define MCR0_PROMISC 0x0020
[all …]
/freebsd/sys/dev/usb/controller/
H A Duhcireg.h36 #define PCI_UHCI_BASE_REG 0x20
39 #define PCI_USBREV 0x60 /* USB protocol revision */
40 #define PCI_USB_REV_MASK 0xff
41 #define PCI_USB_REV_PRE_1_0 0x00
42 #define PCI_USB_REV_1_0 0x10
43 #define PCI_USB_REV_1_1 0x11
44 #define PCI_LEGSUP 0xc0 /* Legacy Support register */
45 #define PCI_LEGSUP_USBPIRQDEN 0x2000 /* USB PIRQ D Enable */
46 #define PCI_CBIO 0x20 /* configuration base IO */
47 #define PCI_INTERFACE_UHCI 0x00
[all …]
/freebsd/sys/dev/mwl/
H A Dmwlreg.h41 #define MACREG_REG_TSF_LOW 0xa600 /* TSF lo */
42 #define MACREG_REG_TSF_HIGH 0xa604 /* TSF hi */
43 #define MACREG_REG_CHIP_REV 0xa814 /* chip rev */
45 // Map to 0x80000000 (Bus control) on BAR0
46 #define MACREG_REG_H2A_INTERRUPT_EVENTS 0x00000C18 // (From host to ARM)
47 #define MACREG_REG_H2A_INTERRUPT_CAUSE 0x00000C1C // (From host to ARM)
48 #define MACREG_REG_H2A_INTERRUPT_MASK 0x00000C20 // (From host to ARM)
49 #define MACREG_REG_H2A_INTERRUPT_CLEAR_SEL 0x00000C24 // (From host to ARM)
50 #define MACREG_REG_H2A_INTERRUPT_STATUS_MASK 0x00000C28 // (From host to ARM)
52 #define MACREG_REG_A2H_INTERRUPT_EVENTS 0x00000C2C // (From ARM to host)
[all …]
/freebsd/sys/dev/pci/
H A Dpcireg.h53 #define PCIE_ARI_SLOTMAX 0
59 #define PCI_RID_FUNC_SHIFT 0
74 #define PCIE_ARI_RID2SLOT(rid) (0)
83 #define PCIR_DEVVENDOR 0x00
84 #define PCIR_VENDOR 0x00
85 #define PCIR_DEVICE 0x02
86 #define PCIR_COMMAND 0x04
87 #define PCIM_CMD_PORTEN 0x0001
88 #define PCIM_CMD_MEMEN 0x0002
89 #define PCIM_CMD_BUSMASTEREN 0x0004
[all …]
/freebsd/sys/dev/xl/
H A Dif_xlreg.h35 #define XL_EE_READ 0x0080 /* read, 5 bit address */
36 #define XL_EE_WRITE 0x0040 /* write, 5 bit address */
37 #define XL_EE_ERASE 0x00c0 /* erase, 5 bit address */
38 #define XL_EE_EWEN 0x0030 /* erase, no data needed */
39 #define XL_EE_8BIT_READ 0x0200 /* read, 8 bit address */
40 #define XL_EE_BUSY 0x8000
42 #define XL_EE_EADDR0 0x00 /* station address, first word */
43 #define XL_EE_EADDR1 0x01 /* station address, next word, */
44 #define XL_EE_EADDR2 0x02 /* station address, last word */
45 #define XL_EE_PRODID 0x03 /* product ID code */
[all …]
/freebsd/contrib/wpa/src/utils/
H A Dradiotap.h24 * @it_version: radiotap version, always 0
44 /* version is always 0 */
45 #define PKTHDR_RADIOTAP_VERSION 0
49 IEEE80211_RADIOTAP_TSFT = 0,
81 IEEE80211_RADIOTAP_F_CFP = 0x01,
82 IEEE80211_RADIOTAP_F_SHORTPRE = 0x02,
83 IEEE80211_RADIOTAP_F_WEP = 0x04,
84 IEEE80211_RADIOTAP_F_FRAG = 0x08,
85 IEEE80211_RADIOTAP_F_FCS = 0x10,
86 IEEE80211_RADIOTAP_F_DATAPAD = 0x20,
[all …]
/freebsd/sys/dev/iommu/
H A Diommu_gas.h35 #define IOMMU_MF_CANWAIT 0x0001
36 #define IOMMU_MF_CANSPLIT 0x0002
37 #define IOMMU_MF_RMRR 0x0004
39 #define IOMMU_PGF_WAITOK 0x0001
40 #define IOMMU_PGF_ZERO 0x0002
41 #define IOMMU_PGF_ALLOC 0x0004
42 #define IOMMU_PGF_NOALLOC 0x0008
43 #define IOMMU_PGF_OBJL 0x0010
45 #define IOMMU_MAP_ENTRY_PLACE 0x0001 /* Fake entry */
46 #define IOMMU_MAP_ENTRY_RMRR 0x0002 /* Permanent, not linked by
[all …]
/freebsd/sys/net80211/
H A Dieee80211_radiotap.h70 uint8_t it_version; /* Version 0. Only increases
83 * (0x80000000) to extend the
111 * Tx/Rx data rate. If bit 0x80 is set then it represents an
146 * power set at factory calibration. 0 is max power.
152 * set at factory calibration. 0 is max power. Monotonically
170 * The first antenna is antenna 0.
208 IEEE80211_RADIOTAP_TSFT = 0,
247 #define IEEE80211_CHAN_TURBO 0x00000010 /* Turbo channel */
248 #define IEEE80211_CHAN_CCK 0x00000020 /* CCK channel */
249 #define IEEE80211_CHAN_OFDM 0x0000004
[all...]
/freebsd/sys/dev/le/
H A Dlancereg.h139 #define LE_CSR0 0x0000 /* Control and status register */
140 #define LE_CSR1 0x0001 /* low address of init block */
141 #define LE_CSR2 0x0002 /* high address of init block */
142 #define LE_CSR3 0x0003 /* Bus master and control */
143 #define LE_CSR4 0x0004 /* Test and features control */
144 #define LE_CSR5 0x0005 /* Extended control and Interrupt 1 */
145 #define LE_CSR6 0x0006 /* Rx/Tx Descriptor table length */
146 #define LE_CSR7 0x0007 /* Extended control and interrupt 2 */
147 #define LE_CSR8 0x0008 /* Logical Address Filter 0 */
148 #define LE_CSR9 0x0009 /* Logical Address Filter 1 */
[all …]
/freebsd/sys/gnu/dev/bwn/phy_n/
H A Dif_bwn_phy_n_tables.c84 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
85 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
86 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
87 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
88 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
89 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
90 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
91 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
92 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
93 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
[all …]
/freebsd/sys/dev/smc/
H A Dif_smcreg.h31 /* All Banks, Offset 0xe: Bank Select Register */
32 #define BSR 0xe
33 #define BSR_BANK_MASK 0x0007 /* Which bank is currently selected */
34 #define BSR_IDENTIFY 0x3300 /* Static value for identification */
35 #define BSR_IDENTIFY_MASK 0xff00
37 /* Bank 0, Offset 0x0: Transmit Control Register */
38 #define TCR 0x0
39 #define TCR_TXENA 0x0001 /* Enable/disable transmitter */
40 #define TCR_LOOP 0x0002 /* Put the PHY into loopback mode */
41 #define TCR_FORCOL 0x0004 /* Force a collision */
[all …]
/freebsd/sys/dev/sound/pci/
H A Dallegro_reg.h49 #define PCI_LEGACY_AUDIO_CTRL 0x40
50 #define SOUND_BLASTER_ENABLE 0x00000001
51 #define FM_SYNTHESIS_ENABLE 0x00000002
52 #define GAME_PORT_ENABLE 0x00000004
53 #define MPU401_IO_ENABLE 0x00000008
54 #define MPU401_IRQ_ENABLE 0x00000010
55 #define ALIAS_10BIT_IO 0x00000020
56 #define SB_DMA_MASK 0x000000C0
57 #define SB_DMA_0 0x00000040
58 #define SB_DMA_1 0x00000040
[all …]

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