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/linux/drivers/media/platform/imagination/
H A De5010-core-regs.h14 #define JASPER_CORE_ID_OFFSET (0x0000)
15 #define JASPER_CORE_ID_CR_GROUP_ID_MASK (0xFF000000)
17 #define JASPER_CORE_ID_CR_CORE_ID_MASK (0x00FF0000)
19 #define JASPER_CORE_ID_CR_UNIQUE_NUM_MASK (0x0000FFF8)
21 #define JASPER_CORE_ID_CR_PELS_PER_CYCLE_MASK (0x00000007)
22 #define JASPER_CORE_ID_CR_PELS_PER_CYCLE_SHIFT (0)
24 #define JASPER_CORE_REV_OFFSET (0x0004)
25 #define JASPER_CORE_REV_CR_JASPER_DESIGNER_MASK (0xFF000000)
27 #define JASPER_CORE_REV_CR_JASPER_MAJOR_REV_MASK (0x00FF0000)
29 #define JASPER_CORE_REV_CR_JASPER_MINOR_REV_MASK (0x0000FF00)
[all …]
/linux/drivers/net/wireless/ralink/rt2x00/
H A Drt2400pci.h20 #define RF2420 0x0000
21 #define RF2421 0x0001
32 #define CSR_REG_BASE 0x0000
33 #define CSR_REG_SIZE 0x014c
34 #define EEPROM_BASE 0x0000
35 #define EEPROM_SIZE 0x0100
36 #define BBP_BASE 0x0000
37 #define BBP_SIZE 0x0020
38 #define RF_BASE 0x0004
39 #define RF_SIZE 0x000c
[all …]
H A Drt2500pci.h20 #define RF2522 0x0000
21 #define RF2523 0x0001
22 #define RF2524 0x0002
23 #define RF2525 0x0003
24 #define RF2525E 0x0004
25 #define RF5222 0x0010
43 #define CSR_REG_BASE 0x0000
44 #define CSR_REG_SIZE 0x0174
45 #define EEPROM_BASE 0x0000
46 #define EEPROM_SIZE 0x0200
[all …]
H A Drt2800.h49 #define RF2820 0x0001
50 #define RF2850 0x0002
51 #define RF2720 0x0003
52 #define RF2750 0x0004
53 #define RF3020 0x0005
54 #define RF2020 0x0006
55 #define RF3021 0x0007
56 #define RF3022 0x0008
57 #define RF3052 0x0009
58 #define RF2853 0x000a
[all …]
H A Drt61pci.h20 #define RT2561s_PCI_ID 0x0301
21 #define RT2561_PCI_ID 0x0302
22 #define RT2661_PCI_ID 0x0401
27 #define RF5225 0x0001
28 #define RF5325 0x0002
29 #define RF2527 0x0003
30 #define RF2529 0x0004
41 #define CSR_REG_BASE 0x3000
42 #define CSR_REG_SIZE 0x04b0
43 #define EEPROM_BASE 0x0000
[all …]
H A Drt73usb.h20 #define RF5226 0x0001
21 #define RF2528 0x0002
22 #define RF5225 0x0003
23 #define RF2527 0x0004
34 #define CSR_REG_BASE 0x3000
35 #define CSR_REG_SIZE 0x04b0
36 #define EEPROM_BASE 0x0000
37 #define EEPROM_SIZE 0x0100
38 #define BBP_BASE 0x0000
39 #define BBP_SIZE 0x0080
[all …]
/linux/drivers/gpu/drm/
H A Ddrm_draw.c21 return ((pix & 0x00F80000) >> 8) | in convert_xrgb8888_to_rgb565()
22 ((pix & 0x0000FC00) >> 5) | in convert_xrgb8888_to_rgb565()
23 ((pix & 0x000000F8) >> 3); in convert_xrgb8888_to_rgb565()
28 return ((pix & 0x00f80000) >> 8) | in convert_xrgb8888_to_rgba5551()
29 ((pix & 0x0000f800) >> 5) | in convert_xrgb8888_to_rgba5551()
30 ((pix & 0x000000f8) >> 2) | in convert_xrgb8888_to_rgba5551()
31 BIT(0); /* set alpha bit */ in convert_xrgb8888_to_rgba5551()
36 return ((pix & 0x00f80000) >> 9) | in convert_xrgb8888_to_xrgb1555()
37 ((pix & 0x0000f800) >> 6) | in convert_xrgb8888_to_xrgb1555()
38 ((pix & 0x000000f8) >> 3); in convert_xrgb8888_to_xrgb1555()
[all …]
/linux/drivers/net/ethernet/ti/
H A Dnetcp_xgbepcsr.c13 #define XGBE_CTRL_OFFSET 0x0c
14 #define XGBE_SGMII_1_OFFSET 0x0114
15 #define XGBE_SGMII_2_OFFSET 0x0214
18 #define PCSR_CPU_CTRL_OFFSET 0x1fd0
31 #define PHY_A(serdes) 0
40 {0x0000, 0x00800002, 0x00ff00ff},
41 {0x0014, 0x00003838, 0x0000ffff},
42 {0x0060, 0x1c44e438, 0xffffffff},
43 {0x0064, 0x00c18400, 0x00ffffff},
44 {0x0068, 0x17078200, 0xffffff00},
[all …]
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/
H A Dtable.c6 0x800, 0x80040000,
7 0x804, 0x00000003,
8 0x808, 0x0000FC00,
9 0x80C, 0x0000000A,
10 0x810, 0x10001331,
11 0x814, 0x020C3D10,
12 0x818, 0x02200385,
13 0x81C, 0x00000000,
14 0x820, 0x01000100,
15 0x824, 0x00390204,
[all …]
/linux/arch/mips/include/asm/mach-rc32434/
H A Deth.h33 #define ETH0_BASE_ADDR 0x18060000
84 #define ETH_INT_FC_EN (1 << 0)
90 #define ETH_INT_FC_IOC 0x000000c0
93 #define ETH_FIFI_TT_TTH_BIT 0
94 #define ETH_FIFO_TT_TTH 0x0000007f
97 #define ETH_ARC_PRO (1 << 0)
103 #define ETH_SAL_BYTE_5 0x000000ff
104 #define ETH_SAL_BYTE_4 0x0000ff00
105 #define ETH_SAL_BYTE_3 0x00ff0000
106 #define ETH_SAL_BYTE_2 0xff000000
[all …]
/linux/drivers/video/fbdev/
H A Dpxa168fb.h6 /* Video Frame 0&1 start address registers */
7 #define LCD_SPU_DMA_START_ADDR_Y0 0x00C0
8 #define LCD_SPU_DMA_START_ADDR_U0 0x00C4
9 #define LCD_SPU_DMA_START_ADDR_V0 0x00C8
10 #define LCD_CFG_DMA_START_ADDR_0 0x00CC /* Cmd address */
11 #define LCD_SPU_DMA_START_ADDR_Y1 0x00D0
12 #define LCD_SPU_DMA_START_ADDR_U1 0x00D4
13 #define LCD_SPU_DMA_START_ADDR_V1 0x00D8
14 #define LCD_CFG_DMA_START_ADDR_1 0x00DC /* Cmd address */
17 #define LCD_SPU_DMA_PITCH_YC 0x00E0
[all …]
/linux/drivers/comedi/drivers/
H A Ddt2817.c24 * [0] - I/O port base base address
30 #define DT2817_CR 0
39 unsigned int oe = 0; in dt2817_dio_insn_config()
44 mask = 0x000000ff; in dt2817_dio_insn_config()
46 mask = 0x0000ff00; in dt2817_dio_insn_config()
48 mask = 0x00ff0000; in dt2817_dio_insn_config()
50 mask = 0xff000000; in dt2817_dio_insn_config()
56 if (s->io_bits & 0x000000ff) in dt2817_dio_insn_config()
57 oe |= 0x1; in dt2817_dio_insn_config()
58 if (s->io_bits & 0x0000ff00) in dt2817_dio_insn_config()
[all …]
/linux/arch/arm/mach-omap1/
H A Dsleep.S72 mov r4, #TCMIF_ASM_BASE & 0xff000000
73 orr r4, r4, #TCMIF_ASM_BASE & 0x00ff0000
74 orr r4, r4, #TCMIF_ASM_BASE & 0x0000ff00
78 ldr r5, [r4, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
79 bic r5, r5, #PDE_BIT & 0xff
80 str r5, [r4, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
83 and r5, r5, #PWD_EN_BIT & 0xff
84 str r5, [r4, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
87 ldr r5, [r4, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff]
88 orr r5, r5, #SELF_REFRESH_MODE & 0xff000000
[all …]
H A Dsram.S25 mov r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0xff000000
26 orr r2, r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0x00ff0000
27 orr r2, r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0x0000ff00
29 mov r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0xff000000
30 orr r3, r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0x00ff0000
31 orr r3, r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0x0000ff00
43 mov r4, #0x0700 @ let the clocks settle
44 orr r4, r4, #0x00ff
46 cmp r4, #0
49 lock: ldrh r4, [r2], #0 @ read back dpll value
[all …]
/linux/drivers/net/ethernet/engleder/
H A Dtsnep_hw.h12 #define ECM_TYPE 0x0000
13 #define ECM_REVISION_MASK 0x000000FF
14 #define ECM_REVISION_SHIFT 0
15 #define ECM_VERSION_MASK 0x0000FF00
17 #define ECM_QUEUE_COUNT_MASK 0x00070000
19 #define ECM_GATE_CONTROL 0x02000000
22 #define ECM_SYSTEM_TIME_LOW 0x0008
23 #define ECM_SYSTEM_TIME_HIGH 0x000C
26 #define ECM_CLOCK_RATE 0x0010
27 #define ECM_CLOCK_RATE_OFFSET_MASK 0x7FFFFFFF
[all …]
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/
H A Dtable.c7 0x800, 0x80040000,
8 0x804, 0x00000003,
9 0x808, 0x0000fc00,
10 0x80c, 0x0000000a,
11 0x810, 0x10005388,
12 0x814, 0x020c3d10,
13 0x818, 0x02200385,
14 0x81c, 0x00000000,
15 0x820, 0x01000100,
16 0x824, 0x00390004,
[all …]
/linux/arch/sh/drivers/pci/
H A Dpci-sh7751.h13 #define SH7751_VENDOR_ID 0x1054
14 #define SH7751_DEVICE_ID 0x3505
15 #define SH7751R_DEVICE_ID 0x350e
18 #define SH7751_PCI_CONFIG_BASE 0xFD000000 /* Config space base addr */
19 #define SH7751_PCI_CONFIG_SIZE 0x1000000 /* Config space size */
20 #define SH7751_PCI_MEMORY_BASE 0xFD000000 /* Memory space base addr */
21 #define SH7751_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */
22 #define SH7751_PCI_IO_BASE 0xFE240000 /* IO space base address */
23 #define SH7751_PCI_IO_SIZE 0x40000 /* Size of IO window */
25 #define SH7751_PCIREG_BASE 0xFE200000 /* PCI regs base address */
[all …]
/linux/drivers/media/usb/cx231xx/
H A Dcx231xx-reg.h17 #define SAV_ACTIVE_VIDEO_FIELD1 0x80
18 #define EAV_ACTIVE_VIDEO_FIELD1 0x90
20 #define SAV_ACTIVE_VIDEO_FIELD2 0xc0
21 #define EAV_ACTIVE_VIDEO_FIELD2 0xd0
23 #define SAV_VBLANK_FIELD1 0xa0
24 #define EAV_VBLANK_FIELD1 0xb0
26 #define SAV_VBLANK_FIELD2 0xe0
27 #define EAV_VBLANK_FIELD2 0xf0
29 #define SAV_VBI_FIELD1 0x20
30 #define EAV_VBI_FIELD1 0x30
[all …]
/linux/drivers/net/ethernet/qlogic/qed/
H A Dqed_mfw_hsi.h9 #define MFW_TRACE_SIGNATURE 0x25071946
12 #define MFW_TRACE_EVENTID_MASK 0x00ffff
13 #define MFW_TRACE_PRM_SIZE_MASK 0x0f0000
22 * 0 - just errors will be written to the buffer
24 u32 modules_mask[2]; /* a bit per module, 1 means write it, 0 means
53 #define OFFSIZE_OFFSET_SHIFT 0
54 #define OFFSIZE_OFFSET_MASK 0x0000ffff
57 #define OFFSIZE_SIZE_MASK 0xffff0000
77 #define ETH_SPEED_AUTONEG 0x0
78 #define ETH_SPEED_SMARTLINQ 0x8
[all …]
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8192du/
H A Dtable.c9 0x800, 0x80040002,
10 0x804, 0x00000003,
11 0x808, 0x0000fc00,
12 0x80c, 0x0000000a,
13 0x810, 0x10001331,
14 0x814, 0x020c3d10,
15 0x818, 0x02200385,
16 0x81c, 0x00000000,
17 0x820, 0x01000100,
18 0x824, 0x00390004,
[all …]
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8192de/
H A Dtable.c9 0x024, 0x0011800d,
10 0x028, 0x00ffdb83,
11 0x014, 0x088ba955,
12 0x010, 0x49022b03,
13 0x800, 0x80040002,
14 0x804, 0x00000003,
15 0x808, 0x0000fc00,
16 0x80c, 0x0000000a,
17 0x810, 0x80706388,
18 0x814, 0x020c3d10,
[all …]
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8192cu/
H A Dtable.c7 0x024, 0x0011800f,
8 0x028, 0x00ffdb83,
9 0x800, 0x80040002,
10 0x804, 0x00000003,
11 0x808, 0x0000fc00,
12 0x80c, 0x0000000a,
13 0x810, 0x10000330,
14 0x814, 0x020c3d10,
15 0x818, 0x02200385,
16 0x81c, 0x00000000,
[all …]
/linux/drivers/net/ethernet/aquantia/atlantic/hw_atl/
H A Dhw_atl_b0_internal.h26 #define HW_ATL_B0_MAC 0U
36 #define HW_ATL_B0_INT_MASK (0xFFFFFFFFU)
38 #define HW_ATL_B0_TXD_CTL2_LEN (0xFFFFC000)
39 #define HW_ATL_B0_TXD_CTL2_CTX_EN (0x00002000)
40 #define HW_ATL_B0_TXD_CTL2_CTX_IDX (0x00001000)
42 #define HW_ATL_B0_TXD_CTL_DESC_TYPE_TXD (0x00000001)
43 #define HW_ATL_B0_TXD_CTL_DESC_TYPE_TXC (0x00000002)
44 #define HW_ATL_B0_TXD_CTL_BLEN (0x000FFFF0)
45 #define HW_ATL_B0_TXD_CTL_DD (0x00100000)
46 #define HW_ATL_B0_TXD_CTL_EOP (0x00200000)
[all …]
/linux/drivers/net/wireless/ath/ath9k/
H A Dar9002_phy.h19 #define AR_PHY_TEST 0x9800
20 #define PHY_AGC_CLR 0x10000000
21 #define RFSILENT_BB 0x00002000
23 #define AR_PHY_TURBO 0x9804
24 #define AR_PHY_FC_TURBO_MODE 0x00000001
25 #define AR_PHY_FC_TURBO_SHORT 0x00000002
26 #define AR_PHY_FC_DYN2040_EN 0x00000004
27 #define AR_PHY_FC_DYN2040_PRI_ONLY 0x00000008
28 #define AR_PHY_FC_DYN2040_PRI_CH 0x00000010
30 #define AR_PHY_FC_DYN2040_EXT_CH 0x00000020
[all …]
/linux/drivers/media/rc/img-ir/
H A Dimg-ir.h20 #define IMG_IR_CONTROL 0x00
21 #define IMG_IR_STATUS 0x04
22 #define IMG_IR_DATA_LW 0x08
23 #define IMG_IR_DATA_UP 0x0c
24 #define IMG_IR_LEAD_SYMB_TIMING 0x10
25 #define IMG_IR_S00_SYMB_TIMING 0x14
26 #define IMG_IR_S01_SYMB_TIMING 0x18
27 #define IMG_IR_S10_SYMB_TIMING 0x1c
28 #define IMG_IR_S11_SYMB_TIMING 0x20
29 #define IMG_IR_FREE_SYMB_TIMING 0x24
[all …]

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