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/linux/arch/riscv/boot/dts/sophgo/
H A Dsg2042.dtsi28 #clock-cells = <0>;
34 #clock-cells = <0>;
40 #clock-cells = <0>;
52 reg = <0x70 0x30005000 0x0 0x1000>;
54 #size-cells = <0>;
65 reg = <0x70 0x30006000 0x0 0x1000>;
67 #size-cells = <0>;
78 reg = <0x70 0x30007000 0x0 0x1000>;
80 #size-cells = <0>;
91 reg = <0x70 0x30008000 0x0 0x1000>;
[all …]
/linux/arch/arm/boot/dts/nvidia/
H A Dtegra124-nyan-blaze-emc.dtsi92 0x40040001
93 0x8000000a
94 0x00000001
95 0x00000001
96 0x00000002
97 0x00000000
98 0x00000002
99 0x00000001
100 0x00000002
101 0x00000008
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/nbio/
H A Dnbio_2_3_default.h26 #define mmBIF_BX_PF_MM_INDEX_DEFAULT 0x00000000
27 #define mmBIF_BX_PF_MM_DATA_DEFAULT 0x00000000
28 #define mmBIF_BX_PF_MM_INDEX_HI_DEFAULT 0x00000000
32 #define mmSYSHUB_INDEX_OVLP_DEFAULT 0x00000000
33 #define mmSYSHUB_DATA_OVLP_DEFAULT 0x00000000
34 #define mmPCIE_INDEX_DEFAULT 0x00000000
35 #define mmPCIE_DATA_DEFAULT 0x00000000
36 #define mmPCIE_INDEX2_DEFAULT 0x00000000
37 #define mmPCIE_DATA2_DEFAULT 0x00000000
38 #define mmSBIOS_SCRATCH_0_DEFAULT 0x00000000
[all …]
H A Dnbio_7_0_default.h26 #define cfgNB_NBCFG0_NB_VENDOR_ID_DEFAULT 0x00000000
27 #define cfgNB_NBCFG0_NB_DEVICE_ID_DEFAULT 0x00000000
28 #define cfgNB_NBCFG0_NB_COMMAND_DEFAULT 0x00000000
29 #define cfgNB_NBCFG0_NB_STATUS_DEFAULT 0x00000000
30 #define cfgNB_NBCFG0_NB_REVISION_ID_DEFAULT 0x00000000
31 #define cfgNB_NBCFG0_NB_REGPROG_INF_DEFAULT 0x00000000
32 #define cfgNB_NBCFG0_NB_SUB_CLASS_DEFAULT 0x00000000
33 #define cfgNB_NBCFG0_NB_BASE_CODE_DEFAULT 0x00000000
34 #define cfgNB_NBCFG0_NB_CACHE_LINE_DEFAULT 0x00000000
35 #define cfgNB_NBCFG0_NB_LATENCY_DEFAULT 0x00000000
[all …]
/linux/drivers/parisc/
H A Dlasi.c29 #define LASI_VER 0xC008 /* LASI Version */
31 #define LASI_IO_CONF 0x7FFFE /* LASI primary configuration register */
32 #define LASI_IO_CONF2 0x7FFFF /* LASI secondary configuration register */
39 case 0x74: irq = 7; break; /* Centronics */ in lasi_choose_irq()
40 case 0x7B: irq = 13; break; /* Audio */ in lasi_choose_irq()
41 case 0x81: irq = 14; break; /* Lasi itself */ in lasi_choose_irq()
42 case 0x82: irq = 9; break; /* SCSI */ in lasi_choose_irq()
43 case 0x83: irq = 20; break; /* Floppy */ in lasi_choose_irq()
44 case 0x84: irq = 26; break; /* PS/2 Keyboard */ in lasi_choose_irq()
45 case 0x87: irq = 18; break; /* ISDN */ in lasi_choose_irq()
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
H A Dramnv40.c43 ret = nvbios_pll_parse(bios, 0x04, &pll); in nv40_ram_calc()
50 if (ret < 0) in nv40_ram_calc()
53 ram->ctrl = 0x80000000 | (log2P << 16); in nv40_ram_calc()
56 ram->ctrl |= 0x00000100; in nv40_ram_calc()
59 ram->ctrl |= 0x40000000; in nv40_ram_calc()
63 return 0; in nv40_ram_calc()
74 u32 crtc_mask = 0; in nv40_ram_prog()
79 for (i = 0; i < 2; i++) { in nv40_ram_prog()
80 u32 vbl = nvkm_rd32(device, 0x600808 + (i * 0x2000)); in nv40_ram_prog()
81 u32 cnt = 0; in nv40_ram_prog()
[all …]
/linux/sound/soc/fsl/
H A Dfsl_dma.h10 u8 res0[0x100];
30 u8 res2[0x38];
35 #define CCSR_DMA_MR_BWC_DISABLED 0x0F000000
37 #define CCSR_DMA_MR_BWC_MASK 0x0F000000
40 #define CCSR_DMA_MR_EMP_EN 0x00200000
41 #define CCSR_DMA_MR_EMS_EN 0x00040000
42 #define CCSR_DMA_MR_DAHTS_MASK 0x00030000
43 #define CCSR_DMA_MR_DAHTS_1 0x00000000
44 #define CCSR_DMA_MR_DAHTS_2 0x00010000
45 #define CCSR_DMA_MR_DAHTS_4 0x00020000
[all …]
/linux/drivers/gpu/drm/etnaviv/
H A Dstate.xml.h7 http://0x04.net/cgit/index.cgi/rules-ng-ng
8 git clone git://0x04.net/rules-ng-ng
48 #define VARYING_COMPONENT_USE_UNUSED 0x00000000
49 #define VARYING_COMPONENT_USE_USED 0x00000001
50 #define VARYING_COMPONENT_USE_POINTCOORD_X 0x00000002
51 #define VARYING_COMPONENT_USE_POINTCOORD_Y 0x00000003
52 #define FE_DATA_TYPE_BYTE 0x00000000
53 #define FE_DATA_TYPE_UNSIGNED_BYTE 0x00000001
54 #define FE_DATA_TYPE_SHORT 0x00000002
55 #define FE_DATA_TYPE_UNSIGNED_SHORT 0x00000003
[all …]
/linux/drivers/media/platform/nxp/
H A Dimx-pxp.h13 #define HW_PXP_CTRL (0x00000000)
14 #define HW_PXP_CTRL_SET (0x00000004)
15 #define HW_PXP_CTRL_CLR (0x00000008)
16 #define HW_PXP_CTRL_TOG (0x0000000c)
18 #define BM_PXP_CTRL_SFTRST 0x80000000
21 #define BM_PXP_CTRL_CLKGATE 0x40000000
24 #define BM_PXP_CTRL_RSVD4 0x20000000
27 #define BM_PXP_CTRL_EN_REPEAT 0x10000000
30 #define BM_PXP_CTRL_ENABLE_ROTATE1 0x08000000
33 #define BM_PXP_CTRL_ENABLE_ROTATE0 0x04000000
[all …]
/linux/arch/mips/boot/dts/loongson/
H A Drs780e-pch.dtsi8 ranges = <0 0x10000000 0 0x10000000 0 0x10000000
9 0 0x40000000 0 0x40000000 0 0x40000000
10 0xfd 0xfe000000 0xfd 0xfe000000 0 0x2000000 /* PCI Config Space */>;
18 reg = <0 0x1a000000 0 0x02000000>;
20 ranges = <0x01000000 0 0x00004000 0 0x18004000 0 0x0000c000>,
21 <0x02000000 0 0x40000000 0 0x40000000 0 0x40000000>;
28 ranges = <1 0 0 0x18000000 0x4000>;
32 reg = <1 0x70 0x8>;
39 reg = <1 0x800 0x100>;
H A Dloongson64v_4core_virtio.dts12 #address-cells = <0>;
22 ranges = <0 0x1fe00000 0 0x1fe00000 0x100000
23 0 0x3ff00000 0 0x3ff00000 0x100000
24 0xefd 0xfb000000 0xefd 0xfb000000 0x10000000>;
28 reg = <0 0x3ff01400 0x64>;
37 loongson,parent_int_map = <0x00000001>, /* int0 */
38 <0xfffffffe>, /* int1 */
39 <0x00000000>, /* int2 */
40 <0x00000000>; /* int3 */
46 reg = <0 0x1fe001e0 0x8>;
[all …]
/linux/Documentation/devicetree/bindings/soc/fsl/cpm_qe/
H A Dfsl,qe-muram.yaml62 ranges = <0 0x00010000 0x0000c000>;
66 data-only@0{
69 reg = <0 0xc000>;
/linux/include/soc/fsl/qe/
H A Dqe.h34 QE_CLK_NONE = 0,
150 return 0; in cpm_muram_dma()
245 return 0; in qe_alive_during_sleep()
291 u8 split; /* 0 = shared I-RAM, 1 = split I-RAM */
304 __be32 traps[16]; /* Trap addresses, 0 == ignore */
348 #define BD_STATUS_MASK 0xffff0000
349 #define BD_LENGTH_MASK 0x0000ffff
357 #define QE_RISC_ALLOCATION_RISC1 0x1 /* RISC 1 */
358 #define QE_RISC_ALLOCATION_RISC2 0x2 /* RISC 2 */
359 #define QE_RISC_ALLOCATION_RISC3 0x4 /* RISC 3 */
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
H A Dtu102.c46 nvkm_wr32(device, device->vfn->addr.user + 0x0090, chan->func->doorbell_handle(chan)); in tu102_chan_start()
67 return nvkm_rd32(device, 0x002b0c + (runl->id * 0x10)) & 0x00008000; in tu102_runl_pending()
77 nvkm_wr32(device, 0x002b00 + (runl->id * 0x10), lower_32_bits(addr)); in tu102_runl_commit()
78 nvkm_wr32(device, 0x002b04 + (runl->id * 0x10), upper_32_bits(addr)); in tu102_runl_commit()
79 nvkm_wr32(device, 0x002b08 + (runl->id * 0x10), count); in tu102_runl_commit()
100 { 0x01, "DISPLAY" },
101 { 0x03, "PTP" },
102 { 0x06, "PWR_PMU" },
103 { 0x08, "IFB", NULL, NVKM_ENGINE_IFB },
104 { 0x09, "PERF" },
[all …]
H A Dregsnv04.h5 #define NV04_PFIFO_DELAY_0 0x00002040
6 #define NV04_PFIFO_DMA_TIMESLICE 0x00002044
7 #define NV04_PFIFO_NEXT_CHANNEL 0x00002050
8 #define NV03_PFIFO_INTR_0 0x00002100
9 #define NV03_PFIFO_INTR_EN_0 0x00002140
10 # define NV_PFIFO_INTR_CACHE_ERROR (1<<0)
17 #define NV03_PFIFO_RAMHT 0x00002210
18 #define NV03_PFIFO_RAMFC 0x00002214
19 #define NV03_PFIFO_RAMRO 0x00002218
20 #define NV40_PFIFO_RAMFC 0x00002220
[all …]
/linux/arch/sh/include/asm/
H A Ddma-register.h14 #define SAR 0x00 /* Source Address Register */
15 #define DAR 0x04 /* Destination Address Register */
16 #define TCR 0x08 /* Transfer Count Register */
17 #define CHCR 0x0C /* Channel Control Register */
18 #define DMAOR 0x40 /* DMA Operation Register */
21 #define DMAOR_AE 0x00000004 /* Address Error Flag */
22 #define DMAOR_NMIF 0x00000002
23 #define DMAOR_DME 0x00000001 /* DMA Master Enable */
26 #define REQ_L 0x00000000
27 #define REQ_E 0x00080000
[all …]
/linux/include/linux/mtd/
H A Dndfc.h12 #define NDFC_CMD 0x00
13 #define NDFC_ALE 0x04
14 #define NDFC_DATA 0x08
15 #define NDFC_ECC 0x10
16 #define NDFC_BCFG0 0x30
17 #define NDFC_BCFG1 0x34
18 #define NDFC_BCFG2 0x38
19 #define NDFC_BCFG3 0x3c
20 #define NDFC_CCR 0x40
21 #define NDFC_STAT 0x44
[all …]
/linux/drivers/net/ethernet/intel/ixgbe/
H A Dixgbe_dcb_82598.h10 #define IXGBE_DPMCS_TDPAC 0x00000001 /* 0 Round Robin, 1 DFP - Deficit Fixed Priority */
11 #define IXGBE_DPMCS_TRM 0x00000010 /* Transmit Recycle Mode */
12 #define IXGBE_DPMCS_ARBDIS 0x00000040 /* DCB arbiter disable */
13 #define IXGBE_DPMCS_TSOEF 0x00080000 /* TSO Expand Factor: 0=x4, 1=x2 */
15 #define IXGBE_RUPPBMR_MQA 0x80000000 /* Enable UP to queue mapping */
18 #define IXGBE_RT2CR_LSP 0x80000000 /* LSP enable bit */
20 #define IXGBE_RDRXCTL_MPBEN 0x00000010 /* DMA config for multiple packet buffers enable */
21 #define IXGBE_RDRXCTL_MCEN 0x00000040 /* DMA config for multiple cores (RSS) enable */
25 #define IXGBE_TDTQ2TCCR_GSP 0x40000000
26 #define IXGBE_TDTQ2TCCR_LSP 0x80000000
[all …]
/linux/drivers/infiniband/hw/irdma/
H A Dicrdma_hw.h8 #define VFPE_CQPTAIL1 0x0000a000
9 #define VFPE_CQPDB1 0x0000bc00
10 #define VFPE_CCQPSTATUS1 0x0000b800
11 #define VFPE_CCQPHIGH1 0x00009800
12 #define VFPE_CCQPLOW1 0x0000ac00
13 #define VFPE_CQARM1 0x0000b400
14 #define VFPE_CQARM1 0x0000b400
15 #define VFPE_CQACK1 0x0000b000
16 #define VFPE_AEQALLOC1 0x0000a400
17 #define VFPE_CQPERRCODES1 0x00009c00
[all …]
/linux/sound/soc/mxs/
H A Dmxs-saif.h10 #define SAIF_CTRL 0x0
11 #define SAIF_STAT 0x10
12 #define SAIF_DATA 0x20
13 #define SAIF_VERSION 0X30
16 #define BM_SAIF_CTRL_SFTRST 0x80000000
17 #define BM_SAIF_CTRL_CLKGATE 0x40000000
19 #define BM_SAIF_CTRL_BITCLK_MULT_RATE 0x38000000
22 #define BM_SAIF_CTRL_BITCLK_BASE_RATE 0x04000000
23 #define BM_SAIF_CTRL_FIFO_ERROR_IRQ_EN 0x02000000
24 #define BM_SAIF_CTRL_FIFO_SERVICE_IRQ_EN 0x01000000
[all …]
/linux/arch/s390/include/uapi/asm/
H A Dptrace.h19 #define PT_PSWMASK 0x00
20 #define PT_PSWADDR 0x04
21 #define PT_GPR0 0x08
22 #define PT_GPR1 0x0C
23 #define PT_GPR2 0x10
24 #define PT_GPR3 0x14
25 #define PT_GPR4 0x18
26 #define PT_GPR5 0x1C
27 #define PT_GPR6 0x20
28 #define PT_GPR7 0x24
[all …]
/linux/arch/powerpc/boot/dts/
H A Da3m071.dts26 ranges = <0 0xf0000000 0x0000c000>;
27 reg = <0xf0000000 0x00000100>;
28 bus-frequency = <0>; /* From boot loader */
29 system-frequency = <0>; /* From boot loader */
41 reg = <0x2000 0x100>;
42 interrupts = <2 1 0>;
63 reg = <0x2c00 0x100>;
64 interrupts = <2 4 0>;
73 reg = <0x03>;
94 ranges = <0 0 0xfc000000 0x02000000
[all …]
/linux/include/linux/
H A Dsh_dma.h95 #define DMAOR_AE 0x00000004 /* Address Error Flag */
96 #define DMAOR_NMIF 0x00000002
97 #define DMAOR_DME 0x00000001 /* DMA Master Enable */
100 #define DM_INC 0x00004000 /* Destination addresses are incremented */
101 #define DM_DEC 0x00008000 /* Destination addresses are decremented */
102 #define DM_FIX 0x0000c000 /* Destination address is fixed */
103 #define SM_INC 0x00001000 /* Source addresses are incremented */
104 #define SM_DEC 0x00002000 /* Source addresses are decremented */
105 #define SM_FIX 0x00003000 /* Source address is fixed */
106 #define RS_AUTO 0x00000400 /* Auto Request */
[all …]
/linux/tools/testing/selftests/powerpc/nx-gzip/include/
H A Dcrb.h11 #define CCW_CI_842 (0x00003ff8)
12 #define CCW_FC_842 (0x00000007)
16 #define CCB_VALUE (0x3fffffffffffffff)
17 #define CCB_ADDRESS (0xfffffffffffffff8)
18 #define CCB_CM (0x0000000000000007)
19 #define CCB_CM0 (0x0000000000000004)
20 #define CCB_CM12 (0x0000000000000003)
22 #define CCB_CM0_ALL_COMPLETIONS (0x0)
23 #define CCB_CM0_LAST_IN_CHAIN (0x4)
24 #define CCB_CM12_STORE (0x0)
[all …]
/linux/drivers/video/fbdev/mb862xx/
H A Dmb862xx_reg.h9 #define MB862XX_MMIO_BASE 0x01fc0000
10 #define MB862XX_MMIO_HIGH_BASE 0x03fc0000
11 #define MB862XX_I2C_BASE 0x0000c000
12 #define MB862XX_DISP_BASE 0x00010000
13 #define MB862XX_CAP_BASE 0x00018000
14 #define MB862XX_DRAW_BASE 0x00030000
15 #define MB862XX_GEO_BASE 0x00038000
16 #define MB862XX_PIO_BASE 0x00038000
17 #define MB862XX_MMIO_SIZE 0x40000
20 #define GC_IST 0x00000020
[all …]

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