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/freebsd/sys/contrib/device-tree/src/arm/broadcom/
H A Dbcm-ns.dtsi26 ranges = <0x00000000 0x18000000 0x00001000>;
32 reg = <0x0300 0x100>;
40 reg = <0x0400 0x100>;
44 pinctrl-0 = <&pinmux_uart1>;
51 ranges = <0x00000000 0x1900000
[all...]
/freebsd/sys/contrib/dev/rtw89/
H A Drtw8852a_rfk_table.c8 RTW89_DECL_RFK_WM(0x12a8, 0x00000001, 0x00000001),
9 RTW89_DECL_RFK_WM(0x12a8, 0x0000000e, 0x00000002),
10 RTW89_DECL_RFK_WM(0x32a8, 0x00000001, 0x00000001),
11 RTW89_DECL_RFK_WM(0x32a8, 0x0000000e, 0x00000002),
12 RTW89_DECL_RFK_WM(0x12bc, 0x000000f0, 0x00000005),
13 RTW89_DECL_RFK_WM(0x12bc, 0x00000f00, 0x00000005),
14 RTW89_DECL_RFK_WM(0x12bc, 0x000f0000, 0x00000005),
15 RTW89_DECL_RFK_WM(0x12bc, 0x0000f000, 0x00000005),
16 RTW89_DECL_RFK_WM(0x120c, 0x000000ff, 0x00000033),
17 RTW89_DECL_RFK_WM(0x12c0, 0x0ff00000, 0x00000033),
[all …]
H A Drtw8851b_rfk_table.c8 RTW89_DECL_RFK_WM(0xc210, 0x003fc000, 0x80),
9 RTW89_DECL_RFK_WM(0xc224, 0x003fc000, 0x80),
10 RTW89_DECL_RFK_WM(0xc0f8, 0x30000000, 0x3),
11 RTW89_DECL_RFK_WM(0x12b8, BIT(30), 0x1),
12 RTW89_DECL_RFK_WM(0x030c, 0x1f000000, 0x1f),
13 RTW89_DECL_RFK_WM(0x032c, 0xc0000000, 0x0),
14 RTW89_DECL_RFK_WM(0x032c, BIT(22), 0x0),
15 RTW89_DECL_RFK_WM(0x032c, BIT(22), 0x1),
16 RTW89_DECL_RFK_WM(0x032c, BIT(16), 0x0),
17 RTW89_DECL_RFK_WM(0x032c, BIT(20), 0x1),
[all …]
H A Drtw8852b_rfk_table.c8 RTW89_DECL_RFK_WM(0xC0D4, 0xffffffff, 0x4486888c),
9 RTW89_DECL_RFK_WM(0xC0D8, 0xffffffff, 0xc6ba10e0),
10 RTW89_DECL_RFK_WM(0xc0dc, 0xffffffff, 0x30c52868),
11 RTW89_DECL_RFK_WM(0xc0e0, 0xffffffff, 0x05008128),
12 RTW89_DECL_RFK_WM(0xc0e4, 0xffffffff, 0x0000272b),
13 RTW89_DECL_RFK_WM(0xC1D4, 0xffffffff, 0x4486888c),
14 RTW89_DECL_RFK_WM(0xC1D8, 0xffffffff, 0xc6ba10e0),
15 RTW89_DECL_RFK_WM(0xc1dc, 0xffffffff, 0x30c52868),
16 RTW89_DECL_RFK_WM(0xc1e0, 0xffffffff, 0x05008128),
17 RTW89_DECL_RFK_WM(0xc1e4, 0xffffffff, 0x0000272b),
[all …]
/freebsd/sys/dev/ath/ath_hal/ar9002/
H A Dar9285an.h25 #define AR9285_AN_RF2G1 0x7820
27 #define AR9285_AN_RF2G1_ENPACAL 0x00000800
29 #define AR9285_AN_RF2G1_PDPADRV1 0x02000000
31 #define AR9285_AN_RF2G1_PDPADRV2 0x01000000
33 #define AR9285_AN_RF2G1_PDPAOUT 0x00800000
36 #define AR9285_AN_RF2G2 0x7824
38 #define AR9285_AN_RF2G2_OFFCAL 0x00001000
41 #define AR9285_AN_RF2G3 0x7828
43 #define AR9285_AN_RF2G3_PDVCCOMP 0x02000000
45 #define AR9285_AN_RF2G3_OB_0 0x00E00000
[all …]
H A Dar9285phy.h31 #define AR9285_AN_RF2G1 0x7820
32 #define AR9285_AN_RF2G1_ENPACAL 0x00000800
34 #define AR9285_AN_RF2G1_PDPADRV1 0x02000000
36 #define AR9285_AN_RF2G1_PDPADRV2 0x01000000
38 #define AR9285_AN_RF2G1_PDPAOUT 0x00800000
41 #define AR9285_AN_RF2G2 0x7824
42 #define AR9285_AN_RF2G2_OFFCAL 0x00001000
45 #define AR9285_AN_RF2G3 0x7828
46 #define AR9285_AN_RF2G3_PDVCCOMP 0x02000000
48 #define AR9285_AN_RF2G3_OB_0 0x00E00000
[all …]
/freebsd/sys/dev/sound/pci/
H A Dich.h30 #define PCIR_NAMBAR 0x10
31 #define PCIR_NABMBAR 0x14
33 #define PCIR_MMBAR 0x18
34 #define PCIR_MBBAR 0x1C
36 #define PCIR_ICH_LEGACY 0x41
37 #define ICH_LEGACY_ENABLE 0x01
40 #define ICH_REG_X_BDBAR 0x00
41 #define ICH_REG_X_CIV 0x04
42 #define ICH_REG_X_LVI 0x05
43 #define ICH_REG_X_SR 0x06
[all …]
/freebsd/sys/contrib/device-tree/Bindings/ata/
H A Dnvidia,tegra-ahci.yaml67 - const: sata-0
164 reg = <0x70027000 0x00002000>, /* AHCI */
165 <0x70020000 0x00007000>, /* SATA */
166 <0x70001100 0x00010000>; /* SATA AUX */
/freebsd/sys/dev/qlnx/qlnxe/
H A Decore_init_values.h35 0x00030003, 0xffff0000, /* if phase != 'engine', skip 3 ops (no DMAE) */
36 0x00020002, 0x00020000, /* if mode != '!asic', skip 2 ops */
37 0x0280c201, 0x00000000, /* write 0x0 to address 0x50184 */
38 0x02810201, 0x00000000, /* write 0x0 to address 0x50204 */
40 0x00110003, 0xffff0000, /* if phase != 'engine', skip 17 ops (no DMAE) */
41 0x00030002, 0x00020000, /* if mode != '!asic', skip 3 ops */
42 0x0048c201, 0x00000000, /* write 0x0 to address 0x9184 */
43 0x0048d201, 0x00000000, /* write 0x0 to address 0x91a4 */
44 0x004ba601, 0x00000001, /* write 0x1 to address 0x974c */
45 0x00020002, 0x00be0000, /* if mode != '(!asic)&bb', skip 2 ops */
[all …]
/freebsd/sys/arm/ti/
H A Dti_adcreg.h30 #define ADC_REVISION 0x000
31 #define ADC_REV_SCHEME_MSK 0xc0000000
33 #define ADC_REV_FUNC_MSK 0x0fff0000
35 #define ADC_REV_RTL_MSK 0x0000f800
37 #define ADC_REV_MAJOR_MSK 0x00000700
39 #define ADC_REV_CUSTOM_MSK 0x000000c0
41 #define ADC_REV_MINOR_MSK 0x0000003f
42 #define ADC_SYSCFG 0x010
43 #define ADC_SYSCFG_IDLE_MSK 0x000000c0
45 #define ADC_IRQSTATUS_RAW 0x024
[all …]
/freebsd/sys/contrib/device-tree/src/arm/sigmastar/
H A Dmstar-v7.dtsi18 #size-cells = <0>;
20 cpu0: cpu@0 {
23 reg = <0x0>;
55 #clock-cells = <0>;
61 #clock-cells = <0>;
68 #clock-cells = <0>;
80 ranges = <0x16001000 0x16001000 0x00007000>,
81 <0x1f000000 0x1f000000 0x00400000>,
82 <0xa0000000 0xa0000000 0x20000>;
86 reg = <0x16001000 0x1000>,
[all …]
/freebsd/sys/dev/cxgbe/firmware/
H A Dt4fw_cfg.txt18 reg[0x7d04] = 0x00010000/0x00010000
21 reg[0x7d6c] = 0x00000000/0x00007000
23 reg[0x7dc0] = 0x0e2f8849 # TP_SHIFT_CNT
31 # TP number of RX channels (0 = auto)
32 tp_nrxch = 0
37 # TP number of TX channels (0 = auto)
38 tp_ntxch = 0
46 # PFs 0-3. These get 8 MSI/8 MSI-X vectors each. VFs are supported by
48 [function "0"]
52 rssnvi = 0
[all …]
H A Dt5fw_cfg_hashfilter.txt23 reg[0x1124] = 0x00000400/0x00000400 # SGE_CONTROL2, enable VFIFO; if
28 reg[0x1130] = 0x00d5ffeb # SGE_DBP_FETCH_THRESHOLD, fetch
31 # queues, and 0xfff for LP which
36 reg[0x113c] = 0x0002ffc0 # SGE_VFIFO_SIZE, set to 0x2ffc0 which
42 reg[0x7d04] = 0x00010000/0x00010000
45 reg[0x7d6c] = 0x00000000/0x00007000
48 reg[0x7d78] = 0x00000400/0x00000000
50 reg[0x7dc0] = 0x0e2f8849 # TP_SHIFT_CNT
58 # TP number of RX channels (0 = auto)
59 tp_nrxch = 0
[all …]
H A Dt5fw_cfg.txt23 reg[0x1124] = 0x00000400/0x00000400 # SGE_CONTROL2, enable VFIFO; if
28 reg[0x1130] = 0x00d5ffeb # SGE_DBP_FETCH_THRESHOLD, fetch
31 # queues, and 0xfff for LP which
36 reg[0x113c] = 0x0002ffc0 # SGE_VFIFO_SIZE, set to 0x2ffc0 which
42 reg[0x7d04] = 0x00010000/0x00010000
45 reg[0x7d6c] = 0x00000000/0x00007000
48 reg[0x7d78] = 0x00000400/0x00000000
50 reg[0x7dc0] = 0x0e2f8849 # TP_SHIFT_CNT
58 # TP number of RX channels (0 = auto)
59 tp_nrxch = 0
[all …]
/freebsd/sys/dev/usb/net/
H A Dif_axgereg.h29 #define AXGE_ACCESS_MAC 0x01
30 #define AXGE_ACCESS_PHY 0x02
31 #define AXGE_ACCESS_WAKEUP 0x03
32 #define AXGE_ACCESS_EEPROM 0x04
33 #define AXGE_ACCESS_EFUSE 0x05
34 #define AXGE_RELOAD_EEPROM_EFUSE 0x06
35 #define AXGE_FW_MODE 0x08
36 #define AXGE_WRITE_EFUSE_EN 0x09
37 #define AXGE_WRITE_EFUSE_DIS 0x0A
38 #define AXGE_ACCESS_MFAB 0x10
[all …]
/freebsd/sys/dev/iavf/
H A Diavf_register.h35 #define IAVF_VF_ARQBAH1 0x00006000 /* Reset: EMPR */
36 #define IAVF_VF_ARQBAL1 0x00006C00 /* Reset: EMPR */
37 #define IAVF_VF_ARQH1 0x00007400 /* Reset: EMPR */
38 #define IAVF_VF_ARQH1_ARQH_SHIFT 0
39 #define IAVF_VF_ARQH1_ARQH_MASK IAVF_MASK(0x3FF, IAVF_VF_ARQH1_ARQH_SHIFT)
40 #define IAVF_VF_ARQLEN1 0x00008000 /* Reset: EMPR */
49 #define IAVF_VF_ARQT1 0x00007000 /* Reset: EMPR */
50 #define IAVF_VF_ATQBAH1 0x00007800 /* Reset: EMPR */
51 #define IAVF_VF_ATQBAL1 0x00007C00 /* Reset: EMPR */
52 #define IAVF_VF_ATQH1 0x00006400 /* Reset: EMPR */
[all …]
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Domap5-l4.dtsi1 &l4_cfg { /* 0x4a000000 */
4 clocks = <&l4cfg_clkctrl OMAP5_L4_CFG_CLKCTRL 0>;
6 reg = <0x4a000000 0x800>,
7 <0x4a000800 0x800>,
8 <0x4a001000 0x1000>;
12 ranges = <0x00000000 0x4a000000 0x080000>, /* segment 0 */
13 <0x00080000 0x4a080000 0x080000>, /* segment 1 */
14 <0x00100000 0x4a100000 0x080000>, /* segment 2 */
15 <0x00180000 0x4a180000 0x080000>, /* segment 3 */
16 <0x00200000 0x4a200000 0x080000>, /* segment 4 */
[all …]
/freebsd/sys/dev/sound/macio/
H A Ddavbusreg.h36 #define DAVBUS_SOUND_CTRL 0x00
37 #define DAVBUS_CODEC_CTRL 0x10
38 #define DAVBUS_CODEC_STATUS 0x20
39 #define DAVBUS_CLIP_COUNT 0x30
40 #define DAVBUS_BYTE_SWAP 0x40
44 * but the controller itself uses subframe 0 to communicate with the codec.
49 #define DAVBUS_INPUT_SUBFRAME0 0x00000001
50 #define DAVBUS_INPUT_SUBFRAME1 0x00000002
51 #define DAVBUS_INPUT_SUBFRAME2 0x00000004
52 #define DAVBUS_INPUT_SUBFRAME3 0x00000008
[all …]
/freebsd/sys/contrib/device-tree/src/powerpc/
H A Dholly.dts23 #size-cells =<0>;
24 PowerPC,750CL@0 {
26 reg = <0x00000000>;
39 memory@0 {
41 reg = <0x00000000 0x20000000>;
49 ranges = <0x00000000 0xc0000000 0x00010000>;
50 reg = <0xc0000000 0x00010000>;
56 interrupts = <0xe 0x2>;
57 reg = <0x00007000 0x00000400>;
62 reg = <0x00006000 0x00000050>;
[all …]
/freebsd/sys/dev/isci/scil/
H A Dscu_completion_codes.h69 #define SCU_COMPLETION_TYPE_MASK 0x70000000
83 #define SCU_COMPLETION_TYPE_TASK SCU_COMPLETION_TYPE(0)
94 #define SCU_COMPLETION_STATUS_MASK 0x0FFC0000
95 #define SCU_COMPLETION_TL_STATUS_MASK 0x0FC00000
97 #define SCU_COMPLETION_SDMA_STATUS_MASK 0x003C0000
98 #define SCU_COMPLETION_PEG_MASK 0x00010000
99 #define SCU_COMPLETION_PORT_MASK 0x00007000
102 #define SCU_COMPLETION_INDEX_MASK 0x00000FFF
171 #define SCU_UNSOLICITED_FRAME_MASK 0x0FFF0000
184 #define SCU_UNSOLICITED_FRAME_ERROR_MASK 0x00008000
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchLBTInstrInfo.td3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
17 let hasSideEffects = 0, mayLoad = 0, mayStore = 0, Predicates = [HasExtLBT] in {
19 def MOVGR2SCR : FmtGR2SCR<0x00000800>;
20 def MOVSCR2GR : FmtSCR2GR<0x00000c00>;
22 def JISCR0 : FmtJISCR<0x48000200>;
23 def JISCR1 : FmtJISCR<0x48000300>;
25 def ADDU12I_W : ALU_2RI5<0x00290000, simm5>;
27 def ADC_B : ALU_3R<0x00300000>;
28 def ADC_H : ALU_3R<0x00308000>;
29 def ADC_W : ALU_3R<0x00310000>;
[all …]
/freebsd/sys/dev/ath/ath_hal/ar5416/
H A Dar5416desc.h29 #define _get_index(_ah) ( IS_5416V1(_ah) ? -4 : 0 )
68 uint32_t ds_ctl0; /* DMA control 0 */
104 #define AR_FrameLen 0x00000fff
105 #define AR_VirtMoreFrag 0x00001000
106 #define AR_TxCtlRsvd00 0x0000e000
107 #define AR_XmitPower 0x003f0000
109 #define AR_RTSEnable 0x00400000
110 #define AR_VEOL 0x00800000
111 #define AR_ClrDestMask 0x01000000
112 #define AR_TxCtlRsvd01 0x1e000000
[all …]
/freebsd/sys/dev/qat/qat_hw/qat_c4xxx/
H A Dadf_c4xxx_inline.h7 #define ARAM_CSR_BAR_OFFSET 0x100000
8 #define ADF_C4XXX_REG_SA_CTRL_LOCK (ARAM_CSR_BAR_OFFSET + 0x00)
9 #define ADF_C4XXX_REG_SA_SCRATCH_0 (ARAM_CSR_BAR_OFFSET + 0x04)
10 #define ADF_C4XXX_REG_SA_SCRATCH_2 (ARAM_CSR_BAR_OFFSET + 0x0C)
11 #define ADF_C4XXX_REG_SA_ENTRY_CTRL (ARAM_CSR_BAR_OFFSET + 0x18)
12 #define ADF_C4XXX_REG_SA_DB_CTRL (ARAM_CSR_BAR_OFFSET + 0x1C)
13 #define ADF_C4XXX_REG_SA_REMAP (ARAM_CSR_BAR_OFFSET + 0x20)
14 #define ADF_C4XXX_REG_SA_INLINE_CAPABILITY (ARAM_CSR_BAR_OFFSET + 0x24)
15 #define ADF_C4XXX_REG_SA_INLINE_ENABLE (ARAM_CSR_BAR_OFFSET + 0x28)
16 #define ADF_C4XXX_REG_SA_LINK_UP (ARAM_CSR_BAR_OFFSET + 0x2C)
[all …]
/freebsd/sys/contrib/alpine-hal/
H A Dal_hal_pbs_regs.h60 /* [0x0] Conf_bus, Configuration of the SB */
62 /* [0x4] PASW high */
64 /* [0x8] PASW low */
66 /* [0xc] PASW high */
68 /* [0x10] PASW low */
70 /* [0x14] PASW high */
72 /* [0x18] PASW low */
74 /* [0x1c] PASW high */
76 /* [0x20] PASW low */
78 /* [0x24] PASW high */
[all …]
/freebsd/sys/net80211/
H A Dieee80211_radiotap.h70 uint8_t it_version; /* Version 0. Only increases
83 * (0x80000000) to extend the
111 * Tx/Rx data rate. If bit 0x80 is set then it represents an
146 * power set at factory calibration. 0 is max power.
152 * set at factory calibration. 0 is max power. Monotonically
170 * The first antenna is antenna 0.
208 IEEE80211_RADIOTAP_TSFT = 0,
247 #define IEEE80211_CHAN_TURBO 0x00000010 /* Turbo channel */
248 #define IEEE80211_CHAN_CCK 0x00000020 /* CCK channel */
249 #define IEEE80211_CHAN_OFDM 0x0000004
[all...]

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