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/linux/arch/powerpc/include/asm/
H A Dmpic.h14 #define MPIC_GREG_BASE 0x01000
16 #define MPIC_GREG_FEATURE_0 0x00000
17 #define MPIC_GREG_FEATURE_LAST_SRC_MASK 0x07ff0000
19 #define MPIC_GREG_FEATURE_LAST_CPU_MASK 0x00001f00
21 #define MPIC_GREG_FEATURE_VERSION_MASK 0xff
22 #define MPIC_GREG_FEATURE_1 0x00010
23 #define MPIC_GREG_GLOBAL_CONF_0 0x00020
24 #define MPIC_GREG_GCONF_RESET 0x80000000
27 * 0b00 = pass through (interrupts routed to IRQ0)
28 * 0b01 = Mixed mode
[all …]
/linux/arch/parisc/include/uapi/asm/
H A Dtermbits.h42 #define VINTR 0
61 #define IUCLC 0x0200
62 #define IXON 0x0400
63 #define IXOFF 0x1000
64 #define IMAXBEL 0x4000
65 #define IUTF8 0x8000
68 #define OLCUC 0x00002
69 #define ONLCR 0x00004
70 #define NLDLY 0x00100
71 #define NL0 0x00000
[all …]
/linux/include/uapi/asm-generic/
H A Dtermbits.h42 #define VINTR 0
61 #define IUCLC 0x0200
62 #define IXON 0x0400
63 #define IXOFF 0x1000
64 #define IMAXBEL 0x2000
65 #define IUTF8 0x4000
68 #define OLCUC 0x00002
69 #define ONLCR 0x00004
70 #define NLDLY 0x00100
71 #define NL0 0x00000
[all …]
/linux/arch/arm64/boot/dts/amd/
H A Damd-seattle-xgbe-b.dtsi10 reg = <0 0xe0700000 0 0x80000>,
11 <0 0xe0780000 0 0x80000>,
12 <0 0xe1240800 0 0x00400>, /* SERDES RX/TX0 */
13 <0 0xe1250000 0 0x00060>, /* SERDES IR 1/2 */
14 <0 0xe12500f8 0 0x00004>; /* SERDES IR 2/2 */
15 interrupts = <0 325 4>,
16 <0 346 1>, <0 347 1>, <0 348 1>, <0 349 1>,
17 <0 323 4>;
19 amd,speed-set = <0>;
20 amd,serdes-blwc = <1>, <1>, <0>;
[all …]
/linux/drivers/gpu/drm/msm/registers/display/
H A Ddsi_phy_28nm_8960.xml9 <array offset="0x00000" name="LN" length="4" stride="0x40">
10 <reg32 offset="0x00" name="CFG_0"/>
11 <reg32 offset="0x04" name="CFG_1"/>
12 <reg32 offset="0x08" name="CFG_2"/>
13 <reg32 offset="0x0c" name="TEST_DATAPATH"/>
14 <reg32 offset="0x14" name="TEST_STR_0"/>
15 <reg32 offset="0x18" name="TEST_STR_1"/>
18 <reg32 offset="0x00100" name="LNCK_CFG_0"/>
19 <reg32 offset="0x00104" name="LNCK_CFG_1"/>
20 <reg32 offset="0x00108" name="LNCK_CFG_2"/>
[all …]
H A Ddsi_phy_28nm.xml8 <array offset="0x00000" name="LN" length="4" stride="0x40">
9 <reg32 offset="0x00" name="CFG_0"/>
10 <reg32 offset="0x04" name="CFG_1"/>
11 <reg32 offset="0x08" name="CFG_2"/>
12 <reg32 offset="0x0c" name="CFG_3"/>
13 <reg32 offset="0x10" name="CFG_4"/>
14 <reg32 offset="0x14" name="TEST_DATAPATH"/>
15 <reg32 offset="0x18" name="DEBUG_SEL"/>
16 <reg32 offset="0x1c" name="TEST_STR_0"/>
17 <reg32 offset="0x20" name="TEST_STR_1"/>
[all …]
H A Ddsi_phy_20nm.xml8 <array offset="0x00000" name="LN" length="4" stride="0x40">
9 <reg32 offset="0x00" name="CFG_0"/>
10 <reg32 offset="0x04" name="CFG_1"/>
11 <reg32 offset="0x08" name="CFG_2"/>
12 <reg32 offset="0x0c" name="CFG_3"/>
13 <reg32 offset="0x10" name="CFG_4"/>
14 <reg32 offset="0x14" name="TEST_DATAPATH"/>
15 <reg32 offset="0x18" name="DEBUG_SEL"/>
16 <reg32 offset="0x1c" name="TEST_STR_0"/>
17 <reg32 offset="0x20" name="TEST_STR_1"/>
[all …]
H A Ddsi_phy_10nm.xml8 <reg32 offset="0x00000" name="REVISION_ID0"/>
9 <reg32 offset="0x00004" name="REVISION_ID1"/>
10 <reg32 offset="0x00008" name="REVISION_ID2"/>
11 <reg32 offset="0x0000c" name="REVISION_ID3"/>
12 <reg32 offset="0x00010" name="CLK_CFG0"/>
13 <reg32 offset="0x00014" name="CLK_CFG1"/>
14 <reg32 offset="0x00018" name="GLBL_CTRL"/>
15 <reg32 offset="0x0001c" name="RBUF_CTRL"/>
16 <reg32 offset="0x00020" name="VREG_CTRL"/>
17 <reg32 offset="0x00024" name="CTRL_0"/>
[all …]
H A Ddsi_phy_14nm.xml8 <reg32 offset="0x00000" name="REVISION_ID0"/>
9 <reg32 offset="0x00004" name="REVISION_ID1"/>
10 <reg32 offset="0x00008" name="REVISION_ID2"/>
11 <reg32 offset="0x0000c" name="REVISION_ID3"/>
12 <reg32 offset="0x00010" name="CLK_CFG0">
16 <reg32 offset="0x00014" name="CLK_CFG1">
17 <bitfield name="DSICLK_SEL" pos="0" type="boolean"/>
19 <reg32 offset="0x00018" name="GLBL_TEST_CTRL">
22 <reg32 offset="0x0001C" name="CTRL_0"/>
23 <reg32 offset="0x00020" name="CTRL_1">
[all …]
H A Dedp.xml9 <value name="EDP_6BIT" value="0"/>
17 <value name="EDP_RGB" value="0"/>
22 <reg32 offset="0x0004" name="MAINLINK_CTRL">
23 <bitfield name="ENABLE" pos="0" type="boolean"/>
27 <reg32 offset="0x0008" name="STATE_CTRL">
28 <bitfield name="TRAIN_PATTERN_1" pos="0" type="boolean"/>
38 <reg32 offset="0x000c" name="CONFIGURATION_CTRL">
40 <bitfield name="SYNC_CLK" pos="0" type="boolean"/>
52 <reg32 offset="0x0014" name="SOFTWARE_MVID" type="uint"/>
53 <reg32 offset="0x0018" name="SOFTWARE_NVID" type="uint"/>
[all …]
/linux/arch/mips/include/uapi/asm/
H A Dtermbits.h55 #define VINTR 0 /* Interrupt character [ISIG] */
67 #if 0
81 #define IUCLC 0x0200 /* Map upper case to lower case on input */
82 #define IXON 0x0400 /* Enable start/stop output control */
83 #define IXOFF 0x1000 /* Enable start/stop input control */
84 #define IMAXBEL 0x2000 /* Ring bell when input queue is full */
85 #define IUTF8 0x4000 /* Input is UTF-8 */
88 #define OLCUC 0x00002 /* Map lower case to upper case on output */
89 #define ONLCR 0x00004 /* Map NL to CR-NL on output */
90 #define NLDLY 0x00100
[all …]
/linux/drivers/gpu/drm/arm/
H A Dmalidp_regs.h20 #define MALIDP_DE_IRQ_UNDERRUN (1 << 0)
34 #define MALIDP500_SE_IRQ_CONF_MODE (1 << 0)
50 #define MALIDP550_SE_IRQ_EOW (1 << 0)
54 #define MALIDP550_DC_IRQ_CONF_VALID (1 << 0)
67 #define MALIDP_CFG_VALID (1 << 0)
68 #define MALIDP_DISP_FUNC_GAMMA (1 << 0)
75 #define MALIDP_REG_STATUS 0x00000
76 #define MALIDP_REG_SETIRQ 0x00004
77 #define MALIDP_REG_MASKIRQ 0x00008
78 #define MALIDP_REG_CLEARIRQ 0x0000c
[all …]
/linux/arch/powerpc/include/uapi/asm/
H A Dtermbits.h48 #define VINTR 0
67 #define IXON 0x0200
68 #define IXOFF 0x0400
69 #define IUCLC 0x1000
70 #define IMAXBEL 0x2000
71 #define IUTF8 0x4000
74 #define ONLCR 0x00002
75 #define OLCUC 0x00004
76 #define NLDLY 0x00300
77 #define NL0 0x00000
[all …]
/linux/arch/alpha/include/uapi/asm/
H A Dtermbits.h54 #define VEOF 0
73 #define IXON 0x0200
74 #define IXOFF 0x0400
75 #define IUCLC 0x1000
76 #define IMAXBEL 0x2000
77 #define IUTF8 0x4000
80 #define ONLCR 0x00002
81 #define OLCUC 0x00004
82 #define NLDLY 0x00300
83 #define NL0 0x00000
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/
H A Dvmmnv04.c31 u32 data = addr | 0x00000003; /* PRESENT, RW. */ in nv04_vmm_pgt_pte()
34 data += 0x00001000; in nv04_vmm_pgt_pte()
52 VMM_WO032(pt, vmm, 8 + (ptei++ * 4), *map->dma++ | 0x00000003); in nv04_vmm_pgt_dma()
63 VMM_FO032(pt, vmm, 8 + (ptei * 4), 0, ptes); in nv04_vmm_pgt_unmap()
75 { PGT, 15, 4, 0x1000, &nv04_vmm_desc_pgt },
96 { 12, &nv04_vmm_desc_12[0], NVKM_VMM_PAGE_HOST },
135 mem = vmm->pd->pt[0]->memory; in nv04_vmm_new()
137 nvkm_wo32(mem, 0x00000, 0x0002103d); /* PCI, RW, PT, !LN */ in nv04_vmm_new()
138 nvkm_wo32(mem, 0x00004, vmm->limit - 1); in nv04_vmm_new()
140 return 0; in nv04_vmm_new()
/linux/arch/x86/include/asm/
H A Dapicdef.h14 #define IO_APIC_DEFAULT_PHYS_BASE 0xfec00000
15 #define APIC_DEFAULT_PHYS_BASE 0xfee00000
23 #define APIC_DELIVERY_MODE_FIXED 0
30 #define APIC_ID 0x20
32 #define APIC_LVR 0x30
33 #define APIC_LVR_MASK 0xFF00FF
35 #define GET_APIC_VERSION(x) ((x) & 0xFFu)
36 #define GET_APIC_MAXLVT(x) (((x) >> 16) & 0xFFu)
38 # define APIC_INTEGRATED(x) ((x) & 0xF0u)
42 #define APIC_XAPIC(x) ((x) >= 0x14)
[all …]
/linux/arch/riscv/boot/dts/thead/
H A Dth1520.dtsi19 #size-cells = <0>;
22 c910_0: cpu@0 {
32 reg = <0>;
143 <0x00003 0x00003 0x0007fff8>,
144 <0x00004 0x00004 0x0007fff8>,
145 <0x00005 0x00005 0x0007fff8>,
146 <0x00006 0x00006 0x0007fff8>,
147 <0x00007 0x00007 0x0007fff8>,
148 <0x00008 0x00008 0x0007fff8>,
149 <0x00009 0x00009 0x0007fff8>,
[all …]
/linux/Documentation/devicetree/bindings/perf/
H A Driscv,pmu.yaml78 value of variant must be 0xffffffff_ffffffff.
104 riscv,event-to-mhpmevent = <0x0000B 0x0000 0x0001>;
105 riscv,event-to-mhpmcounters = <0x00001 0x00001 0x00000001>,
106 <0x00002 0x00002 0x00000004>,
107 <0x00003 0x0000A 0x00000ff8>,
108 <0x10000 0x10033 0x000ff000>;
110 /* For event ID 0x0002 */
111 <0x0000 0x0002 0xffffffff 0xffffffff 0x00000f8>,
112 /* For event ID 0-4 */
113 <0x0 0x0 0xffffffff 0xfffffff0 0x00000ff0>,
[all …]
/linux/drivers/net/wireless/realtek/rtw89/
H A Drtw8851b_rfk_table.c8 RTW89_DECL_RFK_WM(0xc210, 0x003fc000, 0x80),
9 RTW89_DECL_RFK_WM(0xc224, 0x003fc000, 0x80),
10 RTW89_DECL_RFK_WM(0xc0f8, 0x30000000, 0x3),
11 RTW89_DECL_RFK_WM(0x12b8, BIT(30), 0x1),
12 RTW89_DECL_RFK_WM(0x030c, 0x1f000000, 0x1f),
13 RTW89_DECL_RFK_WM(0x032c, 0xc0000000, 0x0),
14 RTW89_DECL_RFK_WM(0x032c, BIT(22), 0x0),
15 RTW89_DECL_RFK_WM(0x032c, BIT(22), 0x1),
16 RTW89_DECL_RFK_WM(0x032c, BIT(16), 0x0),
17 RTW89_DECL_RFK_WM(0x032c, BIT(20), 0x1),
[all …]
/linux/drivers/usb/gadget/udc/
H A Dgoku_udc.h12 * PCI BAR 0 points to these registers.
16 u32 int_status; /* 0x000 */
18 #define INT_SUSPEND 0x00001 /* or resume */
19 #define INT_USBRESET 0x00002
20 #define INT_ENDPOINT0 0x00004
21 #define INT_SETUP 0x00008
22 #define INT_STATUS 0x00010
23 #define INT_STATUSNAK 0x00020
24 #define INT_EPxDATASET(n) (0x00020 << (n)) /* 0 < n < 4 */
25 # define INT_EP1DATASET 0x00040
[all …]
/linux/drivers/scsi/ibmvscsi_tgt/
H A Dibmvscsi_tgt.h27 #define MSG_HI 0
36 #define SRP_VIOLATION 0x102 /* general error code */
55 #define LOCAL 0
70 #define ADAPT_SUCCESS 0L
139 SCSI_CDB = 0x01,
140 TASK_MANAGEMENT = 0x02,
141 /* MAD or addressed to port 0 */
142 ADAPTER_MAD = 0x04,
143 UNSET_TYPE = 0x08,
166 #define CMD_FAST_FAIL BIT(0)
[all …]
/linux/include/uapi/linux/
H A Dmedia.h48 #define MEDIA_ENT_F_BASE 0x00000000
49 #define MEDIA_ENT_F_OLD_BASE 0x00010000
50 #define MEDIA_ENT_F_OLD_SUBDEV_BASE 0x00020000
68 #define MEDIA_ENT_F_DTV_DEMOD (MEDIA_ENT_F_BASE + 0x00001)
69 #define MEDIA_ENT_F_TS_DEMUX (MEDIA_ENT_F_BASE + 0x00002)
70 #define MEDIA_ENT_F_DTV_CA (MEDIA_ENT_F_BASE + 0x00003)
71 #define MEDIA_ENT_F_DTV_NET_DECAP (MEDIA_ENT_F_BASE + 0x00004)
77 #define MEDIA_ENT_F_IO_DTV (MEDIA_ENT_F_BASE + 0x01001)
78 #define MEDIA_ENT_F_IO_VBI (MEDIA_ENT_F_BASE + 0x01002)
79 #define MEDIA_ENT_F_IO_SWRADIO (MEDIA_ENT_F_BASE + 0x01003)
[all …]
/linux/drivers/scsi/aic7xxx/
H A Daic79xx.h60 #define FALSE 0
63 #define ALL_CHANNELS '\0'
64 #define ALL_TARGETS_MASK 0xFFFF
65 #define INITIATOR_WILDCARD (~0)
66 #define SCB_LIST_NULL 0xFF00
68 #define QOUTFIFO_ENTRY_VALID 0x80
69 #define SCBID_IS_NULL(scbid) (((scbid) & 0xFF00 ) == SCB_LIST_NULL)
76 #define SCB_IS_SCSIBUS_B(ahd, scb) (0)
88 (0x01 << (SCB_GET_TARGET_OFFSET(ahd, scb)))
91 ((ahd_debug & AHD_SHOW_MASKED_ERRORS) == 0 \
[all …]
/linux/drivers/net/ethernet/hisilicon/hns3/
H A Dhns3_enet.h35 #define HNS3_RING_RX_RING_BASEADDR_L_REG 0x00000
36 #define HNS3_RING_RX_RING_BASEADDR_H_REG 0x00004
37 #define HNS3_RING_RX_RING_BD_NUM_REG 0x00008
38 #define HNS3_RING_RX_RING_BD_LEN_REG 0x0000C
39 #define HNS3_RING_RX_RING_TAIL_REG 0x00018
40 #define HNS3_RING_RX_RING_HEAD_REG 0x0001C
41 #define HNS3_RING_RX_RING_FBDNUM_REG 0x00020
42 #define HNS3_RING_RX_RING_PKTNUM_RECORD_REG 0x0002C
44 #define HNS3_RING_TX_RING_BASEADDR_L_REG 0x00040
45 #define HNS3_RING_TX_RING_BASEADDR_H_REG 0x00044
[all …]
/linux/drivers/net/ethernet/dec/tulip/
H A Dtulip.h36 #define TULIP_BAR 0 /* CBIO */
52 HAS_MII = 0x00001,
53 HAS_MEDIA_TABLE = 0x00002,
54 CSR12_IN_SROM = 0x00004,
55 ALWAYS_CHECK_MII = 0x00008,
56 HAS_ACPI = 0x00010,
57 MC_HASH_ONLY = 0x00020, /* Hash-only multicast filter. */
58 HAS_PNICNWAY = 0x00080,
59 HAS_NWAY = 0x00040, /* Uses internal NWay xcvr. */
60 HAS_INTR_MITIGATION = 0x00100,
[all …]

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