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/linux/arch/sh/mm/
H A Dcache-sh2.c27 unsigned long addr = CACHE_OC_ADDRESS_ARRAY | (v & 0x00000ff0); in sh2__flush_wback_region()
29 for (way = 0; way < 4; way++) { in sh2__flush_wback_region()
50 CACHE_OC_ADDRESS_ARRAY | (v & 0x00000ff0) | 0x00000008); in sh2__flush_purge_region()
81 CACHE_OC_ADDRESS_ARRAY | (v & 0x00000ff0) | 0x00000008); in sh2__flush_invalidate_region()
/linux/drivers/gpu/drm/nouveau/include/nvhw/class/
H A Dcl907d.h27 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4 0x00000004
28 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE 0:0
29 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_FALSE 0x00000000
30 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_TRUE 0x00000001
31 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20 0x00000014
32 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18 0:0
33 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_FALSE 0x00000000
34 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_TRUE 0x00000001
36 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_FALSE 0x00000000
37 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_TRUE 0x00000001
[all …]
/linux/Documentation/devicetree/bindings/perf/
H A Driscv,pmu.yaml78 value of variant must be 0xffffffff_ffffffff.
104 riscv,event-to-mhpmevent = <0x0000B 0x0000 0x0001>;
105 riscv,event-to-mhpmcounters = <0x00001 0x00001 0x00000001>,
106 <0x00002 0x00002 0x00000004>,
107 <0x00003 0x0000A 0x00000ff8>,
108 <0x10000 0x10033 0x000ff000>;
110 /* For event ID 0x0002 */
111 <0x0000 0x0002 0xffffffff 0xffffffff 0x00000f8>,
112 /* For event ID 0-4 */
113 <0x0 0x0 0xffffffff 0xfffffff0 0x00000ff0>,
[all …]
/linux/drivers/char/agp/
H A Dali-agp.c13 #define ALI_AGPCTRL 0xb8
14 #define ALI_ATTBASE 0xbc
15 #define ALI_TLBCTRL 0xc0
16 #define ALI_TAGCTRL 0xc4
17 #define ALI_CACHE_FLUSH_CTRL 0xD0
18 #define ALI_CACHE_FLUSH_ADDR_MASK 0xFFFFF000
19 #define ALI_CACHE_FLUSH_EN 0x100
28 temp &= ~(0xfffffff0); in ali_fetch_size()
31 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { in ali_fetch_size()
40 return 0; in ali_fetch_size()
[all …]
/linux/drivers/net/wireless/ti/wl1251/
H A Dwl12xx_80211.h8 #define IEEE80211_CCK_RATE_1MB 0x02
9 #define IEEE80211_CCK_RATE_2MB 0x04
10 #define IEEE80211_CCK_RATE_5MB 0x0B
11 #define IEEE80211_CCK_RATE_11MB 0x16
12 #define IEEE80211_OFDM_RATE_6MB 0x0C
13 #define IEEE80211_OFDM_RATE_9MB 0x12
14 #define IEEE80211_OFDM_RATE_12MB 0x18
15 #define IEEE80211_OFDM_RATE_18MB 0x24
16 #define IEEE80211_OFDM_RATE_24MB 0x30
17 #define IEEE80211_OFDM_RATE_36MB 0x48
[all …]
/linux/drivers/net/wireless/ti/wlcore/
H A Dwl12xx_80211.h9 #define IEEE80211_CCK_RATE_1MB 0x02
10 #define IEEE80211_CCK_RATE_2MB 0x04
11 #define IEEE80211_CCK_RATE_5MB 0x0B
12 #define IEEE80211_CCK_RATE_11MB 0x16
13 #define IEEE80211_OFDM_RATE_6MB 0x0C
14 #define IEEE80211_OFDM_RATE_9MB 0x12
15 #define IEEE80211_OFDM_RATE_12MB 0x18
16 #define IEEE80211_OFDM_RATE_18MB 0x24
17 #define IEEE80211_OFDM_RATE_24MB 0x30
18 #define IEEE80211_OFDM_RATE_36MB 0x48
[all …]
/linux/drivers/net/ethernet/aquantia/atlantic/hw_atl/
H A Dhw_atl_b0_internal.h26 #define HW_ATL_B0_MAC 0U
36 #define HW_ATL_B0_INT_MASK (0xFFFFFFFFU)
38 #define HW_ATL_B0_TXD_CTL2_LEN (0xFFFFC000)
39 #define HW_ATL_B0_TXD_CTL2_CTX_EN (0x00002000)
40 #define HW_ATL_B0_TXD_CTL2_CTX_IDX (0x00001000)
42 #define HW_ATL_B0_TXD_CTL_DESC_TYPE_TXD (0x00000001)
43 #define HW_ATL_B0_TXD_CTL_DESC_TYPE_TXC (0x00000002)
44 #define HW_ATL_B0_TXD_CTL_BLEN (0x000FFFF0)
45 #define HW_ATL_B0_TXD_CTL_DD (0x00100000)
46 #define HW_ATL_B0_TXD_CTL_EOP (0x00200000)
[all …]
/linux/drivers/scsi/qedi/
H A Dqedi_nvm_iscsi_cfg.h37 union nvm_iscsi_ipv4_addr addr; /* 0x0 */
38 union nvm_iscsi_ipv4_addr subnet_mask; /* 0x4 */
39 union nvm_iscsi_ipv4_addr gateway; /* 0x8 */
40 union nvm_iscsi_ipv4_addr primary_dns; /* 0xC */
41 union nvm_iscsi_ipv4_addr secondary_dns; /* 0x10 */
42 union nvm_iscsi_ipv4_addr dhcp_addr; /* 0x14 */
44 union nvm_iscsi_ipv4_addr isns_server; /* 0x18 */
45 union nvm_iscsi_ipv4_addr slp_server; /* 0x1C */
46 union nvm_iscsi_ipv4_addr primay_radius_server; /* 0x20 */
47 union nvm_iscsi_ipv4_addr secondary_radius_server; /* 0x24 */
[all …]
/linux/drivers/dma/
H A Dfsldma.h19 #define FSL_DMA_MR_CS 0x00000001
20 #define FSL_DMA_MR_CC 0x00000002
21 #define FSL_DMA_MR_CA 0x00000008
22 #define FSL_DMA_MR_EIE 0x00000040
23 #define FSL_DMA_MR_XFE 0x00000020
24 #define FSL_DMA_MR_EOLNIE 0x00000100
25 #define FSL_DMA_MR_EOLSIE 0x00000080
26 #define FSL_DMA_MR_EOSIE 0x00000200
27 #define FSL_DMA_MR_CDSM 0x00000010
28 #define FSL_DMA_MR_CTM 0x00000004
[all …]
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8192d/
H A Dhw_common.c24 rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xff); in rtl92d_stop_tx_beacon()
25 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64); in rtl92d_stop_tx_beacon()
27 tmp1byte &= ~(BIT(0)); in rtl92d_stop_tx_beacon()
39 rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0x0a); in rtl92d_resume_tx_beacon()
40 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); in rtl92d_resume_tx_beacon()
42 tmp1byte |= BIT(0); in rtl92d_resume_tx_beacon()
66 val_rcr &= 0x00070000; in rtl92d_get_hw_reg()
113 for (idx = 0; idx < ETH_ALEN; idx++) { in rtl92d_set_hw_reg()
119 u16 rate_cfg = ((u16 *)val)[0]; in rtl92d_set_hw_reg()
120 u8 rate_index = 0; in rtl92d_set_hw_reg()
[all …]
/linux/drivers/gpu/drm/mcde/
H A Dmcde_dsi_regs.h5 #define DSI_MCTL_INTEGRATION_MODE 0x00000000
7 #define DSI_MCTL_MAIN_DATA_CTL 0x00000004
8 #define DSI_MCTL_MAIN_DATA_CTL_LINK_EN BIT(0)
25 #define DSI_MCTL_MAIN_PHY_CTL 0x00000008
26 #define DSI_MCTL_MAIN_PHY_CTL_LANE2_EN BIT(0)
33 #define DSI_MCTL_MAIN_PHY_CTL_WAIT_BURST_TIME_MASK 0x000003C0
36 #define DSI_MCTL_PLL_CTL 0x0000000C
37 #define DSI_MCTL_LANE_STS 0x00000010
39 #define DSI_MCTL_DPHY_TIMEOUT 0x00000014
40 #define DSI_MCTL_DPHY_TIMEOUT_CLK_DIV_SHIFT 0
[all …]
/linux/arch/arm/boot/dts/ti/davinci/
H A Dda850-lcdk.dts24 /* 128 MB DDR2 SDRAM @ 0xc0000000 */
25 reg = <0xc0000000 0x08000000>;
35 reg = <0xc3000000 0x1000000>;
122 #size-cells = <0>;
126 #size-cells = <0>;
128 port@0 {
129 reg = <0>;
205 0x00 0x00101010 0x00f0f0f0
207 0x04 0x00000110 0x00000ff0
213 /* EMA_WAIT[0], EMA_OE, EMA_WE, EMA_CS[3] */
[all …]
/linux/drivers/scsi/bfa/
H A Dbfi_reg.h18 #define HOSTFN0_INT_STATUS 0x00014000 /* cb/ct */
19 #define HOSTFN1_INT_STATUS 0x00014100 /* cb/ct */
20 #define HOSTFN2_INT_STATUS 0x00014300 /* ct */
21 #define HOSTFN3_INT_STATUS 0x00014400 /* ct */
22 #define HOSTFN0_INT_MSK 0x00014004 /* cb/ct */
23 #define HOSTFN1_INT_MSK 0x00014104 /* cb/ct */
24 #define HOSTFN2_INT_MSK 0x00014304 /* ct */
25 #define HOSTFN3_INT_MSK 0x00014404 /* ct */
27 #define HOST_PAGE_NUM_FN0 0x00014008 /* cb/ct */
28 #define HOST_PAGE_NUM_FN1 0x00014108 /* cb/ct */
[all …]
/linux/drivers/net/ethernet/brocade/bna/
H A Dbfi_reg.h19 #define HOSTFN0_INT_STATUS 0x00014000 /* cb/ct */
20 #define HOSTFN1_INT_STATUS 0x00014100 /* cb/ct */
21 #define HOSTFN2_INT_STATUS 0x00014300 /* ct */
22 #define HOSTFN3_INT_STATUS 0x00014400 /* ct */
23 #define HOSTFN0_INT_MSK 0x00014004 /* cb/ct */
24 #define HOSTFN1_INT_MSK 0x00014104 /* cb/ct */
25 #define HOSTFN2_INT_MSK 0x00014304 /* ct */
26 #define HOSTFN3_INT_MSK 0x00014404 /* ct */
28 #define HOST_PAGE_NUM_FN0 0x00014008 /* cb/ct */
29 #define HOST_PAGE_NUM_FN1 0x00014108 /* cb/ct */
[all …]
/linux/drivers/scsi/
H A D3w-xxxx.h62 [0x000] = "INFO: AEN queue empty",
63 [0x001] = "INFO: Soft reset occurred",
64 [0x002] = "ERROR: Unit degraded: Unit #",
65 [0x003] = "ERROR: Controller error",
66 [0x004] = "ERROR: Rebuild failed: Unit #",
67 [0x005] = "INFO: Rebuild complete: Unit #",
68 [0x006] = "ERROR: Incomplete unit detected: Unit #",
69 [0x007] = "INFO: Initialization complete: Unit #",
70 [0x008] = "WARNING: Unclean shutdown detected: Unit #",
71 [0x009] = "WARNING: ATA port timeout: Port #",
[all …]
/linux/drivers/staging/rtl8723bs/hal/
H A Dodm.c13 0x0b40002d, /* 0, -15.0dB */
14 0x0c000030, /* 1, -14.5dB */
15 0x0cc00033, /* 2, -14.0dB */
16 0x0d800036, /* 3, -13.5dB */
17 0x0e400039, /* 4, -13.0dB */
18 0x0f00003c, /* 5, -12.5dB */
19 0x10000040, /* 6, -12.0dB */
20 0x11000044, /* 7, -11.5dB */
21 0x12000048, /* 8, -11.0dB */
22 0x1300004c, /* 9, -10.5dB */
[all …]
/linux/drivers/net/ethernet/intel/e1000e/
H A Ddefines.h13 #define E1000_WUC_APME 0x00000001 /* APM Enable */
14 #define E1000_WUC_PME_EN 0x00000002 /* PME Enable */
15 #define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */
16 #define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */
17 #define E1000_WUC_PHY_WAKE 0x00000100 /* if PHY supports wakeup */
20 #define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
21 #define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
22 #define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
23 #define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
24 #define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
[all …]
/linux/drivers/ata/
H A Dpata_sis.c56 { 0x5513, 0x1043, 0x1107 }, /* ASUS A6K */
57 { 0x5513, 0x1734, 0x105F }, /* FSC Amilo A1630 */
58 { 0x5513, 0x1071, 0x8640 }, /* EasyNote K5305 */
60 { 0, }
65 const struct sis_laptop *lap = &sis_laptop[0]; in sis_short_ata40()
75 return 0; in sis_short_ata40()
88 return 0x40 + (4 * adev->link->ap->port_no) + (2 * adev->devno); in sis_old_port_base()
103 int port = 0x40; in sis_port_base()
106 /* If bit 30 is set then the registers are mapped at 0x70 not 0x40 */ in sis_port_base()
107 pci_read_config_dword(pdev, 0x54, &reg54); in sis_port_base()
[all …]
/linux/drivers/net/wireless/intel/ipw2x00/
H A Dlibipw.h53 #define LIBIPW_QCTL_TID 0x000F
61 printk(KERN_DEBUG "libipw: %s " fmt, __func__ , ## args); } while (0)
63 #define LIBIPW_DEBUG(level, fmt, args...) do {} while (0)
92 #define LIBIPW_DL_INFO (1<<0)
125 #define ETH_P_PREAUTH 0x88C7 /* IEEE 802.11i pre-authentication */
137 u8 dsap; /* always 0xAA */
138 u8 ssap; /* always 0xAA */
139 u8 ctrl; /* always 0x03 */
153 #define LIBIPW_STATMASK_SIGNAL (1<<0)
157 #define LIBIPW_STATMASK_WEMASK 0x7
[all …]
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/
H A Dhw.c46 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64); in _rtl8723e_stop_tx_beacon()
48 tmp1byte &= ~(BIT(0)); in _rtl8723e_stop_tx_beacon()
59 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); in _rtl8723e_resume_tx_beacon()
67 _rtl8723e_set_bcn_ctrl_reg(hw, 0, BIT(1)); in _rtl8723e_enable_bcn_sub_func()
72 _rtl8723e_set_bcn_ctrl_reg(hw, BIT(1), 0); in _rtl8723e_disable_bcn_sub_func()
99 val_rcr &= 0x00070000; in rtl8723e_get_hw_reg()
142 for (idx = 0; idx < ETH_ALEN; idx++) { in rtl8723e_set_hw_reg()
149 u16 b_rate_cfg = ((u16 *)val)[0]; in rtl8723e_set_hw_reg()
150 u8 rate_index = 0; in rtl8723e_set_hw_reg()
152 b_rate_cfg = b_rate_cfg & 0x15f; in rtl8723e_set_hw_reg()
[all …]
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8192ce/
H A Dhw.c42 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64); in _rtl92ce_stop_tx_beacon()
44 tmp1byte &= ~(BIT(0)); in _rtl92ce_stop_tx_beacon()
55 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); in _rtl92ce_resume_tx_beacon()
57 tmp1byte |= BIT(0); in _rtl92ce_resume_tx_beacon()
63 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(1)); in _rtl92ce_enable_bcn_sub_func()
68 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(1), 0); in _rtl92ce_disable_bcn_sub_func()
95 val_rcr &= 0x00070000; in rtl92ce_get_hw_reg()
138 for (idx = 0; idx < ETH_ALEN; idx++) { in rtl92ce_set_hw_reg()
145 u16 rate_cfg = ((u16 *) val)[0]; in rtl92ce_set_hw_reg()
146 u8 rate_index = 0; in rtl92ce_set_hw_reg()
[all …]
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8192cu/
H A Dhw.c107 for (rf_path = 0; rf_path < 2; rf_path++) { in _rtl92cu_read_txpower_info_from_hwpg()
108 for (i = 0; i < 3; i++) { in _rtl92cu_read_txpower_info_from_hwpg()
127 for (i = 0; i < 3; i++) { in _rtl92cu_read_txpower_info_from_hwpg()
133 (tempval & 0xf); in _rtl92cu_read_txpower_info_from_hwpg()
135 ((tempval & 0xf0) >> 4); in _rtl92cu_read_txpower_info_from_hwpg()
137 for (rf_path = 0; rf_path < 2; rf_path++) in _rtl92cu_read_txpower_info_from_hwpg()
138 for (i = 0; i < 3; i++) in _rtl92cu_read_txpower_info_from_hwpg()
140 "RF(%d) EEPROM CCK Area(%d) = 0x%x\n", in _rtl92cu_read_txpower_info_from_hwpg()
144 for (rf_path = 0; rf_path < 2; rf_path++) in _rtl92cu_read_txpower_info_from_hwpg()
145 for (i = 0; i < 3; i++) in _rtl92cu_read_txpower_info_from_hwpg()
[all …]
/linux/drivers/net/ethernet/intel/igc/
H A Digc_defines.h13 #define IGC_CTRL_EXT_SDP2_DIR 0x00000400 /* SDP2 Data direction */
14 #define IGC_CTRL_EXT_SDP3_DIR 0x00000800 /* SDP3 Data direction */
15 #define IGC_CTRL_EXT_DRV_LOAD 0x10000000 /* Drv loaded bit for FW */
19 #define IGC_WUC_PME_EN 0x00000002 /* PME Enable */
22 #define IGC_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
23 #define IGC_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
24 #define IGC_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
25 #define IGC_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
26 #define IGC_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
28 #define IGC_WUFC_FLX0 BIT(16) /* Flexible Filter 0 Enable */
[all …]
/linux/drivers/net/ethernet/broadcom/
H A Dtg3.h17 #define TG3_64BIT_REG_HIGH 0x00UL
18 #define TG3_64BIT_REG_LOW 0x04UL
21 #define TG3_BDINFO_HOST_ADDR 0x0UL /* 64-bit */
22 #define TG3_BDINFO_MAXLEN_FLAGS 0x8UL /* 32-bit */
23 #define BDINFO_FLAGS_USE_EXT_RECV 0x00000001 /* ext rx_buffer_desc */
24 #define BDINFO_FLAGS_DISABLED 0x00000002
25 #define BDINFO_FLAGS_MAXLEN_MASK 0xffff0000
27 #define TG3_BDINFO_NIC_ADDR 0xcUL /* 32-bit */
28 #define TG3_BDINFO_SIZE 0x10UL
41 #define TG3PCI_VENDOR 0x00000000
[all …]
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8192se/
H A Dhw.c73 rtl_write_dword(rtlpriv, IDR0, ((u32 *)(val))[0]); in rtl92se_set_hw_reg()
74 rtl_write_word(rtlpriv, IDR4, ((u16 *)(val + 4))[0]); in rtl92se_set_hw_reg()
78 u16 rate_cfg = ((u16 *) val)[0]; in rtl92se_set_hw_reg()
79 u8 rate_index = 0; in rtl92se_set_hw_reg()
82 rate_cfg = rate_cfg & 0x150; in rtl92se_set_hw_reg()
84 rate_cfg = rate_cfg & 0x15f; in rtl92se_set_hw_reg()
86 rate_cfg |= 0x01; in rtl92se_set_hw_reg()
88 rtl_write_byte(rtlpriv, RRSR, rate_cfg & 0xff); in rtl92se_set_hw_reg()
90 (rate_cfg >> 8) & 0xff); in rtl92se_set_hw_reg()
92 while (rate_cfg > 0x1) { in rtl92se_set_hw_reg()
[all …]

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